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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [Processor.v.bak] - Blame information for rev 2

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1 2 lucas.vbal
// Copyright (C) 2017  Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions
3
// and other software and tools, and its AMPP partner logic
4
// functions, and any output files from any of the foregoing
5
// (including device programming or simulation files), and any
6
// associated documentation or information are expressly subject
7
// to the terms and conditions of the Intel Program License
8
// Subscription Agreement, the Intel Quartus Prime License Agreement,
9
// the Intel MegaCore Function License Agreement, or other
10
// applicable license agreement, including, without limitation,
11
// that your use is for the sole purpose of programming logic
12
// devices manufactured by Intel and sold by Intel or its
13
// authorized distributors.  Please refer to the applicable
14
// agreement for further details.
15
 
16
// PROGRAM              "Quartus Prime"
17
// VERSION              "Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition"
18
// CREATED              "Sun Jul 15 21:43:10 2018"
19
 
20
module Processor(
21
        clock,
22
        reset,
23
        testbench_vsync,
24
        testbench_PLL_clock,
25
        six_button_UP_Z,
26
        six_button_DOWN_Y,
27
        six_button_LEFT_X,
28
        six_button_RIGHT_MODE,
29
        six_button_B_A,
30
        six_button_C_START,
31
        SRAM_DQ,
32
        add_overflow,
33
        sub_overflow,
34
        compare_aeb,
35
        compare_agb,
36
        compare_alb,
37
        arbiter_grant_1,
38
        arbiter_grant_2,
39
        arbiter_grant_3,
40
        arbiter_wren,
41
        cpu_ram_wren,
42
        cpu_ram_req,
43
        cpu_const_bool,
44
        pic_mem_wren,
45
        pic_mem_req,
46
        pic_cpu_req,
47
        cpu_int_ack,
48
        pic_int_ack_0,
49
        cpu_v_sync_flag,
50
        VGA_CLK,
51
        VGA_HS,
52
        VGA_VS,
53
        VGA_BLANK,
54
        six_button_mem_wren,
55
        six_button_mem_req,
56
        six_button_v_sync_flag,
57
        six_button_int_req,
58
        SRAM_UB_N,
59
        SRAM_LB_N,
60
        SRAM_CE_N,
61
        SRAM_OE_N,
62
        SRAM_WE_N,
63
        arbiter_grant_0,
64
        sprite_reader_mem_wren,
65
        sprite_reader_mem_req,
66
        sprite_reader_line_flag,
67
        sprite_reader_cpu_sleep,
68
        six_button_SELECT,
69
        button_up,
70
        button_down,
71
        button_left,
72
        button_right,
73
        button_b,
74
        button_c,
75
        button_a,
76
        button_start,
77
        button_z,
78
        button_y,
79
        button_x,
80
        VGA_SYNC,
81
        add_result,
82
        arbiter_addr,
83
        arbiter_current_state,
84
        arbiter_data,
85
        arbiter_next_state,
86
        cpu_current_state,
87
        cpu_imm,
88
        cpu_int_program_counter,
89
        cpu_int_rflags,
90
        cpu_next_state,
91
        cpu_opcode,
92
        cpu_pc_stack,
93
        cpu_pc_stack_val,
94
        cpu_program_counter,
95
        cpu_ram_addr,
96
        cpu_ram_data,
97
        cpu_reg_a_num,
98
        cpu_reg_a_val,
99
        cpu_reg_b_num,
100
        cpu_reg_b_val,
101
        cpu_reg_c_num,
102
        cpu_reg_c_val,
103
        cpu_registers,
104
        cpu_rflags,
105
        cpu_rflags_index,
106
        cpu_rom_addr,
107
        cpu_sprite_color,
108
        cpu_sprite_id,
109
        cpu_sprite_level,
110
        cpu_sprite_x,
111
        cpu_sprite_y,
112
        cpu_stack_pointer,
113
        divide_quotient,
114
        divide_remain,
115
        mult_result,
116
        pic_current_state,
117
        pic_int_mask,
118
        pic_isr_addr,
119
        pic_mem_addr,
120
        pic_next_state,
121
        ram_q,
122
        rom_q,
123
        six_button_buttons,
124
        six_button_counter,
125
        six_button_current_state,
126
        six_button_mem_addr,
127
        six_button_mem_data,
128
        six_button_next_state,
129
        sprite_reader_EstadoAtual,
130
        sprite_reader_EstadoFuturo,
131
        sprite_reader_level_counter,
132
        sprite_reader_level_sprite_id,
133
        sprite_reader_level_sprite_y,
134
        sprite_reader_mem_addr,
135
        SRAM_ADDR,
136
        sub_result,
137
        VGA_B,
138
        VGA_G,
139
        VGA_h_pos,
140
        VGA_oAddress,
141
        VGA_R,
142
        VGA_v_pos
143
);
144
 
145
 
146
input wire      clock;
147
input wire      reset;
148
input wire      testbench_vsync;
149
input wire      testbench_PLL_clock;
150
input wire      six_button_UP_Z;
151
input wire      six_button_DOWN_Y;
152
input wire      six_button_LEFT_X;
153
input wire      six_button_RIGHT_MODE;
154
input wire      six_button_B_A;
155
input wire      six_button_C_START;
156
input wire      [15:0] SRAM_DQ;
157
output wire     add_overflow;
158
output wire     sub_overflow;
159
output wire     compare_aeb;
160
output wire     compare_agb;
161
output wire     compare_alb;
162
output wire     arbiter_grant_1;
163
output wire     arbiter_grant_2;
164
output wire     arbiter_grant_3;
165
output wire     arbiter_wren;
166
output wire     cpu_ram_wren;
167
output wire     cpu_ram_req;
168
output wire     cpu_const_bool;
169
output wire     pic_mem_wren;
170
output wire     pic_mem_req;
171
output wire     pic_cpu_req;
172
output wire     cpu_int_ack;
173
output wire     pic_int_ack_0;
174
output wire     cpu_v_sync_flag;
175
output wire     VGA_CLK;
176
output wire     VGA_HS;
177
output wire     VGA_VS;
178
output wire     VGA_BLANK;
179
output wire     six_button_mem_wren;
180
output wire     six_button_mem_req;
181
output wire     six_button_v_sync_flag;
182
output wire     six_button_int_req;
183
output wire     SRAM_UB_N;
184
output wire     SRAM_LB_N;
185
output wire     SRAM_CE_N;
186
output wire     SRAM_OE_N;
187
output wire     SRAM_WE_N;
188
output wire     arbiter_grant_0;
189
output wire     sprite_reader_mem_wren;
190
output wire     sprite_reader_mem_req;
191
output wire     sprite_reader_line_flag;
192
output wire     sprite_reader_cpu_sleep;
193
output wire     six_button_SELECT;
194
output wire     button_up;
195
output wire     button_down;
196
output wire     button_left;
197
output wire     button_right;
198
output wire     button_b;
199
output wire     button_c;
200
output wire     button_a;
201
output wire     button_start;
202
output wire     button_z;
203
output wire     button_y;
204
output wire     button_x;
205
output wire     VGA_SYNC;
206
output wire     [15:0] add_result;
207
output wire     [15:0] arbiter_addr;
208
output wire     [3:0] arbiter_current_state;
209
output wire     [15:0] arbiter_data;
210
output wire     [3:0] arbiter_next_state;
211
output wire     [5:0] cpu_current_state;
212
output wire     [15:0] cpu_imm;
213
output wire     [15:0] cpu_int_program_counter;
214
output wire     [7:0] cpu_int_rflags;
215
output wire     [5:0] cpu_next_state;
216
output wire     [5:0] cpu_opcode;
217
output wire     [127:0] cpu_pc_stack;
218
output wire     [15:0] cpu_pc_stack_val;
219
output wire     [15:0] cpu_program_counter;
220
output wire     [15:0] cpu_ram_addr;
221
output wire     [15:0] cpu_ram_data;
222
output wire     [4:0] cpu_reg_a_num;
223
output wire     [15:0] cpu_reg_a_val;
224
output wire     [4:0] cpu_reg_b_num;
225
output wire     [15:0] cpu_reg_b_val;
226
output wire     [4:0] cpu_reg_c_num;
227
output wire     [15:0] cpu_reg_c_val;
228
output wire     [511:0] cpu_registers;
229
output wire     [7:0] cpu_rflags;
230
output wire     [2:0] cpu_rflags_index;
231
output wire     [15:0] cpu_rom_addr;
232
output wire     [1023:0] cpu_sprite_color;
233
output wire     [383:0] cpu_sprite_id;
234
output wire     [5:0] cpu_sprite_level;
235
output wire     [639:0] cpu_sprite_x;
236
output wire     [639:0] cpu_sprite_y;
237
output wire     [2:0] cpu_stack_pointer;
238
output wire     [15:0] divide_quotient;
239
output wire     [15:0] divide_remain;
240
output wire     [31:0] mult_result;
241
output wire     [3:0] pic_current_state;
242
output wire     [15:0] pic_int_mask;
243
output wire     [15:0] pic_isr_addr;
244
output wire     [15:0] pic_mem_addr;
245
output wire     [3:0] pic_next_state;
246
output wire     [15:0] ram_q;
247
output wire     [31:0] rom_q;
248
output wire     [15:0] six_button_buttons;
249
output wire     [9:0] six_button_counter;
250
output wire     [3:0] six_button_current_state;
251
output wire     [15:0] six_button_mem_addr;
252
output wire     [15:0] six_button_mem_data;
253
output wire     [3:0] six_button_next_state;
254
output wire     [4:0] sprite_reader_EstadoAtual;
255
output wire     [4:0] sprite_reader_EstadoFuturo;
256
output wire     [6:0] sprite_reader_level_counter;
257
output wire     [5:0] sprite_reader_level_sprite_id;
258
output wire     [9:0] sprite_reader_level_sprite_y;
259
output wire     [15:0] sprite_reader_mem_addr;
260
output wire     [19:0] SRAM_ADDR;
261
output wire     [15:0] sub_result;
262
output wire     [7:0] VGA_B;
263
output wire     [7:0] VGA_G;
264
output wire     [9:0] VGA_h_pos;
265
output wire     [19:0] VGA_oAddress;
266
output wire     [7:0] VGA_R;
267
output wire     [9:0] VGA_v_pos;
268
 
269
wire    [15:0] buttons_bus;
270
wire    [15:0] SYNTHESIZED_WIRE_0;
271
wire    SYNTHESIZED_WIRE_80;
272
wire    [7:0] SYNTHESIZED_WIRE_2;
273
wire    [7:0] SYNTHESIZED_WIRE_3;
274
wire    [9:0] SYNTHESIZED_WIRE_81;
275
wire    [7:0] SYNTHESIZED_WIRE_5;
276
wire    [1023:0] SYNTHESIZED_WIRE_6;
277
wire    [383:0] SYNTHESIZED_WIRE_82;
278
wire    [1023:0] SYNTHESIZED_WIRE_8;
279
wire    [639:0] SYNTHESIZED_WIRE_9;
280
wire    [639:0] SYNTHESIZED_WIRE_83;
281
wire    [9:0] SYNTHESIZED_WIRE_84;
282
wire    SYNTHESIZED_WIRE_13;
283
wire    SYNTHESIZED_WIRE_14;
284
wire    SYNTHESIZED_WIRE_15;
285
wire    SYNTHESIZED_WIRE_16;
286
wire    SYNTHESIZED_WIRE_17;
287
wire    SYNTHESIZED_WIRE_18;
288
wire    SYNTHESIZED_WIRE_19;
289
wire    SYNTHESIZED_WIRE_20;
290
wire    [15:0] SYNTHESIZED_WIRE_21;
291
wire    [15:0] SYNTHESIZED_WIRE_22;
292
wire    [15:0] SYNTHESIZED_WIRE_23;
293
wire    [15:0] SYNTHESIZED_WIRE_24;
294
wire    [15:0] SYNTHESIZED_WIRE_25;
295
wire    [15:0] SYNTHESIZED_WIRE_26;
296
wire    [19:0] SYNTHESIZED_WIRE_27;
297
wire    SYNTHESIZED_WIRE_28;
298
wire    SYNTHESIZED_WIRE_29;
299
wire    SYNTHESIZED_WIRE_31;
300
wire    [15:0] SYNTHESIZED_WIRE_85;
301
wire    [15:0] SYNTHESIZED_WIRE_86;
302
wire    [15:0] SYNTHESIZED_WIRE_87;
303
wire    SYNTHESIZED_WIRE_35;
304
wire    SYNTHESIZED_WIRE_37;
305
wire    SYNTHESIZED_WIRE_88;
306
wire    SYNTHESIZED_WIRE_39;
307
wire    SYNTHESIZED_WIRE_40;
308
wire    SYNTHESIZED_WIRE_41;
309
wire    SYNTHESIZED_WIRE_42;
310
wire    SYNTHESIZED_WIRE_43;
311
wire    SYNTHESIZED_WIRE_44;
312
wire    [15:0] SYNTHESIZED_WIRE_45;
313
wire    [15:0] SYNTHESIZED_WIRE_46;
314
wire    [15:0] SYNTHESIZED_WIRE_47;
315
wire    [31:0] SYNTHESIZED_WIRE_48;
316
wire    [15:0] SYNTHESIZED_WIRE_49;
317
wire    [31:0] SYNTHESIZED_WIRE_50;
318
wire    [15:0] SYNTHESIZED_WIRE_52;
319
wire    SYNTHESIZED_WIRE_54;
320
wire    SYNTHESIZED_WIRE_60;
321
wire    [15:0] SYNTHESIZED_WIRE_61;
322
wire    [15:0] SYNTHESIZED_WIRE_62;
323
wire    SYNTHESIZED_WIRE_64;
324
wire    SYNTHESIZED_WIRE_66;
325
//wire  SYNTHESIZED_WIRE_73;
326
wire    [7:0] SYNTHESIZED_WIRE_75;
327
wire    [7:0] SYNTHESIZED_WIRE_76;
328
wire    [7:0] SYNTHESIZED_WIRE_77;
329
 
330
assign  add_overflow = SYNTHESIZED_WIRE_40;
331
assign  sub_overflow = SYNTHESIZED_WIRE_41;
332
assign  compare_aeb = SYNTHESIZED_WIRE_42;
333
assign  compare_agb = SYNTHESIZED_WIRE_43;
334
assign  compare_alb = SYNTHESIZED_WIRE_44;
335
assign  arbiter_grant_1 = SYNTHESIZED_WIRE_35;
336
assign  arbiter_grant_2 = SYNTHESIZED_WIRE_29;
337
assign  arbiter_grant_3 = SYNTHESIZED_WIRE_64;
338
assign  arbiter_wren = SYNTHESIZED_WIRE_60;
339
assign  cpu_ram_wren = SYNTHESIZED_WIRE_17;
340
assign  cpu_ram_req = SYNTHESIZED_WIRE_18;
341
assign  pic_mem_wren = SYNTHESIZED_WIRE_15;
342
assign  pic_mem_req = SYNTHESIZED_WIRE_16;
343
assign  pic_cpu_req = SYNTHESIZED_WIRE_37;
344
assign  cpu_int_ack = SYNTHESIZED_WIRE_28;
345
assign  pic_int_ack_0 = SYNTHESIZED_WIRE_66;
346
assign  VGA_VS = SYNTHESIZED_WIRE_88;
347
assign  six_button_mem_wren = SYNTHESIZED_WIRE_13;
348
assign  six_button_mem_req = SYNTHESIZED_WIRE_14;
349
assign  six_button_int_req = SYNTHESIZED_WIRE_31;
350
assign  arbiter_grant_0 = SYNTHESIZED_WIRE_54;
351
assign  sprite_reader_mem_wren = SYNTHESIZED_WIRE_19;
352
assign  sprite_reader_mem_req = SYNTHESIZED_WIRE_20;
353
assign  sprite_reader_cpu_sleep = SYNTHESIZED_WIRE_39;
354
assign  add_result = SYNTHESIZED_WIRE_45;
355
assign  arbiter_addr = SYNTHESIZED_WIRE_61;
356
assign  arbiter_data = SYNTHESIZED_WIRE_62;
357
assign  cpu_ram_addr = SYNTHESIZED_WIRE_22;
358
assign  cpu_ram_data = SYNTHESIZED_WIRE_25;
359
assign  cpu_reg_a_val = SYNTHESIZED_WIRE_86;
360
assign  cpu_reg_b_val = SYNTHESIZED_WIRE_87;
361
assign  cpu_rom_addr = SYNTHESIZED_WIRE_0;
362
assign  cpu_sprite_color = SYNTHESIZED_WIRE_6;
363
assign  cpu_sprite_id = SYNTHESIZED_WIRE_82;
364
assign  cpu_sprite_x = SYNTHESIZED_WIRE_9;
365
assign  cpu_sprite_y = SYNTHESIZED_WIRE_83;
366
assign  divide_quotient = SYNTHESIZED_WIRE_46;
367
assign  divide_remain = SYNTHESIZED_WIRE_47;
368
assign  mult_result = SYNTHESIZED_WIRE_50;
369
assign  pic_isr_addr = SYNTHESIZED_WIRE_49;
370
assign  pic_mem_addr = SYNTHESIZED_WIRE_23;
371
assign  ram_q = SYNTHESIZED_WIRE_85;
372
assign  rom_q = SYNTHESIZED_WIRE_48;
373
assign  six_button_mem_addr = SYNTHESIZED_WIRE_24;
374
assign  six_button_mem_data = SYNTHESIZED_WIRE_26;
375
assign  sprite_reader_mem_addr = SYNTHESIZED_WIRE_21;
376
assign  sub_result = SYNTHESIZED_WIRE_52;
377
assign  VGA_h_pos = SYNTHESIZED_WIRE_81;
378
assign  VGA_oAddress = SYNTHESIZED_WIRE_27;
379
assign  VGA_v_pos = SYNTHESIZED_WIRE_84;
380
 
381
 
382
 
383
 
384
IP_ROM_Program  b2v_inst(
385
        .clock(clock),
386
        .address(SYNTHESIZED_WIRE_0),
387
        .q(SYNTHESIZED_WIRE_48));
388
 
389
 
390
Sprite_Processor        b2v_inst1(
391
        .clk(clock),
392
        .rst(SYNTHESIZED_WIRE_80),
393
        .B_in(SYNTHESIZED_WIRE_2),
394
        .G_in(SYNTHESIZED_WIRE_3),
395
        .H_pos_in(SYNTHESIZED_WIRE_81),
396
        .R_in(SYNTHESIZED_WIRE_5),
397
        .sprite_color(SYNTHESIZED_WIRE_6),
398
        .sprite_id(SYNTHESIZED_WIRE_82),
399
        .sprite_shape(SYNTHESIZED_WIRE_8),
400
        .sprite_x(SYNTHESIZED_WIRE_9),
401
        .sprite_y(SYNTHESIZED_WIRE_83),
402
        .V_pos_in(SYNTHESIZED_WIRE_84),
403
        .B_out(SYNTHESIZED_WIRE_75),
404
        .G_out(SYNTHESIZED_WIRE_76),
405
        .R_out(SYNTHESIZED_WIRE_77));
406
 
407
 
408
Memory_Arbiter  b2v_inst10(
409
        .clock(clock),
410
        .reset(SYNTHESIZED_WIRE_80),
411
 
412
 
413
 
414
 
415
 
416
 
417
 
418
 
419
        .wren_3(SYNTHESIZED_WIRE_13),
420
        .req_3(SYNTHESIZED_WIRE_14),
421
        .wren_2(SYNTHESIZED_WIRE_15),
422
        .req_2(SYNTHESIZED_WIRE_16),
423
        .wren_1(SYNTHESIZED_WIRE_17),
424
        .req_1(SYNTHESIZED_WIRE_18),
425
        .wren_0(SYNTHESIZED_WIRE_19),
426
        .req_0(SYNTHESIZED_WIRE_20),
427
        .addr_0(SYNTHESIZED_WIRE_21),
428
        .addr_1(SYNTHESIZED_WIRE_22),
429
        .addr_2(SYNTHESIZED_WIRE_23),
430
        .addr_3(SYNTHESIZED_WIRE_24),
431
 
432
 
433
 
434
 
435
 
436
        .data_1(SYNTHESIZED_WIRE_25),
437
 
438
        .data_3(SYNTHESIZED_WIRE_26),
439
 
440
 
441
 
442
 
443
 
444
 
445
 
446
 
447
        .grant_3(SYNTHESIZED_WIRE_64),
448
        .grant_2(SYNTHESIZED_WIRE_29),
449
        .grant_1(SYNTHESIZED_WIRE_35),
450
        .grant_0(SYNTHESIZED_WIRE_54),
451
        .wren(SYNTHESIZED_WIRE_60),
452
        .addr(SYNTHESIZED_WIRE_61),
453
        .current_state(arbiter_current_state),
454
        .data(SYNTHESIZED_WIRE_62),
455
        .next_state(arbiter_next_state));
456
        defparam        b2v_inst10.Grant_0 = 4'b0001;
457
        defparam        b2v_inst10.Grant_1 = 4'b0010;
458
        defparam        b2v_inst10.Grant_2 = 4'b0011;
459
        defparam        b2v_inst10.Grant_3 = 4'b0100;
460
        defparam        b2v_inst10.Grant_4 = 4'b0101;
461
        defparam        b2v_inst10.Grant_5 = 4'b0110;
462
        defparam        b2v_inst10.Grant_6 = 4'b0111;
463
        defparam        b2v_inst10.Grant_7 = 4'b1000;
464
        defparam        b2v_inst10.Idle = 4'b0000;
465
 
466
 
467
SRAM_Interface  b2v_inst11(
468
        .iADDR(SYNTHESIZED_WIRE_27),
469
        .iDATA(SRAM_DQ),
470
        .oWE_N(SRAM_WE_N),
471
        .oOE_N(SRAM_OE_N),
472
        .oCE_N(SRAM_CE_N),
473
        .oLB_N(SRAM_LB_N),
474
        .oUB_N(SRAM_UB_N),
475
        .oADDR(SRAM_ADDR),
476
        .oBLUE(SYNTHESIZED_WIRE_2),
477
        .oGREEN(SYNTHESIZED_WIRE_3),
478
        .oRED(SYNTHESIZED_WIRE_5));
479
 
480
 
481
Interrupt_Controller    b2v_inst12(
482
        .cpu_ack(SYNTHESIZED_WIRE_28),
483
        .mem_grant(SYNTHESIZED_WIRE_29),
484
        .clock(clock),
485
        .reset(SYNTHESIZED_WIRE_80),
486
        .int_req_0(SYNTHESIZED_WIRE_31),
487
 
488
 
489
 
490
        .mem_q(SYNTHESIZED_WIRE_85),
491
        .mem_wren(SYNTHESIZED_WIRE_15),
492
        .mem_req(SYNTHESIZED_WIRE_16),
493
        .cpu_req(SYNTHESIZED_WIRE_37),
494
        .int_ack_0(SYNTHESIZED_WIRE_66),
495
 
496
 
497
 
498
        .current_state(pic_current_state),
499
        .int_mask(pic_int_mask),
500
        .isr_addr(SYNTHESIZED_WIRE_49),
501
        .mem_addr(SYNTHESIZED_WIRE_23),
502
        .next_state(pic_next_state));
503
        defparam        b2v_inst12.Get_Mask = 4'b0100;
504
        defparam        b2v_inst12.Idle = 4'b0000;
505
        defparam        b2v_inst12.Int_Req_0 = 4'b0101;
506
        defparam        b2v_inst12.Int_Req_1 = 4'b0110;
507
        defparam        b2v_inst12.Int_Req_2 = 4'b0111;
508
        defparam        b2v_inst12.Int_Req_3 = 4'b1000;
509
        defparam        b2v_inst12.Read_Mask = 4'b0001;
510
        defparam        b2v_inst12.Wait_Mem_1 = 4'b0010;
511
        defparam        b2v_inst12.Wait_Mem_2 = 4'b0011;
512
        defparam        b2v_inst12.Wait_Req_0 = 4'b1001;
513
        defparam        b2v_inst12.Wait_Req_1 = 4'b1010;
514
        defparam        b2v_inst12.Wait_Req_2 = 4'b1011;
515
        defparam        b2v_inst12.Wait_Req_3 = 4'b1100;
516
 
517
 
518
IP_PLL  b2v_inst17(
519
        .inclk0(clock);
520
        //.c0(SYNTHESIZED_WIRE_73));
521
 
522
 
523
IP_MULT b2v_inst2(
524
        .clock(clock),
525
        .dataa(SYNTHESIZED_WIRE_86),
526
        .datab(SYNTHESIZED_WIRE_87),
527
        .result(SYNTHESIZED_WIRE_50));
528
 
529
 
530
Processor_Controller    b2v_inst20(
531
        .ram_grant(SYNTHESIZED_WIRE_35),
532
        .clock(clock),
533
        .reset(SYNTHESIZED_WIRE_80),
534
        .int_req(SYNTHESIZED_WIRE_37),
535
        .v_sync(SYNTHESIZED_WIRE_88),
536
        .sleep(SYNTHESIZED_WIRE_39),
537
        .add_overflow(SYNTHESIZED_WIRE_40),
538
        .sub_overflow(SYNTHESIZED_WIRE_41),
539
        .compare_aeb(SYNTHESIZED_WIRE_42),
540
        .compare_agb(SYNTHESIZED_WIRE_43),
541
        .compare_alb(SYNTHESIZED_WIRE_44),
542
        .add_result(SYNTHESIZED_WIRE_45),
543
        .divide_quotient(SYNTHESIZED_WIRE_46),
544
        .divide_remain(SYNTHESIZED_WIRE_47),
545
        .instruction(SYNTHESIZED_WIRE_48),
546
        .isr_addr(SYNTHESIZED_WIRE_49),
547
        .mult_result(SYNTHESIZED_WIRE_50),
548
        .ram_q(SYNTHESIZED_WIRE_85),
549
        .sub_result(SYNTHESIZED_WIRE_52),
550
        .int_ack(SYNTHESIZED_WIRE_28),
551
        .const_bool(cpu_const_bool),
552
        .ram_wren(SYNTHESIZED_WIRE_17),
553
        .ram_req(SYNTHESIZED_WIRE_18),
554
        .v_sync_flag(cpu_v_sync_flag),
555
        .current_state(cpu_current_state),
556
        .imm(cpu_imm),
557
        .int_program_counter(cpu_int_program_counter),
558
        .int_rflags(cpu_int_rflags),
559
        .next_state(cpu_next_state),
560
        .opcode(cpu_opcode),
561
        .pc_stack(cpu_pc_stack),
562
        .pc_stack_val(cpu_pc_stack_val),
563
        .program_counter(cpu_program_counter),
564
        .ram_addr(SYNTHESIZED_WIRE_22),
565
        .ram_data(SYNTHESIZED_WIRE_25),
566
        .reg_a_num(cpu_reg_a_num),
567
        .reg_a_val(SYNTHESIZED_WIRE_86),
568
        .reg_b_num(cpu_reg_b_num),
569
        .reg_b_val(SYNTHESIZED_WIRE_87),
570
        .reg_c_num(cpu_reg_c_num),
571
        .reg_c_val(cpu_reg_c_val),
572
        .registers(cpu_registers),
573
        .rflags(cpu_rflags),
574
        .rflags_index(cpu_rflags_index),
575
        .rom_addr(SYNTHESIZED_WIRE_0),
576
        .sprite_color(SYNTHESIZED_WIRE_6),
577
        .sprite_id(SYNTHESIZED_WIRE_82),
578
        .sprite_level(cpu_sprite_level),
579
        .sprite_x(SYNTHESIZED_WIRE_9),
580
        .sprite_y(SYNTHESIZED_WIRE_83),
581
        .stack_pointer(cpu_stack_pointer));
582
        defparam        b2v_inst20.ADD = 6'b001000;
583
        defparam        b2v_inst20.AND = 6'b001100;
584
        defparam        b2v_inst20.BRFL = 6'b011100;
585
        defparam        b2v_inst20.BRFLR = 6'b011101;
586
        defparam        b2v_inst20.CALL = 6'b011111;
587
        defparam        b2v_inst20.CALLR = 6'b100000;
588
        defparam        b2v_inst20.CMP = 6'b001110;
589
        defparam        b2v_inst20.code_start_addr = 16'b0000000000000100;
590
        defparam        b2v_inst20.Decode_Instruction = 6'b000010;
591
        defparam        b2v_inst20.DIV = 6'b001011;
592
        defparam        b2v_inst20.Inc_Program_Counter = 6'b100011;
593
        defparam        b2v_inst20.Int_Req_Wait = 6'b100100;
594
        defparam        b2v_inst20.Interrupt = 6'b100101;
595
        defparam        b2v_inst20.IRET = 6'b100110;
596
        defparam        b2v_inst20.JMP = 6'b011010;
597
        defparam        b2v_inst20.JR = 6'b011011;
598
        defparam        b2v_inst20.LIMM = 6'b010011;
599
        defparam        b2v_inst20.LW_Begin = 6'b010100;
600
        defparam        b2v_inst20.LW_End = 6'b010111;
601
        defparam        b2v_inst20.LW_Wait_1 = 6'b010101;
602
        defparam        b2v_inst20.LW_Wait_2 = 6'b010110;
603
        defparam        b2v_inst20.MUL = 6'b001010;
604
        defparam        b2v_inst20.NOP = 6'b011110;
605
        defparam        b2v_inst20.NOT = 6'b001111;
606
        defparam        b2v_inst20.opcode_add = 6'b010001;
607
        defparam        b2v_inst20.opcode_and = 6'b100001;
608
        defparam        b2v_inst20.opcode_brfl = 6'b101010;
609
        defparam        b2v_inst20.opcode_brflr = 6'b011010;
610
        defparam        b2v_inst20.opcode_call = 6'b101011;
611
        defparam        b2v_inst20.opcode_callr = 6'b011011;
612
        defparam        b2v_inst20.opcode_cmp = 6'b100100;
613
        defparam        b2v_inst20.opcode_div = 6'b010101;
614
        defparam        b2v_inst20.opcode_iret = 6'b101101;
615
        defparam        b2v_inst20.opcode_jmp = 6'b101001;
616
        defparam        b2v_inst20.opcode_jr = 6'b011001;
617
        defparam        b2v_inst20.opcode_limm = 6'b001100;
618
        defparam        b2v_inst20.opcode_lw = 6'b001001;
619
        defparam        b2v_inst20.opcode_mul = 6'b010100;
620
        defparam        b2v_inst20.opcode_nop = 6'b101110;
621
        defparam        b2v_inst20.opcode_not = 6'b100101;
622
        defparam        b2v_inst20.opcode_or = 6'b100010;
623
        defparam        b2v_inst20.opcode_ret = 6'b101100;
624
        defparam        b2v_inst20.opcode_sprite_color = 6'b110010;
625
        defparam        b2v_inst20.opcode_sprite_id = 6'b110001;
626
        defparam        b2v_inst20.opcode_sprite_pos = 6'b110100;
627
        defparam        b2v_inst20.opcode_sub = 6'b010010;
628
        defparam        b2v_inst20.opcode_sw = 6'b001010;
629
        defparam        b2v_inst20.opcode_wait_vsync = 6'b110111;
630
        defparam        b2v_inst20.OR = 6'b001101;
631
        defparam        b2v_inst20.Reset = 6'b000000;
632
        defparam        b2v_inst20.RET = 6'b100001;
633
        defparam        b2v_inst20.SPRITE_COLOR = 6'b010001;
634
        defparam        b2v_inst20.SPRITE_ID = 6'b010000;
635
        defparam        b2v_inst20.SPRITE_POS = 6'b010010;
636
        defparam        b2v_inst20.SUB = 6'b001001;
637
        defparam        b2v_inst20.SW_Begin = 6'b011000;
638
        defparam        b2v_inst20.SW_End = 6'b011001;
639
        defparam        b2v_inst20.Wait_DIV_1 = 6'b000100;
640
        defparam        b2v_inst20.Wait_DIV_2 = 6'b000101;
641
        defparam        b2v_inst20.Wait_DIV_3 = 6'b000110;
642
        defparam        b2v_inst20.Wait_DIV_4 = 6'b000111;
643
        defparam        b2v_inst20.Wait_Operation = 6'b000011;
644
        defparam        b2v_inst20.Wait_Program_Mem_1 = 6'b000001;
645
        defparam        b2v_inst20.WAIT_VSYNC = 6'b100010;
646
 
647
 
648
Sprite_Shape_Reader     b2v_inst21(
649
        .clock(clock),
650
        .reset(SYNTHESIZED_WIRE_80),
651
        .mem_grant(SYNTHESIZED_WIRE_54),
652
        .H_pos(SYNTHESIZED_WIRE_81),
653
        .mem_q(SYNTHESIZED_WIRE_85),
654
        .sprite_id(SYNTHESIZED_WIRE_82),
655
        .sprite_y(SYNTHESIZED_WIRE_83),
656
        .V_pos(SYNTHESIZED_WIRE_84),
657
        .mem_wren(SYNTHESIZED_WIRE_19),
658
        .mem_req(SYNTHESIZED_WIRE_20),
659
        .line_flag(sprite_reader_line_flag),
660
        .cpu_sleep(SYNTHESIZED_WIRE_39),
661
        .EstadoAtual(sprite_reader_EstadoAtual),
662
        .EstadoFuturo(sprite_reader_EstadoFuturo),
663
        .level_counter(sprite_reader_level_counter),
664
        .level_sprite_id(sprite_reader_level_sprite_id),
665
        .level_sprite_y(sprite_reader_level_sprite_y),
666
 
667
 
668
        .mem_addr(SYNTHESIZED_WIRE_21),
669
        .sprite_shape(SYNTHESIZED_WIRE_8));
670
        defparam        b2v_inst21.Change_Level = 5'b01000;
671
        defparam        b2v_inst21.Change_Line = 5'b00010;
672
        defparam        b2v_inst21.Get_Level_Info = 5'b00011;
673
        defparam        b2v_inst21.line_A = 1'b0;
674
        defparam        b2v_inst21.line_B = 1'b1;
675
        defparam        b2v_inst21.Read_Shape = 5'b00111;
676
        defparam        b2v_inst21.Reset = 5'b00000;
677
        defparam        b2v_inst21.Set_Shape_Address = 5'b00100;
678
        defparam        b2v_inst21.Wait_Line = 5'b00001;
679
        defparam        b2v_inst21.Wait_Mem_1 = 5'b00101;
680
        defparam        b2v_inst21.Wait_Mem_2 = 5'b00110;
681
 
682
 
683
IP_RAM_Data     b2v_inst22(
684
        .clock(clock),
685
        .wren(SYNTHESIZED_WIRE_60),
686
        .address(SYNTHESIZED_WIRE_61),
687
        .data(SYNTHESIZED_WIRE_62),
688
        .q(SYNTHESIZED_WIRE_85));
689
 
690
 
691
Genesis_6button_Interface       b2v_inst3(
692
        .clock(clock),
693
        .reset(SYNTHESIZED_WIRE_80),
694
        .mem_grant(SYNTHESIZED_WIRE_64),
695
        .up_z(six_button_UP_Z),
696
        .down_y(six_button_DOWN_Y),
697
        .left_x(six_button_LEFT_X),
698
        .right_mode(six_button_RIGHT_MODE),
699
        .b_a(six_button_B_A),
700
        .c_start(six_button_C_START),
701
        .v_sync(SYNTHESIZED_WIRE_88),
702
        .int_ack(SYNTHESIZED_WIRE_66),
703
        .mem_wren(SYNTHESIZED_WIRE_13),
704
        .mem_req(SYNTHESIZED_WIRE_14),
705
        .select(six_button_SELECT),
706
        .v_sync_flag(six_button_v_sync_flag),
707
        .int_req(SYNTHESIZED_WIRE_31),
708
        .buttons(buttons_bus),
709
        .counter(six_button_counter),
710
        .current_state(six_button_current_state),
711
        .mem_addr(SYNTHESIZED_WIRE_24),
712
        .mem_data(SYNTHESIZED_WIRE_26),
713
        .next_state(six_button_next_state));
714
        defparam        b2v_inst3.Int_Req = 4'b1100;
715
        defparam        b2v_inst3.Reset = 4'b0000;
716
        defparam        b2v_inst3.Step_0 = 4'b0010;
717
        defparam        b2v_inst3.Step_1 = 4'b0011;
718
        defparam        b2v_inst3.Step_2 = 4'b0100;
719
        defparam        b2v_inst3.Step_3 = 4'b0101;
720
        defparam        b2v_inst3.Step_4 = 4'b0110;
721
        defparam        b2v_inst3.Step_5 = 4'b0111;
722
        defparam        b2v_inst3.Step_6 = 4'b1000;
723
        defparam        b2v_inst3.Step_7 = 4'b1001;
724
        defparam        b2v_inst3.Wait_Frame = 4'b0001;
725
        defparam        b2v_inst3.Wait_Mem = 4'b1011;
726
        defparam        b2v_inst3.Write_Data = 4'b1010;
727
 
728
 
729
Reset_Synchronizer      b2v_inst4(
730
        .clock(clock),
731
        .reset_in(reset),
732
        .reset_out(SYNTHESIZED_WIRE_80));
733
 
734
 
735
IP_ADD  b2v_inst5(
736
        .clock(clock),
737
        .dataa(SYNTHESIZED_WIRE_86),
738
        .datab(SYNTHESIZED_WIRE_87),
739
        .overflow(SYNTHESIZED_WIRE_40),
740
        .result(SYNTHESIZED_WIRE_45));
741
 
742
 
743
IP_SUB  b2v_inst6(
744
        .clock(clock),
745
        .dataa(SYNTHESIZED_WIRE_86),
746
        .datab(SYNTHESIZED_WIRE_87),
747
        .overflow(SYNTHESIZED_WIRE_41),
748
        .result(SYNTHESIZED_WIRE_52));
749
 
750
 
751
IP_DIVIDE       b2v_inst7(
752
        .clock(clock),
753
        .denom(SYNTHESIZED_WIRE_87),
754
        .numer(SYNTHESIZED_WIRE_86),
755
        .quotient(SYNTHESIZED_WIRE_46),
756
        .remain(SYNTHESIZED_WIRE_47));
757
 
758
 
759
VGA_Interface   b2v_inst8(
760
        .clk(testbench_PLL_clock),
761
        .rst(SYNTHESIZED_WIRE_80),
762
        .B_in(SYNTHESIZED_WIRE_75),
763
        .G_in(SYNTHESIZED_WIRE_76),
764
        .R_in(SYNTHESIZED_WIRE_77),
765
        .BLANK(VGA_BLANK),
766
        .VGA_SYNC(VGA_SYNC),
767
        .VGA_CLK(VGA_CLK),
768
        .HS(VGA_HS),
769
        .VS(SYNTHESIZED_WIRE_88),
770
        .B(VGA_B),
771
        .G(VGA_G),
772
        .h_pos(SYNTHESIZED_WIRE_81),
773
        .oAddress(SYNTHESIZED_WIRE_27),
774
        .R(VGA_R),
775
        .v_pos(SYNTHESIZED_WIRE_84));
776
        defparam        b2v_inst8.H_BACK = 48;
777
        defparam        b2v_inst8.H_DISPLAY = 640;
778
        defparam        b2v_inst8.H_FRONT = 16;
779
        defparam        b2v_inst8.H_SYNC = 96;
780
        defparam        b2v_inst8.V_BACK = 33;
781
        defparam        b2v_inst8.V_DISPLAY = 480;
782
        defparam        b2v_inst8.V_FRONT = 10;
783
        defparam        b2v_inst8.V_SYNC = 2;
784
 
785
 
786
IP_COMPARE      b2v_inst9(
787
        .clock(clock),
788
        .dataa(SYNTHESIZED_WIRE_86),
789
        .datab(SYNTHESIZED_WIRE_87),
790
        .aeb(SYNTHESIZED_WIRE_42),
791
        .agb(SYNTHESIZED_WIRE_43),
792
        .alb(SYNTHESIZED_WIRE_44));
793
 
794
assign  button_up = buttons_bus[0];
795
assign  button_down = buttons_bus[1];
796
assign  button_left = buttons_bus[2];
797
assign  button_right = buttons_bus[3];
798
assign  button_b = buttons_bus[4];
799
assign  button_c = buttons_bus[5];
800
assign  button_a = buttons_bus[6];
801
assign  button_start = buttons_bus[7];
802
assign  button_z = buttons_bus[8];
803
assign  button_y = buttons_bus[9];
804
assign  button_x = buttons_bus[10];
805
assign  six_button_buttons = buttons_bus;
806
 
807
endmodule

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