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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [Processor_Controller.v] - Blame information for rev 2

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1 2 lucas.vbal
module Processor_Controller(
2
 
3
ram_grant,
4
instruction,
5
clock,
6
reset,
7
 
8
isr_addr,
9
int_req,
10
 
11
v_sync,
12
sleep,
13
 
14
ram_q,
15
 
16
add_overflow,
17
add_result,
18
sub_overflow,
19
sub_result,
20
mult_result,
21
divide_quotient,
22
divide_remain,
23
compare_aeb,
24
compare_agb,
25
compare_alb,
26
 
27
int_ack,
28
rom_addr,
29
opcode,
30
reg_a_num,
31
reg_b_num,
32
reg_c_num,
33
imm,
34
rflags_index,
35
const_bool,
36
 
37
sprite_level,
38
sprite_id,
39
sprite_x,
40
sprite_y,
41
sprite_color,
42
 
43
ram_addr,
44
ram_data,
45
ram_wren,
46
ram_req,
47
 
48
reg_c_val,
49
reg_b_val,
50
reg_a_val,
51
 
52
current_state,
53
next_state,
54
program_counter,
55
registers,
56
rflags,
57
v_sync_flag,
58
stack_pointer,
59
pc_stack,
60
pc_stack_val,
61
int_program_counter,
62
int_rflags
63
 
64
);
65
 
66
 
67
input   [15:0]   ram_q;
68
input   [15:0]   isr_addr;
69
input [31:0]     instruction;
70
 
71
input wire signed       [15:0]   add_result;
72
input wire signed       [15:0]   sub_result;
73
input wire signed       [31:0]   mult_result;
74
input wire signed       [15:0]   divide_quotient;
75
input   wire signed [15:0]       divide_remain;
76
 
77
input           ram_grant;
78
input           add_overflow;
79
input           sub_overflow;
80
input           compare_aeb;
81
input           compare_agb;
82
input           compare_alb;
83
input           int_req;
84
 
85
input           sleep;
86
input           v_sync;
87
 
88
input   clock;
89
input   reset;
90
 
91
output                          v_sync_flag;
92
output                          const_bool;
93
output  [2:0]            rflags_index;
94
output  [4:0]            reg_a_num;
95
output  [4:0]            reg_b_num;
96
output  [4:0]            reg_c_num;
97
output  [5:0]            opcode;
98
output  [15:0]   imm;
99
 
100
output reg      [15:0]   reg_a_val;
101
output reg      [15:0]   reg_b_val;
102
output reg      [15:0]   reg_c_val;
103
 
104
output reg      [15:0]   ram_addr;
105
output reg      [15:0]   ram_data;
106
output reg                              ram_wren;
107
output reg                              ram_req;
108
 
109
output reg                              int_ack;
110
output reg      [15:0]   int_program_counter;
111
output reg      [7:0]            int_rflags;
112
 
113
output reg      [15:0]   rom_addr;
114
output reg      [15:0]   program_counter;
115
output reg      [511:0]  registers;
116
output reg      [7:0]            rflags;
117
 
118
output reg      [2:0]            stack_pointer;
119
output reg      [127:0]  pc_stack;
120
output reg      [15:0]   pc_stack_val;
121
 
122
output reg      [5:0]            sprite_level;
123
output reg      [383:0]  sprite_id;
124
output reg      [639:0]  sprite_x;
125
output reg      [639:0]  sprite_y;
126
output reg      [1023:0] sprite_color;
127
 
128
assign  opcode                  =       instruction[31:26];
129
assign  reg_a_num               =       instruction[25:21];
130
assign  reg_b_num               =       instruction[20:16];
131
assign  reg_c_num               =       instruction[15:11];
132
assign  imm                             =       instruction[15:0];
133
assign  const_bool              =       instruction[17];
134
assign  rflags_index    =       instruction[20:18];
135
 
136
 
137
// Number of Interrupt Service Routines
138
parameter code_start_addr = 16'd4;
139
 
140
// INSTRUCTIONS OPERATION CODE
141
// Data Transfer Instructions
142
parameter opcode_lw                                             = 6'b001001;
143
parameter opcode_sw                                             = 6'b001010;
144
parameter opcode_limm                                   = 6'b001100;
145
// Arithmetic Instructions
146
parameter opcode_add                                            = 6'b010001;
147
parameter opcode_sub                                            = 6'b010010;
148
parameter opcode_mul                                            = 6'b010100;
149
parameter opcode_div                                            = 6'b010101;
150
// Logical Instructions
151
parameter opcode_and                                            = 6'b100001;
152
parameter opcode_or                                             = 6'b100010;
153
parameter opcode_cmp                                            = 6'b100100;
154
parameter opcode_not                                            = 6'b100101;
155
// Control Transfer Instructions (Immediate)
156
parameter opcode_jmp                                            = 6'b101001;
157
parameter opcode_brfl                                   = 6'b101010;
158
parameter opcode_call                                   = 6'b101011;
159
parameter opcode_ret                                            = 6'b101100;
160
parameter opcode_iret                                   = 6'b101101;
161
parameter opcode_nop                                            = 6'b101110;
162
// Control Transfer Instructions (Register)
163
parameter opcode_jr                                             = 6'b011001;
164
parameter opcode_brflr                                  = 6'b011010;
165
parameter opcode_callr                                  = 6'b011011;
166
// Graphical instructions
167
parameter opcode_sprite_id                              = 6'b110001;
168
parameter opcode_sprite_color                   = 6'b110010;
169
parameter opcode_sprite_pos                     = 6'b110100;
170
parameter opcode_wait_vsync                     = 6'b110111;
171
 
172
 
173
/*########################################################################*/
174
/*#################  Video vertical sync edge-detection  #################*/
175
/*########################################################################*/
176
 
177
reg   v_sync_delay;
178
 
179
always @ (posedge clock)
180
begin
181
        v_sync_delay <= v_sync;
182
end
183
 
184
assign v_sync_flag = ~v_sync & v_sync_delay;
185
 
186
/*########################################################################*/
187
/*########################################################################*/
188
 
189
 
190
/*########################################################################*/
191
/*########################  FINITE STATE MACHINE  ########################*/
192
/*########################  PROCESSOR CONTROLLER  ########################*/
193
/*########################################################################*/
194
 
195
output reg      [5:0]            current_state;
196
output reg      [5:0]            next_state;
197
 
198
// States
199
parameter       Reset                                           = 6'b000000;    // Reset                                                = 0
200
parameter       Wait_Program_Mem_1      = 6'b000001;    // Wait_Program_Mem_1   = 1
201
parameter       Decode_Instruction      = 6'b000010;    // Decode_Instruction   = 2
202
parameter       Wait_Operation                  = 6'b000011;    // Wait_Operation                       = 3
203
parameter       Wait_DIV_1                              = 6'b000100;    // Wait_DIV_1                           = 4
204
parameter       Wait_DIV_2                              = 6'b000101;    // Wait_DIV_2                           = 5
205
parameter       Wait_DIV_3                              = 6'b000110;    // Wait_DIV_3                           = 6
206
parameter       Wait_DIV_4                              = 6'b000111;    // Wait_DIV_4                           = 7
207
parameter       ADD                                             = 6'b001000;    // ADD                                          = 8
208
parameter       SUB                                             = 6'b001001;    // SUB                                          = 9
209
parameter       MUL                                             = 6'b001010;    // MUL                                          = 10
210
parameter       DIV                                             = 6'b001011;    // DIV                                          = 11
211
parameter       AND                                             = 6'b001100;    // AND                                          = 12
212
parameter       OR                                                      = 6'b001101;    // OR                                                   = 13
213
parameter       CMP                                             = 6'b001110;    // CMP                                          = 14
214
parameter       NOT                                             = 6'b001111;    // NOT                                          = 15
215
parameter       SPRITE_ID                               = 6'b010000;    // SPRITE_ID                            = 16
216
parameter       SPRITE_COLOR                    = 6'b010001;    // SPRITE_COLOR                 = 17
217
parameter       SPRITE_POS                              = 6'b010010;    // SPRITE_POS                           = 18
218
parameter       LIMM                                            = 6'b010011;    // LIMM                                         = 19
219
parameter       LW_Begin                                        = 6'b010100;    // LW_Begin                                     = 20
220
parameter       LW_Wait_1                               = 6'b010101;    // LW_Wait_1                            = 21
221
parameter       LW_Wait_2                               = 6'b010110;    // LW_Wait_2                            = 22
222
parameter       LW_End                                  = 6'b010111;    // LW_End                                       = 23
223
parameter       SW_Begin                                        = 6'b011000;    // SW_Begin                                     = 24
224
parameter       SW_End                                  = 6'b011001;    // SW_End                                       = 25
225
parameter       JMP                                             = 6'b011010;    // JMP                                          = 26
226
 
227
parameter       JR                                                      = 6'b011011;    // JR                                                   = 27
228
parameter       BRFL                                            = 6'b011100;    // BRFL                                         = 28
229
parameter       BRFLR                                           = 6'b011101;    // BRFL                                         = 29
230
 
231
parameter       NOP                                             = 6'b011110;    // NOP                                          = 30
232
 
233
parameter       CALL                                            = 6'b011111;    // CALL                                         = 31
234
parameter       CALLR                                           = 6'b100000;    // CALLR                                                = 32
235
parameter       RET                                             = 6'b100001;    // RET                                          = 33
236
parameter       WAIT_VSYNC                              = 6'b100010;    // WAIT_VSYNC                           = 34
237
 
238
parameter       Inc_Program_Counter     = 6'b100011;    // Inc_Program_Counter  = 35
239
 
240
 
241
parameter       Int_Req_Wait                    = 6'b100100;    // Int_Req_Wait                 = 36
242
 
243
parameter       Interrupt                               = 6'b100101;    // Interrupt                            = 37
244
parameter       IRET                                            = 6'b100110;    // IRET                                         = 38
245
 
246
 
247
 
248
// Next State Decoder
249
always @ (*)
250
begin
251
        case (current_state)
252
 
253
                // State 0
254
                Reset:
255
                begin
256
                        next_state = Wait_Program_Mem_1;
257
                end
258
 
259
                // State 1
260
                Wait_Program_Mem_1:
261
                begin
262
                        if (sleep)
263
                                next_state = Wait_Program_Mem_1;
264
                        else if (int_req)
265
                                next_state = Int_Req_Wait;
266
                        else
267
                                next_state = Decode_Instruction;
268
                end
269
 
270
                // State 2
271
                Decode_Instruction:
272
                begin
273
                        next_state = Wait_Operation;
274
                end
275
 
276
                // State 3
277
                Wait_Operation:
278
                begin
279
 
280
                        case (opcode)
281
 
282
                                opcode_add:
283
                                begin
284
                                        next_state = ADD;
285
                                end
286
 
287
                                opcode_sub:
288
                                begin
289
                                        next_state = SUB;
290
                                end
291
 
292
                                opcode_mul:
293
                                begin
294
                                        next_state = MUL;
295
                                end
296
 
297
                                opcode_div:
298
                                begin
299
                                        next_state = Wait_DIV_1;
300
                                end
301
 
302
                                opcode_and:
303
                                begin
304
                                        next_state = AND;
305
                                end
306
 
307
                                opcode_or:
308
                                begin
309
                                        next_state = OR;
310
                                end
311
 
312
                                opcode_cmp:
313
                                begin
314
                                        next_state = CMP;
315
                                end
316
 
317
                                opcode_not:
318
                                begin
319
                                        next_state = NOT;
320
                                end
321
 
322
                                opcode_sprite_id:
323
                                begin
324
                                        next_state = SPRITE_ID;
325
                                end
326
 
327
                                opcode_sprite_color:
328
                                begin
329
                                        next_state = SPRITE_COLOR;
330
                                end
331
 
332
                                opcode_sprite_pos:
333
                                begin
334
                                        next_state = SPRITE_POS;
335
                                end
336
 
337
                                opcode_limm:
338
                                begin
339
                                        next_state = LIMM;
340
                                end
341
 
342
                                opcode_lw:
343
                                begin
344
                                        next_state = LW_Begin;
345
                                end
346
 
347
                                opcode_sw:
348
                                begin
349
                                        next_state = SW_Begin;
350
                                end
351
 
352
                                opcode_jmp:
353
                                begin
354
                                        next_state = JMP;
355
                                end
356
 
357
 
358
 
359
 
360
                                opcode_jr:
361
                                begin
362
                                        next_state = JR;
363
                                end
364
 
365
                                opcode_brfl:
366
                                begin
367
                                        if (rflags[rflags_index] == const_bool)
368
                                                next_state = BRFL;
369
                                        else
370
                                                next_state = Inc_Program_Counter;
371
                                end
372
 
373
                                opcode_brflr:
374
                                begin
375
                                        if (rflags[rflags_index] == const_bool)
376
                                                next_state = BRFLR;
377
                                        else
378
                                                next_state = Inc_Program_Counter;
379
                                end
380
 
381
                                opcode_nop:
382
                                begin
383
                                        next_state = NOP;
384
                                end
385
 
386
                                opcode_call:
387
                                begin
388
                                        next_state = CALL;
389
                                end
390
 
391
                                opcode_callr:
392
                                begin
393
                                        next_state = CALLR;
394
                                end
395
 
396
                                opcode_ret:
397
                                begin
398
                                        next_state = RET;
399
                                end
400
 
401
                                opcode_wait_vsync:
402
                                begin
403
                                        next_state = WAIT_VSYNC;
404
                                end
405
 
406
                                opcode_iret:
407
                                begin
408
                                        next_state = IRET;
409
                                end
410
 
411
 
412
 
413
 
414
                                default:
415
                                begin
416
                                        next_state = Reset;
417
                                end
418
 
419
                        endcase
420
 
421
 
422
                end
423
 
424
                // State 4
425
                Wait_DIV_1:
426
                begin
427
                        next_state = Wait_DIV_2;
428
                end
429
 
430
                // State 5
431
                Wait_DIV_2:
432
                begin
433
                        next_state = Wait_DIV_3;
434
                end
435
 
436
                // State 6
437
                Wait_DIV_3:
438
                begin
439
                        next_state = Wait_DIV_4;
440
                end
441
 
442
                // State 7
443
                Wait_DIV_4:
444
                begin
445
                        next_state = DIV;
446
                end
447
 
448
                // State 8
449
                ADD:
450
                begin
451
                        next_state = Inc_Program_Counter;
452
                end
453
 
454
                // State 9
455
                SUB:
456
                begin
457
                        next_state = Inc_Program_Counter;
458
                end
459
 
460
                // State 10
461
                MUL:
462
                begin
463
                        next_state = Inc_Program_Counter;
464
                end
465
 
466
                // State 11
467
                DIV:
468
                begin
469
                        next_state = Inc_Program_Counter;
470
                end
471
 
472
                // State 12
473
                AND:
474
                begin
475
                        next_state = Inc_Program_Counter;
476
                end
477
 
478
                // State 13
479
                OR:
480
                begin
481
                        next_state = Inc_Program_Counter;
482
                end
483
 
484
                // State 14
485
                CMP:
486
                begin
487
                        next_state = Inc_Program_Counter;
488
                end
489
 
490
                // State 15
491
                NOT:
492
                begin
493
                        next_state = Inc_Program_Counter;
494
                end
495
 
496
                // State 16
497
                SPRITE_ID:
498
                begin
499
                        next_state = Inc_Program_Counter;
500
                end
501
 
502
                // State 17
503
                SPRITE_COLOR:
504
                begin
505
                        next_state = Inc_Program_Counter;
506
                end
507
 
508
                // State 18
509
                SPRITE_POS:
510
                begin
511
                        next_state = Inc_Program_Counter;
512
                end
513
 
514
                // State 19
515
                LIMM:
516
                begin
517
                        next_state = Inc_Program_Counter;
518
                end
519
 
520
                // State 20
521
                LW_Begin:
522
                begin
523
                        if (ram_grant)
524
                                next_state = LW_Wait_1;
525
                        else
526
                                next_state = LW_Begin;
527
                end
528
 
529
                // State 21
530
                LW_Wait_1:
531
                begin
532
                        next_state = LW_Wait_2;
533
                end
534
 
535
                // State 22
536
                LW_Wait_2:
537
                begin
538
                        next_state = LW_End;
539
                end
540
 
541
                // State 23
542
                LW_End:
543
                begin
544
                        next_state = Inc_Program_Counter;
545
                end
546
 
547
                // State 24
548
                SW_Begin:
549
                begin
550
                        if (ram_grant)
551
                                next_state = SW_End;
552
                        else
553
                                next_state = SW_Begin;
554
                end
555
 
556
                // State 25
557
                SW_End:
558
                begin
559
                        next_state = Inc_Program_Counter;
560
                end
561
 
562
                // State 26
563
                JMP:
564
                begin
565
                        next_state = Wait_Program_Mem_1;
566
                end
567
 
568
 
569
 
570
 
571
 
572
                // State 27
573
                JR:
574
                begin
575
                        next_state = Wait_Program_Mem_1;
576
                end
577
 
578
                // State 28
579
                BRFL:
580
                begin
581
                        next_state = Wait_Program_Mem_1;
582
                end
583
 
584
                // State 29
585
                BRFLR:
586
                begin
587
                        next_state = Wait_Program_Mem_1;
588
                end
589
 
590
                // State 30
591
                NOP:
592
                begin
593
                        next_state = Inc_Program_Counter;
594
                end
595
 
596
                // State 31
597
                CALL:
598
                begin
599
                        next_state = Wait_Program_Mem_1;
600
                end
601
 
602
                // State 32
603
                CALLR:
604
                begin
605
                        next_state = Wait_Program_Mem_1;
606
                end
607
 
608
                // State 33
609
                RET:
610
                begin
611
                        next_state = Wait_Program_Mem_1;
612
                end
613
 
614
                // State 34
615
                WAIT_VSYNC:
616
                begin
617
                        if (v_sync_flag)
618
                                next_state = Inc_Program_Counter;
619
                        else
620
                                next_state = WAIT_VSYNC;
621
                end
622
 
623
 
624
 
625
                // State 35
626
                Inc_Program_Counter:
627
                begin
628
                        next_state = Wait_Program_Mem_1;
629
                end
630
 
631
 
632
                // State 36
633
                Int_Req_Wait:
634
                begin
635
                        if (!int_req)
636
                                next_state = Interrupt;
637
                        else
638
                                next_state = Int_Req_Wait;
639
                end
640
 
641
 
642
                // State 37
643
                Interrupt:
644
                begin
645
                        next_state = Wait_Program_Mem_1;
646
                end
647
 
648
 
649
                // State 38
650
                IRET:
651
                begin
652
                        next_state = Wait_Program_Mem_1;
653
                end
654
 
655
 
656
                default:
657
                begin
658
                        next_state = Reset;
659
                end
660
 
661
        endcase
662
 
663
end
664
 
665
 
666
// Output Decoder
667
always @ (*)
668
begin
669
 
670
        // Default Assignments
671
 
672
        pc_stack_val = pc_stack[16*stack_pointer +: 16];
673
        reg_a_val = registers[16*reg_a_num +: 16];
674
        reg_b_val = registers[16*reg_b_num +: 16];
675
        reg_c_val = registers[16*reg_c_num +: 16];
676
        sprite_level = registers[16*reg_a_num +: 6];
677
        rom_addr = program_counter;
678
        ram_wren = 0;
679
        ram_req = 0;
680
 
681
        case (current_state)
682
 
683
                // State 0
684
                Reset:
685
                begin
686
 
687
                end
688
 
689
                // State 1
690
                Wait_Program_Mem_1:
691
                begin
692
 
693
                end
694
 
695
                // State 2
696
                Decode_Instruction:
697
                begin
698
 
699
                end
700
 
701
                // State 3
702
                Wait_Operation:
703
                begin
704
 
705
                end
706
 
707
                // State 4
708
                Wait_DIV_1:
709
                begin
710
 
711
                end
712
 
713
                // State 5
714
                Wait_DIV_2:
715
                begin
716
 
717
                end
718
 
719
                // State 6
720
                Wait_DIV_3:
721
                begin
722
 
723
                end
724
 
725
                // State 7
726
                Wait_DIV_4:
727
                begin
728
 
729
                end
730
 
731
                // State 8
732
                ADD:
733
                begin
734
 
735
                end
736
 
737
                // State 9
738
                SUB:
739
                begin
740
 
741
                end
742
 
743
                // State 10
744
                MUL:
745
                begin
746
 
747
                end
748
 
749
                // State 11
750
                DIV:
751
                begin
752
 
753
                end
754
 
755
                // State 12
756
                AND:
757
                begin
758
 
759
                end
760
 
761
                // State 13
762
                OR:
763
                begin
764
 
765
                end
766
 
767
                // State 14
768
                CMP:
769
                begin
770
 
771
                end
772
 
773
                // State 15
774
                NOT:
775
                begin
776
 
777
                end
778
 
779
                // State 16
780
                SPRITE_ID:
781
                begin
782
 
783
                end
784
 
785
                // State 17
786
                SPRITE_COLOR:
787
                begin
788
 
789
                end
790
 
791
                // State 18
792
                SPRITE_POS:
793
                begin
794
 
795
                end
796
 
797
                // State 19
798
                LIMM:
799
                begin
800
 
801
                end
802
 
803
                // State 20
804
                LW_Begin:
805
                begin
806
                        ram_req = 1;
807
                end
808
 
809
                // State 21
810
                LW_Wait_1:
811
                begin
812
                        ram_req = 1;
813
                end
814
 
815
                // State 22
816
                LW_Wait_2:
817
                begin
818
                        ram_req = 1;
819
                end
820
 
821
                // State 23
822
                LW_End:
823
                begin
824
                        ram_req = 1;
825
                end
826
 
827
                // State 24
828
                SW_Begin:
829
                begin
830
                        ram_wren = 1;
831
                        ram_req = 1;
832
                end
833
 
834
                // State 25
835
                SW_End:
836
                begin
837
                        ram_wren = 1;
838
                        ram_req = 1;
839
                end
840
 
841
                // State 26
842
                JMP:
843
                begin
844
 
845
                end
846
 
847
 
848
 
849
 
850
 
851
                // State 27
852
                JR:
853
                begin
854
 
855
                end
856
 
857
                // State 28
858
                BRFL:
859
                begin
860
 
861
                end
862
 
863
                // State 29
864
                BRFLR:
865
                begin
866
 
867
                end
868
 
869
                // State 30
870
                NOP:
871
                begin
872
 
873
                end
874
 
875
                // State 31
876
                CALL:
877
                begin
878
 
879
                end
880
 
881
                // State 32
882
                CALLR:
883
                begin
884
 
885
                end
886
 
887
                // State 33
888
                RET:
889
                begin
890
 
891
                end
892
 
893
                // State 34
894
                WAIT_VSYNC:
895
                begin
896
 
897
                end
898
 
899
 
900
                // State 35
901
                Inc_Program_Counter:
902
                begin
903
 
904
                end
905
 
906
 
907
                // State 36
908
                Int_Req_Wait:
909
                begin
910
 
911
                end
912
 
913
 
914
                // State 37
915
                Interrupt:
916
                begin
917
 
918
                end
919
 
920
 
921
                // State 38
922
                IRET:
923
                begin
924
 
925
                end
926
 
927
 
928
                default:
929
                begin
930
 
931
                end
932
 
933
        endcase
934
end
935
 
936
 
937
// State Register and Reset Logic
938
always @ (posedge clock)
939
begin
940
 
941
        if (reset)
942
        begin
943
                current_state   <= Reset;
944
 
945
                program_counter <= code_start_addr;
946
                stack_pointer <= 3'b000;
947
                rflags <= 8'b00000000;
948
                int_ack <= 0;
949
 
950
        end
951
 
952
        else
953
        begin
954
                current_state   <=      next_state;
955
 
956
 
957
                // State: ADD
958
                if (next_state == ADD)
959
                begin
960
                        if (add_overflow)
961
                        begin
962
                                rflags[6] <= 1; //RFlags[overflow] = 1
963
                                registers[16*reg_a_num +: 16] <= 16'b1111111111111111;
964
                        end
965
 
966
                        else
967
                        begin
968
                                rflags[6] <= 0;  //RFlags[overflow] = 0
969
                                registers[16*reg_a_num +: 16] <= add_result;
970
                        end
971
                end
972
 
973
 
974
                // State: SUB
975
                if (next_state == SUB)
976
                begin
977
                        if (sub_overflow)
978
                        begin
979
                                rflags[6] <= 1; //RFlags[overflow] = 1
980
                                registers[16*reg_a_num +: 16] <= 16'b1111111111111111;
981
                        end
982
 
983
                        else
984
                        begin
985
                                rflags[6] <= 0;  //RFlags[overflow] = 0
986
                                registers[16*reg_a_num +: 16] <= sub_result;
987
                        end
988
                end
989
 
990
 
991
                // State: MUL
992
                if (next_state == MUL)
993
                begin
994
                        if ( (mult_result > 32'sd32767) || (mult_result < -32'sd32768) )
995
                        begin
996
                                rflags[6] <= 1; //RFlags[overflow] = 1
997
                                registers[16*reg_a_num +: 16] <= 16'b1111111111111111;
998
                        end
999
 
1000
                        else
1001
                        begin
1002
                                rflags[6] <= 0;  //RFlags[overflow] = 0
1003
                                registers[16*reg_a_num +: 16] <= mult_result[15:0];
1004
                        end
1005
                end
1006
 
1007
 
1008
                // State: DIV
1009
                if (next_state == DIV)
1010
                begin
1011
 
1012
                        if (reg_b_val == 16'd0)
1013
                        begin
1014
                                rflags[0] <= 1;  //RFlags[error] = 1
1015
                                rflags[6] <= 0;  //RFlags[overflow] = 0
1016
                                registers[16*reg_a_num +: 16] <= 16'b1111111111111111;
1017
                        end
1018
 
1019
                        else
1020
                        begin
1021
                                rflags[0] <= 0;   //RFlags[error] = 0
1022
 
1023
                                if ( (reg_a_val == 16'b1000000000000000) && (reg_b_val == 16'b1111111111111111) )
1024
                                begin
1025
                                        rflags[6] <= 1; //RFlags[overflow] = 1
1026
                                        registers[16*reg_a_num +: 16] <= 16'b1111111111111111;
1027
                                end
1028
 
1029
                                else
1030
                                begin
1031
                                        rflags[6] <= 0;  //RFlags[overflow] = 0
1032
                                        registers[16*reg_a_num +: 16] <= divide_quotient;
1033
                                end
1034
                        end
1035
                end
1036
 
1037
 
1038
                // State: AND
1039
                if (next_state == AND)
1040
                        registers[16*reg_a_num +: 16] <= reg_a_val & reg_b_val;
1041
 
1042
 
1043
                // State: OR
1044
                if (next_state == OR)
1045
                        registers[16*reg_a_num +: 16] <= reg_a_val | reg_b_val;
1046
 
1047
 
1048
                // State: CMP
1049
                if (next_state == CMP)
1050
                begin
1051
                        rflags[3] <= compare_alb;       //RFlags[below]
1052
                        rflags[4] <= compare_aeb;       //RFlags[equal]
1053
                        rflags[5] <= compare_agb;       //RFlags[above]
1054
                end
1055
 
1056
 
1057
                // State: NOT
1058
                if (next_state == NOT)
1059
                        registers[16*reg_a_num +: 16] <= ~ reg_a_val;
1060
 
1061
 
1062
                // State: SPRITE_ID
1063
                if (next_state == SPRITE_ID)
1064
                        sprite_id[6*sprite_level +: 6] <= reg_b_val[5:0];
1065
 
1066
 
1067
                // State: SPRITE_COLOR
1068
                if (next_state == SPRITE_COLOR)
1069
                        sprite_color[16*sprite_level +: 16] <= reg_b_val;
1070
 
1071
 
1072
                // State: SPRITE_POS
1073
                if (next_state == SPRITE_POS)
1074
                begin
1075
                        sprite_x[10*sprite_level +: 10] <= reg_c_val[9:0];
1076
                        sprite_y[10*sprite_level +: 10] <= reg_b_val[9:0];
1077
                end
1078
 
1079
 
1080
                // State: LIMM
1081
                if (next_state == LIMM)
1082
                        registers[16*reg_a_num +: 16] <= imm;
1083
 
1084
 
1085
                // State: LW_Begin
1086
                if (next_state == LW_Begin)
1087
                begin
1088
                        ram_addr <= reg_b_val + imm;
1089
                end
1090
 
1091
 
1092
                // State: LW_End
1093
                if (next_state == LW_End)
1094
                        registers[16*reg_a_num +: 16] <= ram_q;
1095
 
1096
 
1097
                // State: SW_Begin
1098
                if (next_state == SW_Begin)
1099
                begin
1100
                        ram_addr <= reg_b_val + imm;
1101
                        ram_data <= reg_a_val;
1102
                end
1103
 
1104
 
1105
                // State: JMP
1106
                if (next_state == JMP)
1107
                        program_counter <= imm;
1108
 
1109
 
1110
 
1111
 
1112
 
1113
                // State: JR
1114
                if (next_state == JR)
1115
                        program_counter <= reg_a_val;
1116
 
1117
 
1118
                // State: BRFL
1119
                if (next_state == BRFL)
1120
                begin
1121
                        program_counter <= imm;
1122
                end
1123
 
1124
 
1125
                // State: BRFLR
1126
                if (next_state == BRFLR)
1127
                begin
1128
                        program_counter <= reg_a_val;
1129
                end
1130
 
1131
 
1132
                // State: CALL
1133
                if (next_state == CALL)
1134
                begin
1135
                        pc_stack[16*stack_pointer +: 16] <= program_counter + 1'b1;
1136
                        program_counter <= imm;
1137
                        stack_pointer <= stack_pointer + 1'b1;
1138
                end
1139
 
1140
 
1141
                // State: CALLR
1142
                if (next_state == CALLR)
1143
                begin
1144
                        pc_stack[16*stack_pointer +: 16] <= program_counter + 1'b1;
1145
                        program_counter <= reg_a_val;
1146
                        stack_pointer <= stack_pointer + 1'b1;
1147
                end
1148
 
1149
 
1150
                // State: RET
1151
                if (next_state == RET)
1152
                begin
1153
                        program_counter <= pc_stack[16*(stack_pointer - 1) +: 16];
1154
                        stack_pointer <= stack_pointer - 1'b1;
1155
                end
1156
 
1157
 
1158
 
1159
 
1160
                // State: Inc_Program_Counter
1161
                if (next_state == Inc_Program_Counter)
1162
                begin
1163
                        program_counter <= program_counter + 1'b1;
1164
                end
1165
 
1166
 
1167
                // State: Int_Req_Wait
1168
                if (next_state == Int_Req_Wait)
1169
                begin
1170
                        int_ack <= 1;
1171
                end
1172
 
1173
 
1174
                // State: Interrupt
1175
                if (next_state == Interrupt)
1176
                begin
1177
                        int_rflags <= rflags;
1178
                        int_program_counter <= program_counter;
1179
                        program_counter <= isr_addr;
1180
                end
1181
 
1182
                // State: IRET
1183
                if (next_state == IRET)
1184
                begin
1185
                        int_ack <= 0;
1186
                        rflags <= int_rflags;
1187
                        program_counter <= int_program_counter;
1188
                end
1189
 
1190
 
1191
 
1192
        end
1193
 
1194
end
1195
 
1196
/*########################################################################*/
1197
/*########################################################################*/
1198
 
1199
 
1200
 
1201
 
1202
 
1203
 
1204
endmodule

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