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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [Project_Testbench_Processor.cr.mti] - Blame information for rev 2

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Line No. Rev Author Line
1 2 lucas.vbal 
C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity IP_SUB
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-- Compiling architecture SYN of ip_sub
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Reset_Synchronizer
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Top level modules:
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        Reset_Synchronizer
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Processor
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Top level modules:
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        Processor
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Memory_Arbiter
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Top level modules:
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        Memory_Arbiter
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package altera_mf_components
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-- Compiling entity IP_ROM_Program
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-- Compiling architecture SYN of ip_rom_program
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity IP_DIVIDE
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-- Compiling architecture SYN of ip_divide
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module SRAM_Interface
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Top level modules:
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        SRAM_Interface
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Processor_Controller
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Top level modules:
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        Processor_Controller
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity IP_PLL
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-- Compiling architecture SYN of ip_pll
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity IP_ADD
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-- Compiling architecture SYN of ip_add
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module VGA_Interface
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Top level modules:
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        VGA_Interface
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Sprite_Processor
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Top level modules:
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        Sprite_Processor
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity IP_MULT
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-- Compiling architecture SYN of ip_mult
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Genesis_6button_Interface
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Top level modules:
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        Genesis_6button_Interface
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Interrupt_Controller
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Top level modules:
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        Interrupt_Controller
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module Sprite_Shape_Reader
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Top level modules:
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        Sprite_Shape_Reader
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity IP_COMPARE
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-- Compiling architecture SYN of ip_compare
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v
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Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
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-- Compiling module TB_Processor
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Top level modules:
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        TB_Processor
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} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd
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Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package altera_mf_components
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-- Compiling entity IP_RAM_Data
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-- Compiling architecture SYN of ip_ram_data
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} {} {}}

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