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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [SRAM_Interface.v] - Blame information for rev 2

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1 2 lucas.vbal
 
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module SRAM_Interface (
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        iDATA,
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        iADDR,
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        oWE_N,
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        oOE_N,
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        oCE_N,
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        oLB_N,
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        oUB_N,
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        oADDR,
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        oRED,
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        oGREEN,
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        oBLUE
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);
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input   wire    [19:0]   iADDR;
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input           wire    [15:0]   iDATA;
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output          [7:0]            oRED;
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output          [7:0]            oGREEN;
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output          [7:0]            oBLUE;
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output          [19:0]   oADDR;
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output          oWE_N;
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output          oOE_N;
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output          oCE_N;
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output          oLB_N;
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output          oUB_N;
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assign  oWE_N = 1'b1;
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assign  oOE_N = 1'b0;
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assign  oCE_N = 1'b0;
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assign  oLB_N = 1'b0;
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assign  oUB_N = 1'b0;
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assign  oADDR = iADDR;
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assign  oRED            [2:0]    =       3'b000;
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assign  oRED            [7:3]   =       iDATA   [4:0];
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assign  oGREEN  [1:0]    =       2'b00;
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assign  oGREEN  [7:2]   =       iDATA   [10:5];
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assign  oBLUE           [2:0]    =       3'b000;
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assign  oBLUE           [7:3]   =       iDATA   [15:11];
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endmodule

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