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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [VGA_Interface.v] - Blame information for rev 2

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module VGA_Interface(
 
        clk,
        rst,
        R_in,
        G_in,
        B_in,
 
        oAddress,
        R,G,B,
        BLANK,
        VGA_SYNC,
        VGA_CLK,
        HS,VS,
        v_pos,
        h_pos
);
 
        input [7:0] R_in, G_in, B_in;
        input clk, rst;
 
        output reg [7:0] R, G, B;
        output reg HS, VS;
        output reg BLANK;
        output VGA_SYNC, VGA_CLK;
 
        output reg [9:0] h_pos, v_pos;
        output reg [19:0]        oAddress;
 
        parameter H_FRONT = 16; //16
        parameter H_SYNC = 96;  //96
        parameter H_BACK = 48;  //48
        parameter H_DISPLAY = 640;
        parameter H_BLANK = H_SYNC+H_BACK;
        parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_DISPLAY;
 
        parameter V_FRONT = 10; //12
        parameter V_SYNC = 2;   //2
        parameter V_BACK = 33;  //31
        parameter V_DISPLAY     = 480;
        parameter V_BLANK = V_SYNC+V_BACK;
        parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_DISPLAY;
 
 
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        h_pos <= 10'b0000000000;
                        v_pos <= 10'b0000000000;
                end
 
                else
                begin
                        if (h_pos<H_TOTAL-1)//800 pulsos
                        begin
                                h_pos <= h_pos + 1'b1;
                        end
 
                        else
                        begin
                                h_pos <= 1'b0;
 
                                if (v_pos<V_TOTAL-1)//525 pulsos
                                begin
                                        v_pos <= v_pos + 1'b1;
                                end
 
                                else
                                begin
                                        v_pos <= 1'b0;
                                end
                        end
                end
        end
 
        // Sincronismo Horizontal
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        HS <= 1'b1;
                end
                else
                begin
                        if ( (h_pos > H_BACK+H_DISPLAY+H_FRONT-1) && (h_pos < H_TOTAL) )
                        begin
                                HS <= 1'b0;
                        end
                        else
                        begin
                                HS <= 1'b1;
                        end
                end
        end
 
        // Sincronismo Vertical
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        VS <= 1'b1;
                end
                else
                begin
                        if ( (v_pos > V_BACK+V_DISPLAY+V_FRONT-1) && (v_pos < V_TOTAL) )
                        begin
                                VS <= 1'b0;
                        end
                        else
                        begin
                                VS <= 1'b1;
                        end
                end
        end
 
        // Blank
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        BLANK <= 1'b1;
                end
                else
                begin
                        if ( (h_pos<H_BACK) || (h_pos > H_BACK+H_DISPLAY-1) || (v_pos<V_BACK) || (v_pos > V_BACK+V_DISPLAY-1) )
                        begin
                                BLANK <= 1'b0;
                        end
                        else
                        begin
                                BLANK <= 1'b1;
                        end
                end
        end
 
        assign VGA_CLK = clk;
        assign VGA_SYNC = 1'b0;
 
        always @(posedge clk )
        begin
                R <= R_in;
                G <= G_in;
                B <= B_in;
        end
 
 
        // Bloco para geracao dos enderecos de cada pixel na memoria
        // Cada pixel está guardado em um endereco diferente, sequencialmente
        always @(posedge clk )
        begin
 
                // Reset no circuito, endereco vai para zero
                if (rst == 1'b1)
                begin
                        oAddress <= 20'h00000;
                end
 
                // Operacao normal, apos reset
                else
                begin
                        // Operacao na parte visivel do video
                        if( (h_pos>H_BACK-1) && (h_pos < H_BACK+H_DISPLAY) && (v_pos>V_BACK-1) && (v_pos < V_BACK+V_DISPLAY) )
                        begin
 
                                // Enquanto nao tiver atingido o ultimo pixel
                                if ( oAddress < ((H_DISPLAY*V_DISPLAY) - 1)  )
                                begin
                                        oAddress <= oAddress + 1'b1;
                                end
 
                                // Retorna para o inicio apos atingir o ultimo pixel
                                else
                                begin
                                        oAddress <= 1'b0;
                                end
 
                        end
 
                        // Operacao na parte de sincronismo do video
                        else
                        begin
                                oAddress <= oAddress;
                        end
                end
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	lucas.vbal	`module VGA_Interface(`
2
3			`clk,`
4			`rst,`
5			`R_in,`
6			`G_in,`
7			`B_in,`
8
9			`oAddress,`
10			`R,G,B,`
11			`BLANK,`
12			`VGA_SYNC,`
13			`VGA_CLK,`
14			`HS,VS,`
15			`v_pos,`
16			`h_pos`
17			`);`
18
19			`input [7:0] R_in, G_in, B_in;`
20			`input clk, rst;`
21
22			`output reg [7:0] R, G, B;`
23			`output reg HS, VS;`
24			`output reg BLANK;`
25			`output VGA_SYNC, VGA_CLK;`
26
27			`output reg [9:0] h_pos, v_pos;`
28			`output reg [19:0] oAddress;`
29
30			`parameter H_FRONT = 16; //16`
31			`parameter H_SYNC = 96; //96`
32			`parameter H_BACK = 48; //48`
33			`parameter H_DISPLAY = 640;`
34			`parameter H_BLANK = H_SYNC+H_BACK;`
35			`parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_DISPLAY;`
36
37			`parameter V_FRONT = 10; //12`
38			`parameter V_SYNC = 2; //2`
39			`parameter V_BACK = 33; //31`
40			`parameter V_DISPLAY = 480;`
41			`parameter V_BLANK = V_SYNC+V_BACK;`
42			`parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_DISPLAY;`
43
44
45			`always @(posedge clk)`
46			`begin`
47			`if (rst == 1'b1)`
48			`begin`
49			`h_pos <= 10'b0000000000;`
50			`v_pos <= 10'b0000000000;`
51			`end`
52
53			`else`
54			`begin`
55			`if (h_pos<H_TOTAL-1)//800 pulsos`
56			`begin`
57			`h_pos <= h_pos + 1'b1;`
58			`end`
59
60			`else`
61			`begin`
62			`h_pos <= 1'b0;`
63
64			`if (v_pos<V_TOTAL-1)//525 pulsos`
65			`begin`
66			`v_pos <= v_pos + 1'b1;`
67			`end`
68
69			`else`
70			`begin`
71			`v_pos <= 1'b0;`
72			`end`
73			`end`
74			`end`
75			`end`
76
77			`// Sincronismo Horizontal`
78			`always @(posedge clk)`
79			`begin`
80			`if (rst == 1'b1)`
81			`begin`
82			`HS <= 1'b1;`
83			`end`
84			`else`
85			`begin`
86			`if ( (h_pos > H_BACK+H_DISPLAY+H_FRONT-1) && (h_pos < H_TOTAL) )`
87			`begin`
88			`HS <= 1'b0;`
89			`end`
90			`else`
91			`begin`
92			`HS <= 1'b1;`
93			`end`
94			`end`
95			`end`
96
97			`// Sincronismo Vertical`
98			`always @(posedge clk)`
99			`begin`
100			`if (rst == 1'b1)`
101			`begin`
102			`VS <= 1'b1;`
103			`end`
104			`else`
105			`begin`
106			`if ( (v_pos > V_BACK+V_DISPLAY+V_FRONT-1) && (v_pos < V_TOTAL) )`
107			`begin`
108			`VS <= 1'b0;`
109			`end`
110			`else`
111			`begin`
112			`VS <= 1'b1;`
113			`end`
114			`end`
115			`end`
116
117			`// Blank`
118			`always @(posedge clk)`
119			`begin`
120			`if (rst == 1'b1)`
121			`begin`
122			`BLANK <= 1'b1;`
123			`end`
124			`else`
125			`begin`
126			`if ( (h_pos<H_BACK) \|\| (h_pos > H_BACK+H_DISPLAY-1) \|\| (v_pos<V_BACK) \|\| (v_pos > V_BACK+V_DISPLAY-1) )`
127			`begin`
128			`BLANK <= 1'b0;`
129			`end`
130			`else`
131			`begin`
132			`BLANK <= 1'b1;`
133			`end`
134			`end`
135			`end`
136
137			`assign VGA_CLK = clk;`
138			`assign VGA_SYNC = 1'b0;`
139
140			`always @(posedge clk )`
141			`begin`
142			`R <= R_in;`
143			`G <= G_in;`
144			`B <= B_in;`
145			`end`
146
147
148			`// Bloco para geracao dos enderecos de cada pixel na memoria`
149			`// Cada pixel está guardado em um endereco diferente, sequencialmente`
150			`always @(posedge clk )`
151			`begin`
152
153			`// Reset no circuito, endereco vai para zero`
154			`if (rst == 1'b1)`
155			`begin`
156			`oAddress <= 20'h00000;`
157			`end`
158
159			`// Operacao normal, apos reset`
160			`else`
161			`begin`
162			`// Operacao na parte visivel do video`
163			`if( (h_pos>H_BACK-1) && (h_pos < H_BACK+H_DISPLAY) && (v_pos>V_BACK-1) && (v_pos < V_BACK+V_DISPLAY) )`
164			`begin`
165
166			`// Enquanto nao tiver atingido o ultimo pixel`
167			`if ( oAddress < ((H_DISPLAY*V_DISPLAY) - 1) )`
168			`begin`
169			`oAddress <= oAddress + 1'b1;`
170			`end`
171
172			`// Retorna para o inicio apos atingir o ultimo pixel`
173			`else`
174			`begin`
175			`oAddress <= 1'b0;`
176			`end`
177
178			`end`
179
180			`// Operacao na parte de sincronismo do video`
181			`else`
182			`begin`
183			`oAddress <= oAddress;`
184			`end`
185			`end`
186			`end`
187
188			`endmodule`

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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [VGA_Interface.v] - Blame information for rev 2