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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [work/] [_info] - Blame information for rev 2

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1 2 lucas.vbal
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!s112 1.1
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!i10d 8192
7
!i10e 25
8
!i10f 100
9
cModel Technology
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dC:/intelFPGA/17.0
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vGenesis_6button_Interface
12
Z0 !s110 1531706168
13
!i10b 1
14
!s100 5YDRCP[^PLhb?HS0EIFPh2
15
IlzCYJ[QaJjAXOJ`UZUdg?3
16
Z1 VDg1SIo80bB@j0V0VzS_@n1
17
Z2 dC:/Users/Lucas/Desktop/TCC/Processor_ModelSim
18
w1530371484
19
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v
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FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v
21
L0 1
22
Z3 OV;L;10.5b;63
23
r1
24
!s85 0
25
31
26
Z4 !s108 1531706168.000000
27
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v|
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!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v|
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!i113 1
30
Z5 o-work work
31
Z6 tCvgOpt 0
32
n@genesis_6button_@interface
33
vInterrupt_Controller
34
Z7 !s110 1531706169
35
!i10b 1
36
!s100 1LRR9?YgIooCc:o4Kd52A1
37
I=8YBF
38
R1
39
R2
40
w1525207608
41
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v
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FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v
43
L0 1
44
R3
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r1
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!s85 0
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31
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R4
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!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v|
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!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v|
51
!i113 1
52
R5
53
R6
54
n@interrupt_@controller
55
Eip_add
56
Z8 w1520454852
57
Z9 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
58
Z10 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1
59
R2
60
Z11 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd
61
Z12 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd
62
l0
63
L43
64
Vd1AXYR_9G]W]
65
!s100 `m7Q0n_>_PK5DgL;^SJkI0
66
Z13 OV;C;10.5b;63
67
32
68
R7
69
!i10b 1
70
Z14 !s108 1531706169.000000
71
Z15 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd|
72
Z16 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd|
73
!i113 1
74
Z17 o-work work -2002 -explicit
75
Z18 tExplicit 1 CvgOpt 0
76
Asyn
77
R9
78
R10
79
DEx4 work 6 ip_add 0 22 d1AXYR_9G]W]
80
l80
81
L55
82
Vi84Blfb[n=_PD3QlU[bb`0
83
!s100 h7F4lbgd`cHOV8On^0
84
R13
85
32
86
R7
87
!i10b 1
88
R14
89
R15
90
R16
91
!i113 1
92
R17
93
R18
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Eip_compare
95
Z19 w1520474075
96
R9
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R10
98
R2
99
Z20 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd
100
Z21 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd
101
l0
102
L43
103
V5W1
104
!s100 j5a8kfY_IW]cV37eH
105
R13
106
32
107
R7
108
!i10b 1
109
R14
110
Z22 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd|
111
Z23 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd|
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!i113 1
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R17
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R18
115
Asyn
116
R9
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R10
118
DEx4 work 10 ip_compare 0 22 5W1
119
l81
120
L56
121
VAI^Vj<=4glm8:
122
!s100 iNQ1@ijagM1NNK_8Wb=nn0
123
R13
124
32
125
R7
126
!i10b 1
127
R14
128
R22
129
R23
130
!i113 1
131
R17
132
R18
133
Eip_divide
134
Z24 w1530386675
135
R9
136
R10
137
R2
138
Z25 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd
139
Z26 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd
140
l0
141
L43
142
V=3
143
!s100 >eallAU?fX?UDIifT5o7P3
144
R13
145
32
146
R7
147
!i10b 1
148
R14
149
Z27 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd|
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Z28 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd|
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!i113 1
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R17
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R18
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Asyn
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R9
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R10
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DEx4 work 9 ip_divide 0 22 =3
158
l81
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L55
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VPNl2B=0[_mR>^DhXFSNEX3
161
!s100 SiRIoU^Iblg3kCFD:XXBR2
162
R13
163
32
164
R7
165
!i10b 1
166
R14
167
R27
168
R28
169
!i113 1
170
R17
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R18
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Eip_mult
173
Z29 w1522805773
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R9
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R10
176
R2
177
Z30 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd
178
Z31 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd
179
l0
180
L43
181
V6F4;ceEc;n`U5GmcYYoB41
182
!s100 3lif@Ti:6T;]kM]M4JSDB0
183
R13
184
32
185
Z32 !s110 1531706170
186
!i10b 1
187
Z33 !s108 1531706170.000000
188
Z34 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd|
189
Z35 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd|
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!i113 1
191
R17
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R18
193
Asyn
194
R9
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R10
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DEx4 work 7 ip_mult 0 22 6F4;ceEc;n`U5GmcYYoB41
197
l78
198
L54
199
VVA@IzCSbFkW_a_25lAC8Q2
200
!s100 l]@QIH@5meOAPLTajfb];1
201
R13
202
32
203
R32
204
!i10b 1
205
R33
206
R34
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R35
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!i113 1
209
R17
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R18
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Eip_pll
212
Z36 w1525568790
213
R9
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R10
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R2
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Z37 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd
217
Z38 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd
218
l0
219
L43
220
V]>eAO8Mb
221
!s100 1XN1FnDQg^N8m1aSL``A@1
222
R13
223
32
224
R32
225
!i10b 1
226
R33
227
Z39 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd|
228
Z40 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd|
229
!i113 1
230
R17
231
R18
232
Asyn
233
R9
234
R10
235
DEx4 work 6 ip_pll 0 22 ]>eAO8Mb
236
l126
237
L52
238
V[Ffffd@QZ6z7j[P2MRK3n1
239
!s100 8kh58kb7a@1lZdfPz8RkQ3
240
R13
241
32
242
R32
243
!i10b 1
244
R33
245
R39
246
R40
247
!i113 1
248
R17
249
R18
250
Eip_ram_data
251
Z41 w1526428777
252
Z42 DPx9 altera_mf 20 altera_mf_components 0 22 :YRc5
253
R9
254
R10
255
R2
256
Z43 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd
257
Z44 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd
258
l0
259
L43
260
V^QQO99U1LDZLMWD]>zEg73
261
!s100 >:@`Z`hQO?<8XXzA]G9
262
R13
263
32
264
R32
265
!i10b 1
266
R33
267
Z45 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd|
268
Z46 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd|
269
!i113 1
270
R17
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R18
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Asyn
273
R42
274
R9
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R10
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DEx4 work 11 ip_ram_data 0 22 ^QQO99U1LDZLMWD]>zEg73
277
l59
278
L55
279
Vo:[=mSS9>DJ_[ae2i=Y=`1
280
!s100 gh:BI@W=:6LbB
281
R13
282
32
283
R32
284
!i10b 1
285
R33
286
R45
287
R46
288
!i113 1
289
R17
290
R18
291
Eip_rom_program
292
Z47 w1525012912
293
R42
294
R9
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R10
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R2
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Z48 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd
298
Z49 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd
299
l0
300
L43
301
V3RcQ:l6NU`e=1f:dC:Ij<2
302
!s100 iY6C[l7_2ZBfWjEF`R>T?2
303
R13
304
32
305
Z50 !s110 1531706171
306
!i10b 1
307
Z51 !s108 1531706171.000000
308
Z52 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd|
309
Z53 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd|
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!i113 1
311
R17
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R18
313
Asyn
314
R42
315
R9
316
R10
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DEx4 work 14 ip_rom_program 0 22 3RcQ:l6NU`e=1f:dC:Ij<2
318
l57
319
L53
320
V62EPF=6PCYAz;>emm`lRh3
321
!s100 Oi:gi=gI=M@VLjNLIA7NL0
322
R13
323
32
324
R50
325
!i10b 1
326
R51
327
R52
328
R53
329
!i113 1
330
R17
331
R18
332
Eip_sub
333
Z54 w1520455019
334
R9
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R10
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R2
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Z55 8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd
338
Z56 FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd
339
l0
340
L43
341
V3_PWE861Fa41?f1B9@NMD3
342
!s100 
343
R13
344
32
345
R50
346
!i10b 1
347
R51
348
Z57 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd|
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Z58 !s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd|
350
!i113 1
351
R17
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R18
353
Asyn
354
R9
355
R10
356
DEx4 work 6 ip_sub 0 22 3_PWE861Fa41?f1B9@NMD3
357
l80
358
L55
359
VD?_jNZNKd^YLoHS^ZJ;d51
360
!s100 EUm]c4d1OJ]T9NC>1NU4K3
361
R13
362
32
363
R50
364
!i10b 1
365
R51
366
R57
367
R58
368
!i113 1
369
R17
370
R18
371
vMemory_Arbiter
372
R50
373
!i10b 1
374
!s100 ]^RhA4=@z`S=cH]TJ;Ng]0
375
ICGkGg18gbjX@]9_2@6YgX3
376
R1
377
R2
378
w1525139685
379
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v
380
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v
381
L0 1
382
R3
383
r1
384
!s85 0
385
31
386
R51
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!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v|
388
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v|
389
!i113 1
390
R5
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R6
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n@memory_@arbiter
393
vMemory_Reader_FSM
394
!s110 1528685825
395
!i10b 1
396
!s100 gm]=ZzB1QBAM:beTA=2W42
397
I1X_PIFEob`;REj>B=IY8@3
398
R1
399
R2
400
w1526435127
401
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Reader_FSM.v
402
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Reader_FSM.v
403
L0 2
404
R3
405
r1
406
!s85 0
407
31
408
!s108 1528685825.000000
409
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Reader_FSM.v|
410
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Reader_FSM.v|
411
!i113 1
412
R5
413
R6
414
n@memory_@reader_@f@s@m
415
vProcessor
416
Z59 !s110 1531706172
417
!i10b 1
418
!s100 K;eebT]65CaNa:nJ
419
ICA^N]4
420
R1
421
R2
422
w1531703328
423
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v
424
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v
425
L0 20
426
R3
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r1
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!s85 0
429
31
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Z60 !s108 1531706172.000000
431
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v|
432
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v|
433
!i113 1
434
R5
435
R6
436
n@processor
437
vProcessor_Controller
438
R59
439
!i10b 1
440
!s100 HiS4Nlime90L@z0k>1SZW2
441
I7hR`eC;S^K51kM:ghS:9P3
442
R1
443
R2
444
w1526427782
445
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v
446
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v
447
L0 1
448
R3
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r1
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!s85 0
451
31
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R60
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!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v|
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!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v|
455
!i113 1
456
R5
457
R6
458
n@processor_@controller
459
vReset_Synchronizer
460
R59
461
!i10b 1
462
!s100 YAJka4WNh4D3GeSJ3DTMB0
463
IJ<820ko3I@m^JJ?9>^zee1
464
R1
465
R2
466
w1526602542
467
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v
468
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v
469
L0 1
470
R3
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r1
472
!s85 0
473
31
474
R60
475
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v|
476
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v|
477
!i113 1
478
R5
479
R6
480
n@reset_@synchronizer
481
vSega_Genesis_6button_Controller
482
!s110 1528685826
483
!i10b 1
484
!s100 j=FeIFiVgzPDGQbgTjhMe2
485
Io
486
R1
487
R2
488
w1526268585
489
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sega_Genesis_6button_Controller.v
490
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sega_Genesis_6button_Controller.v
491
L0 1
492
R3
493
r1
494
!s85 0
495
31
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!s108 1528685826.000000
497
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sega_Genesis_6button_Controller.v|
498
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sega_Genesis_6button_Controller.v|
499
!i113 1
500
R5
501
R6
502
n@sega_@genesis_6button_@controller
503
vSprite_Processor
504
Z61 !s110 1531706173
505
!i10b 1
506
!s100 A9gf;DH2;7?cG9Rd_zO>71
507
IVYXe@c[11mjgG<7]DOXZB0
508
R1
509
R2
510
w1528680799
511
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v
512
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v
513
L0 1
514
R3
515
r1
516
!s85 0
517
31
518
R60
519
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v|
520
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v|
521
!i113 1
522
R5
523
R6
524
n@sprite_@processor
525
vSprite_Shape_Reader
526
R61
527
!i10b 1
528
!s100 Z2OdmlIBl7U>lkK5TF8540
529
IcFEoPMFUGz[ogDZ`USKjd0
530
R1
531
R2
532
w1526530167
533
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v
534
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v
535
L0 1
536
R3
537
r1
538
!s85 0
539
31
540
Z62 !s108 1531706173.000000
541
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v|
542
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v|
543
!i113 1
544
R5
545
R6
546
n@sprite_@shape_@reader
547
vSRAM_Controller
548
!s110 1528685827
549
!i10b 1
550
!s100 9JB19mmk;XYAzz]7ZM7^03
551
IVMGK@Igjcgb3Xh4KXRzHT0
552
R1
553
R2
554
w1499552154
555
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Controller.v
556
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Controller.v
557
L0 1
558
R3
559
r1
560
!s85 0
561
31
562
!s108 1528685827.000000
563
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Controller.v|
564
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Controller.v|
565
!i113 1
566
R5
567
R6
568
n@s@r@a@m_@controller
569
vSRAM_Interface
570
R61
571
!i10b 1
572
!s100 RHolWzfg23zb;4Gfh6C1O3
573
IWdLDBOmOVa
574
R1
575
R2
576
w1530377394
577
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v
578
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v
579
L0 2
580
R3
581
r1
582
!s85 0
583
31
584
R62
585
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v|
586
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v|
587
!i113 1
588
R5
589
R6
590
n@s@r@a@m_@interface
591
vTB_Processor
592
R0
593
!i10b 1
594
!s100 ^AofD]WJB82NZMEd^izb13
595
I@TYa=4d`gC@a61Kl
596
R1
597
R2
598
w1531706166
599
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v
600
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v
601
L0 4
602
R3
603
r1
604
!s85 0
605
31
606
R4
607
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v|
608
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v|
609
!i113 1
610
R5
611
R6
612
n@t@b_@processor
613
vVGA_Interface
614
R61
615
!i10b 1
616
!s100 o4LBe6LB4PSS0LAX_bEL>1
617
In?NT>nzR=JVCd2eMD:;eM3
618
R1
619
R2
620
w1531700427
621
8C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v
622
FC:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v
623
L0 1
624
R3
625
r1
626
!s85 0
627
31
628
R62
629
!s107 C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v|
630
!s90 -reportprogress|300|-work|work|-stats=none|C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v|
631
!i113 1
632
R5
633
R6
634
n@v@g@a_@interface

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