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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Genesis_6button_Interface.v] - Blame information for rev 2

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module Genesis_6button_Interface(
 
clock,
reset,
mem_grant,
up_z,
down_y,
left_x,
right_mode,
b_a,
c_start,
v_sync,
int_ack,
 
mem_addr,
mem_data,
mem_wren,
mem_req,
counter,
buttons,
current_state,
next_state,
select,
v_sync_flag,
int_req
 
);
 
 
input   up_z;
input   down_y;
input           left_x;
input           right_mode;
input           b_a;
input           c_start;
input           mem_grant;
input           int_ack;
input   v_sync;
input   clock;
input   reset;
 
 
output reg      [9:0]    counter;
output reg      [15:0]   buttons;
 
output reg      [15:0]   mem_addr;
output reg      [15:0]   mem_data;
output reg      mem_wren;
output reg      mem_req;
output reg      int_req;
output reg      select;
output          v_sync_flag;
 
 
/*########################################################################*/
/*#################  Video vertical sync edge-detection  #################*/
/*########################################################################*/
 
reg   v_sync_delay;
 
always @ (posedge clock)
begin
        v_sync_delay <= v_sync;
end
 
assign v_sync_flag = ~v_sync & v_sync_delay;
 
/*########################################################################*/
/*########################################################################*/
 
 
/*########################################################################*/
/*########################  FINITE STATE MACHINE  ########################*/
/*########################  SEGA GENESIS          ########################*/
/*########################  6-BUTTON CONTROLLER   ########################*/
/*########################################################################*/
 
output reg      [3:0]            current_state;
output reg      [3:0]            next_state;
 
// States
parameter       Reset                   = 4'b0000;      // Reset                        = 0
parameter       Wait_Frame      = 4'b0001;      // Wait_Frame   = 1
parameter       Step_0          = 4'b0010;      // Step_0               = 2
parameter       Step_1          = 4'b0011;      // Step_1               = 3
parameter       Step_2          = 4'b0100;      // Step_2               = 4
parameter       Step_3          = 4'b0101;      // Step_3               = 5
parameter       Step_4          = 4'b0110;      // Step_4               = 6
parameter       Step_5          = 4'b0111;      // Step_5               = 7
parameter       Step_6          = 4'b1000;      // Step_6               = 8
parameter       Step_7          = 4'b1001;      // Step_7               = 9
parameter       Write_Data      = 4'b1010;      // Write_Data   = 10
parameter       Wait_Mem                = 4'b1011;      // Wait_Mem             = 11
parameter       Int_Req         = 4'b1100;      // Int_Req              = 12
 
 
// Next State Decoder
always @ (*)
begin
        case (current_state)
 
                // State 0
                Reset:
                begin
                        next_state = Wait_Frame;
                end
 
                // State 1
                Wait_Frame:
                begin
                        if (v_sync_flag)
                                next_state = Step_0;
                        else
                                next_state = Wait_Frame;
                end
 
                // State 2
                Step_0:
                begin
                        if (counter > 1000)
                                next_state = Step_1;
                        else
                                next_state = Step_0;
                end
 
                // State 3
                Step_1:
                begin
                        if (counter > 1000)
                                next_state = Step_2;
                        else
                                next_state = Step_1;
                end
 
                // State 4
                Step_2:
                begin
                        if (counter > 1000)
                                next_state = Step_3;
                        else
                                next_state = Step_2;
                end
 
                // State 5
                Step_3:
                begin
                        if (counter > 1000)
                                next_state = Step_4;
                        else
                                next_state = Step_3;
                end
 
                // State 6
                Step_4:
                begin
                        if (counter > 1000)
                                next_state = Step_5;
                        else
                                next_state = Step_4;
                end
 
                // State 7
                Step_5:
                begin
                        if (counter > 1000)
                                next_state = Step_6;
                        else
                                next_state = Step_5;
                end
 
                // State 8
                Step_6:
                begin
                        if (counter > 1000)
                                next_state = Step_7;
                        else
                                next_state = Step_6;
                end
 
                // State 9
                Step_7:
                begin
                        if (counter <= 1000)
                        begin
                                next_state = Step_7;
                        end
 
                        else if ( (counter > 1000) && (buttons != mem_data) && (buttons != 0) && (! int_ack) )
                        begin
                                next_state = Write_Data;
                        end
 
                        else if ( (counter > 1000) && (buttons == mem_data) && (buttons != 0) && (! int_ack) )
                        begin
                                next_state = Int_Req;
                        end
 
                        else
                        begin
                                next_state = Wait_Frame;
                        end
                end
 
                // State 10
                Write_Data:
                begin
                        if (mem_grant)
                                next_state = Wait_Mem;
                        else
                                next_state = Write_Data;
                end
 
                // State 11
                Wait_Mem:
                begin
                        next_state = Int_Req;
                end
 
                // State 12
                Int_Req:
                begin
                        if (int_ack)
                                next_state = Wait_Frame;
                        else
                                next_state = Int_Req;
                end
 
                default:
                begin
                        next_state = Reset;
                end
 
        endcase
 
end
 
 
// Output Decoder
always @ (*)
begin
 
        // Default Assignments
        select = 1;
        mem_addr = 16'd1025;
        mem_wren = 0;
        mem_req = 0;
        int_req = 0;
 
 
        case (current_state)
 
                // State 0
                Reset:
                begin
 
                end
 
                // State 1
                Wait_Frame:
                begin
 
                end
 
                // State 2
                Step_0:
                begin
 
                end
 
                // State 3
                Step_1:
                begin
                        select = 0;
                end
 
                // State 4
                Step_2:
                begin
 
                end
 
                // State 5
                Step_3:
                begin
                        select = 0;
                end
 
                // State 6
                Step_4:
                begin
 
                end
 
                // State 7
                Step_5:
                begin
                        select = 0;
                end
 
                // State 8
                Step_6:
                begin
 
                end
 
                // State 9
                Step_7:
                begin
                        select = 0;
                end
 
                // State 10
                Write_Data:
                begin
                        mem_wren = 1;
                        mem_req = 1;
                end
 
                // State 11
                Wait_Mem:
                begin
                        mem_wren = 1;
                        mem_req = 1;
                end
 
                // State 12
                Int_Req:
                begin
                        int_req = 1;
                end
 
                default:
                begin
 
                end
 
        endcase
end
 
 
// State Register and Reset Logic
always @ (posedge clock)
begin
 
        if (reset)
        begin
                current_state   <= Reset;
 
                // State: Reset
                mem_data <= 16'd0;
                buttons <= 16'd0;
                counter <= 10'd0;
 
        end
 
        else
        begin
                current_state   <=      next_state;
 
                // State: Step_0
                if (next_state == Step_0)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_1
                if (next_state == Step_1)
                begin
                        buttons[6] <= ~ b_a;
                        buttons[7] <= ~ c_start;
 
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_2
                if (next_state == Step_2)
                begin
                        buttons[0] <= ~ up_z;
                        buttons[1] <= ~ down_y;
                        buttons[2] <= ~ left_x;
                        buttons[3] <= ~ right_mode;
                        buttons[4] <= ~ b_a;
                        buttons[5] <= ~ c_start;
 
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_3
                if (next_state == Step_3)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_4
                if (next_state == Step_4)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_5
                if (next_state == Step_5)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_6
                if (next_state == Step_6)
                begin
                        buttons[8] <= ~ up_z;
                        buttons[9] <= ~ down_y;
                        buttons[10] <= ~ left_x;
                        buttons[11] <= ~ right_mode;
 
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_7
                if (next_state == Step_7)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Write_Data
                if (next_state == Write_Data)
                begin
                        mem_data <= buttons;
                end
 
 
        end
 
end
 
/*########################################################################*/
/*########################################################################*/
 
 
endmodule

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Subversion Repositories 2d_game_console

[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Genesis_6button_Interface.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	lucas.vbal	`module Genesis_6button_Interface(`
2
3			`clock,`
4			`reset,`
5			`mem_grant,`
6			`up_z,`
7			`down_y,`
8			`left_x,`
9			`right_mode,`
10			`b_a,`
11			`c_start,`
12			`v_sync,`
13			`int_ack,`
14
15			`mem_addr,`
16			`mem_data,`
17			`mem_wren,`
18			`mem_req,`
19			`counter,`
20			`buttons,`
21			`current_state,`
22			`next_state,`
23			`select,`
24			`v_sync_flag,`
25			`int_req`
26
27			`);`
28
29
30			`input up_z;`
31			`input down_y;`
32			`input left_x;`
33			`input right_mode;`
34			`input b_a;`
35			`input c_start;`
36			`input mem_grant;`
37			`input int_ack;`
38			`input v_sync;`
39			`input clock;`
40			`input reset;`
41
42
43			`output reg [9:0] counter;`
44			`output reg [15:0] buttons;`
45
46			`output reg [15:0] mem_addr;`
47			`output reg [15:0] mem_data;`
48			`output reg mem_wren;`
49			`output reg mem_req;`
50			`output reg int_req;`
51			`output reg select;`
52			`output v_sync_flag;`
53
54
55			`/########################################################################/`
56			`/################# Video vertical sync edge-detection #################/`
57			`/########################################################################/`
58
59			`reg v_sync_delay;`
60
61			`always @ (posedge clock)`
62			`begin`
63			`v_sync_delay <= v_sync;`
64			`end`
65
66			`assign v_sync_flag = ~v_sync & v_sync_delay;`
67
68			`/########################################################################/`
69			`/########################################################################/`
70
71
72			`/########################################################################/`
73			`/######################## FINITE STATE MACHINE ########################/`
74			`/######################## SEGA GENESIS ########################/`
75			`/######################## 6-BUTTON CONTROLLER ########################/`
76			`/########################################################################/`
77
78			`output reg [3:0] current_state;`
79			`output reg [3:0] next_state;`
80
81			`// States`
82			`parameter Reset = 4'b0000; // Reset = 0`
83			`parameter Wait_Frame = 4'b0001; // Wait_Frame = 1`
84			`parameter Step_0 = 4'b0010; // Step_0 = 2`
85			`parameter Step_1 = 4'b0011; // Step_1 = 3`
86			`parameter Step_2 = 4'b0100; // Step_2 = 4`
87			`parameter Step_3 = 4'b0101; // Step_3 = 5`
88			`parameter Step_4 = 4'b0110; // Step_4 = 6`
89			`parameter Step_5 = 4'b0111; // Step_5 = 7`
90			`parameter Step_6 = 4'b1000; // Step_6 = 8`
91			`parameter Step_7 = 4'b1001; // Step_7 = 9`
92			`parameter Write_Data = 4'b1010; // Write_Data = 10`
93			`parameter Wait_Mem = 4'b1011; // Wait_Mem = 11`
94			`parameter Int_Req = 4'b1100; // Int_Req = 12`
95
96
97			`// Next State Decoder`
98			`always @ (*)`
99			`begin`
100			`case (current_state)`
101
102			`// State 0`
103			`Reset:`
104			`begin`
105			`next_state = Wait_Frame;`
106			`end`
107
108			`// State 1`
109			`Wait_Frame:`
110			`begin`
111			`if (v_sync_flag)`
112			`next_state = Step_0;`
113			`else`
114			`next_state = Wait_Frame;`
115			`end`
116
117			`// State 2`
118			`Step_0:`
119			`begin`
120			`if (counter > 1000)`
121			`next_state = Step_1;`
122			`else`
123			`next_state = Step_0;`
124			`end`
125
126			`// State 3`
127			`Step_1:`
128			`begin`
129			`if (counter > 1000)`
130			`next_state = Step_2;`
131			`else`
132			`next_state = Step_1;`
133			`end`
134
135			`// State 4`
136			`Step_2:`
137			`begin`
138			`if (counter > 1000)`
139			`next_state = Step_3;`
140			`else`
141			`next_state = Step_2;`
142			`end`
143
144			`// State 5`
145			`Step_3:`
146			`begin`
147			`if (counter > 1000)`
148			`next_state = Step_4;`
149			`else`
150			`next_state = Step_3;`
151			`end`
152
153			`// State 6`
154			`Step_4:`
155			`begin`
156			`if (counter > 1000)`
157			`next_state = Step_5;`
158			`else`
159			`next_state = Step_4;`
160			`end`
161
162			`// State 7`
163			`Step_5:`
164			`begin`
165			`if (counter > 1000)`
166			`next_state = Step_6;`
167			`else`
168			`next_state = Step_5;`
169			`end`
170
171			`// State 8`
172			`Step_6:`
173			`begin`
174			`if (counter > 1000)`
175			`next_state = Step_7;`
176			`else`
177			`next_state = Step_6;`
178			`end`
179
180			`// State 9`
181			`Step_7:`
182			`begin`
183			`if (counter <= 1000)`
184			`begin`
185			`next_state = Step_7;`
186			`end`
187
188			`else if ( (counter > 1000) && (buttons != mem_data) && (buttons != 0) && (! int_ack) )`
189			`begin`
190			`next_state = Write_Data;`
191			`end`
192
193			`else if ( (counter > 1000) && (buttons == mem_data) && (buttons != 0) && (! int_ack) )`
194			`begin`
195			`next_state = Int_Req;`
196			`end`
197
198			`else`
199			`begin`
200			`next_state = Wait_Frame;`
201			`end`
202			`end`
203
204			`// State 10`
205			`Write_Data:`
206			`begin`
207			`if (mem_grant)`
208			`next_state = Wait_Mem;`
209			`else`
210			`next_state = Write_Data;`
211			`end`
212
213			`// State 11`
214			`Wait_Mem:`
215			`begin`
216			`next_state = Int_Req;`
217			`end`
218
219			`// State 12`
220			`Int_Req:`
221			`begin`
222			`if (int_ack)`
223			`next_state = Wait_Frame;`
224			`else`
225			`next_state = Int_Req;`
226			`end`
227
228			`default:`
229			`begin`
230			`next_state = Reset;`
231			`end`
232
233			`endcase`
234
235			`end`
236
237
238			`// Output Decoder`
239			`always @ (*)`
240			`begin`
241
242			`// Default Assignments`
243			`select = 1;`
244			`mem_addr = 16'd1025;`
245			`mem_wren = 0;`
246			`mem_req = 0;`
247			`int_req = 0;`
248
249
250			`case (current_state)`
251
252			`// State 0`
253			`Reset:`
254			`begin`
255
256			`end`
257
258			`// State 1`
259			`Wait_Frame:`
260			`begin`
261
262			`end`
263
264			`// State 2`
265			`Step_0:`
266			`begin`
267
268			`end`
269
270			`// State 3`
271			`Step_1:`
272			`begin`
273			`select = 0;`
274			`end`
275
276			`// State 4`
277			`Step_2:`
278			`begin`
279
280			`end`
281
282			`// State 5`
283			`Step_3:`
284			`begin`
285			`select = 0;`
286			`end`
287
288			`// State 6`
289			`Step_4:`
290			`begin`
291
292			`end`
293
294			`// State 7`
295			`Step_5:`
296			`begin`
297			`select = 0;`
298			`end`
299
300			`// State 8`
301			`Step_6:`
302			`begin`
303
304			`end`
305
306			`// State 9`
307			`Step_7:`
308			`begin`
309			`select = 0;`
310			`end`
311
312			`// State 10`
313			`Write_Data:`
314			`begin`
315			`mem_wren = 1;`
316			`mem_req = 1;`
317			`end`
318
319			`// State 11`
320			`Wait_Mem:`
321			`begin`
322			`mem_wren = 1;`
323			`mem_req = 1;`
324			`end`
325
326			`// State 12`
327			`Int_Req:`
328			`begin`
329			`int_req = 1;`
330			`end`
331
332			`default:`
333			`begin`
334
335			`end`
336
337			`endcase`
338			`end`
339
340
341			`// State Register and Reset Logic`
342			`always @ (posedge clock)`
343			`begin`
344
345			`if (reset)`
346			`begin`
347			`current_state <= Reset;`
348
349			`// State: Reset`
350			`mem_data <= 16'd0;`
351			`buttons <= 16'd0;`
352			`counter <= 10'd0;`
353
354			`end`
355
356			`else`
357			`begin`
358			`current_state <= next_state;`
359
360			`// State: Step_0`
361			`if (next_state == Step_0)`
362			`begin`
363			`if (counter > 1000)`
364			`counter <= 0;`
365			`else`
366			`counter <= counter + 1'b1;`
367			`end`
368
369			`// State: Step_1`
370			`if (next_state == Step_1)`
371			`begin`
372			`buttons[6] <= ~ b_a;`
373			`buttons[7] <= ~ c_start;`
374
375			`if (counter > 1000)`
376			`counter <= 0;`
377			`else`
378			`counter <= counter + 1'b1;`
379			`end`
380
381			`// State: Step_2`
382			`if (next_state == Step_2)`
383			`begin`
384			`buttons[0] <= ~ up_z;`
385			`buttons[1] <= ~ down_y;`
386			`buttons[2] <= ~ left_x;`
387			`buttons[3] <= ~ right_mode;`
388			`buttons[4] <= ~ b_a;`
389			`buttons[5] <= ~ c_start;`
390
391			`if (counter > 1000)`
392			`counter <= 0;`
393			`else`
394			`counter <= counter + 1'b1;`
395			`end`
396
397			`// State: Step_3`
398			`if (next_state == Step_3)`
399			`begin`
400			`if (counter > 1000)`
401			`counter <= 0;`
402			`else`
403			`counter <= counter + 1'b1;`
404			`end`
405
406			`// State: Step_4`
407			`if (next_state == Step_4)`
408			`begin`
409			`if (counter > 1000)`
410			`counter <= 0;`
411			`else`
412			`counter <= counter + 1'b1;`
413			`end`
414
415			`// State: Step_5`
416			`if (next_state == Step_5)`
417			`begin`
418			`if (counter > 1000)`
419			`counter <= 0;`
420			`else`
421			`counter <= counter + 1'b1;`
422			`end`
423
424			`// State: Step_6`
425			`if (next_state == Step_6)`
426			`begin`
427			`buttons[8] <= ~ up_z;`
428			`buttons[9] <= ~ down_y;`
429			`buttons[10] <= ~ left_x;`
430			`buttons[11] <= ~ right_mode;`
431
432			`if (counter > 1000)`
433			`counter <= 0;`
434			`else`
435			`counter <= counter + 1'b1;`
436			`end`
437
438			`// State: Step_7`
439			`if (next_state == Step_7)`
440			`begin`
441			`if (counter > 1000)`
442			`counter <= 0;`
443			`else`
444			`counter <= counter + 1'b1;`
445			`end`
446
447			`// State: Write_Data`
448			`if (next_state == Write_Data)`
449			`begin`
450			`mem_data <= buttons;`
451			`end`
452
453
454			`end`
455
456			`end`
457
458			`/########################################################################/`
459			`/########################################################################/`
460
461
462			`endmodule`