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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Genesis_6button_Interface.v.bak] - Blame information for rev 2

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module Genesis_6button_Interface(
 
clock,
reset,
mem_grant,
up_z,
down_y,
left_x,
right_mode,
b_a,
c_start,
v_sync,
int_ack,
 
mem_addr,
mem_data,
mem_wren,
mem_req,
counter,
buttons,
current_state,
next_state,
select,
v_sync_flag,
int_req
 
);
 
 
input   up_z;
input   down_y;
input           left_x;
input           right_mode;
input           b_a;
input           c_start;
input           mem_grant;
input           int_ack;
input   v_sync;
input   clock;
input   reset;
 
 
output reg      [19:0]  counter;
output reg      [15:0]  buttons;
 
output reg      [15:0]  mem_addr;
output reg      [15:0]  mem_data;
output reg      mem_wren;
output reg      mem_req;
output reg      int_req;
output reg      select;
output          v_sync_flag;
 
 
/*########################################################################*/
/*#################  Video vertical sync edge-detection  #################*/
/*########################################################################*/
 
reg   v_sync_delay;
 
always @ (posedge clock)
begin
        v_sync_delay <= v_sync;
end
 
assign v_sync_flag = ~v_sync & v_sync_delay;
 
/*########################################################################*/
/*########################################################################*/
 
 
/*########################################################################*/
/*########################  FINITE STATE MACHINE  ########################*/
/*########################  SEGA GENESIS          ########################*/
/*########################  6-BUTTON CONTROLLER   ########################*/
/*########################################################################*/
 
output reg      [3:0]           current_state;
output reg      [3:0]           next_state;
 
// States
parameter       Reset                   = 4'b0000;      // Reset                        = 0
parameter       Wait_Frame      = 4'b0001;      // Wait_Frame   = 1
parameter       Step_0          = 4'b0010;      // Step_0               = 2
parameter       Step_1          = 4'b0011;      // Step_1               = 3
parameter       Step_2          = 4'b0100;      // Step_2               = 4
parameter       Step_3          = 4'b0101;      // Step_3               = 5
parameter       Step_4          = 4'b0110;      // Step_4               = 6
parameter       Step_5          = 4'b0111;      // Step_5               = 7
parameter       Step_6          = 4'b1000;      // Step_6               = 8
parameter       Step_7          = 4'b1001;      // Step_7               = 9
parameter       Write_Data      = 4'b1010;      // Write_Data   = 10
parameter       Wait_Mem                = 4'b1011;      // Wait_Mem             = 11
parameter       Int_Req         = 4'b1100;      // Int_Req              = 12
 
 
// Next State Decoder
always @ (*)
begin
        case (current_state)
 
                // State 0
                Reset:
                begin
                        next_state = Wait_Frame;
                end
 
                // State 1
                Wait_Frame:
                begin
                        //if (counter > 840000)
                        //      next_state = Step_0;
                        //else
                        //      next_state = Wait_Frame;
 
                        //ATENÇÃO!!!!!!!!
                        if (v_sync_flag)
                                next_state = Step_0;
                        else
                                next_state = Wait_Frame;
                end
 
                // State 2
                Step_0:
                begin
                        if (counter > 1000)
                                next_state = Step_1;
                        else
                                next_state = Step_0;
                end
 
                // State 3
                Step_1:
                begin
                        if (counter > 1000)
                                next_state = Step_2;
                        else
                                next_state = Step_1;
                end
 
                // State 4
                Step_2:
                begin
                        if (counter > 1000)
                                next_state = Step_3;
                        else
                                next_state = Step_2;
                end
 
                // State 5
                Step_3:
                begin
                        if (counter > 1000)
                                next_state = Step_4;
                        else
                                next_state = Step_3;
                end
 
                // State 6
                Step_4:
                begin
                        if (counter > 1000)
                                next_state = Step_5;
                        else
                                next_state = Step_4;
                end
 
                // State 7
                Step_5:
                begin
                        if (counter > 1000)
                                next_state = Step_6;
                        else
                                next_state = Step_5;
                end
 
                // State 8
                Step_6:
                begin
                        if (counter > 1000)
                                next_state = Step_7;
                        else
                                next_state = Step_6;
                end
 
                // State 9
                Step_7:
                begin
                        if (counter <= 1000)
                        begin
                                next_state = Step_7;
                        end
 
                        else if ( (counter > 1000) && (buttons != mem_data) && (buttons != 0) && (! int_ack) )
                        begin
                                next_state = Write_Data;
                        end
 
                        else if ( (counter > 1000) && (buttons == mem_data) && (buttons != 0) && (! int_ack) )
                        begin
                                next_state = Int_Req;
                        end
 
                        else
                        begin
                                next_state = Wait_Frame;
                        end
                end
 
                // State 10
                Write_Data:
                begin
                        if (mem_grant)
                                next_state = Wait_Mem;
                        else
                                next_state = Write_Data;
                end
 
                // State 11
                Wait_Mem:
                begin
                        next_state = Int_Req;
                end
 
                // State 12
                Int_Req:
                begin
                        if (int_ack)
                                next_state = Wait_Frame;
                        else
                                next_state = Int_Req;
                end
 
                default:
                begin
                        next_state = Reset;
                end
 
        endcase
 
end
 
 
// Output Decoder
always @ (*)
begin
 
        // Default Assignments
        select = 1;
        mem_addr = 16'd1025;
        mem_wren = 0;
        mem_req = 0;
        int_req = 0;
 
 
        case (current_state)
 
                // State 0
                Reset:
                begin
 
                end
 
                // State 1
                Wait_Frame:
                begin
 
                end
 
                // State 2
                Step_0:
                begin
 
                end
 
                // State 3
                Step_1:
                begin
                        select = 0;
                end
 
                // State 4
                Step_2:
                begin
 
                end
 
                // State 5
                Step_3:
                begin
                        select = 0;
                end
 
                // State 6
                Step_4:
                begin
 
                end
 
                // State 7
                Step_5:
                begin
                        select = 0;
                end
 
                // State 8
                Step_6:
                begin
 
                end
 
                // State 9
                Step_7:
                begin
                        select = 0;
                end
 
                // State 10
                Write_Data:
                begin
                        mem_wren = 1;
                        mem_req = 1;
                end
 
                // State 11
                Wait_Mem:
                begin
                        mem_wren = 1;
                        mem_req = 1;
                end
 
                // State 12
                Int_Req:
                begin
                        int_req = 1;
                end
 
                default:
                begin
 
                end
 
        endcase
end
 
 
// State Register and Reset Logic
always @ (posedge clock)
begin
 
        if (reset)
        begin
                current_state   <= Reset;
 
                // State: Reset
                mem_data <= 16'd0;
                buttons <= 16'd0;
                counter <= 20'd0;
 
        end
 
        else
        begin
                current_state   <=        next_state;
 
                // State: Wait_Frame
                //if (next_state == Wait_Frame)
                //      counter <= counter + 1'b1;
 
                // State: Step_0
                if (next_state == Step_0)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_1
                if (next_state == Step_1)
                begin
                        buttons[6] <= ~ b_a;
                        buttons[7] <= ~ c_start;
 
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_2
                if (next_state == Step_2)
                begin
                        buttons[0] <= ~ up_z;
                        buttons[1] <= ~ down_y;
                        buttons[2] <= ~ left_x;
                        buttons[3] <= ~ right_mode;
                        buttons[4] <= ~ b_a;
                        buttons[5] <= ~ c_start;
 
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_3
                if (next_state == Step_3)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_4
                if (next_state == Step_4)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_5
                if (next_state == Step_5)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_6
                if (next_state == Step_6)
                begin
                        buttons[8] <= ~ up_z;
                        buttons[9] <= ~ down_y;
                        buttons[10] <= ~ left_x;
                        buttons[11] <= ~ right_mode;
 
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Step_7
                if (next_state == Step_7)
                begin
                        if (counter > 1000)
                                counter <= 0;
                        else
                                counter <= counter + 1'b1;
                end
 
                // State: Write_Data
                if (next_state == Write_Data)
                begin
                        mem_data <= buttons;
                end
 
 
        end
 
end
 
/*########################################################################*/
/*########################################################################*/
 
 
endmodule

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Subversion Repositories 2d_game_console

[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Genesis_6button_Interface.v.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	lucas.vbal	`module Genesis_6button_Interface(`
2
3			`clock,`
4			`reset,`
5			`mem_grant,`
6			`up_z,`
7			`down_y,`
8			`left_x,`
9			`right_mode,`
10			`b_a,`
11			`c_start,`
12			`v_sync,`
13			`int_ack,`
14
15			`mem_addr,`
16			`mem_data,`
17			`mem_wren,`
18			`mem_req,`
19			`counter,`
20			`buttons,`
21			`current_state,`
22			`next_state,`
23			`select,`
24			`v_sync_flag,`
25			`int_req`
26
27			`);`
28
29
30			`input up_z;`
31			`input down_y;`
32			`input left_x;`
33			`input right_mode;`
34			`input b_a;`
35			`input c_start;`
36			`input mem_grant;`
37			`input int_ack;`
38			`input v_sync;`
39			`input clock;`
40			`input reset;`
41
42
43			`output reg [19:0] counter;`
44			`output reg [15:0] buttons;`
45
46			`output reg [15:0] mem_addr;`
47			`output reg [15:0] mem_data;`
48			`output reg mem_wren;`
49			`output reg mem_req;`
50			`output reg int_req;`
51			`output reg select;`
52			`output v_sync_flag;`
53
54
55			`/########################################################################/`
56			`/################# Video vertical sync edge-detection #################/`
57			`/########################################################################/`
58
59			`reg v_sync_delay;`
60
61			`always @ (posedge clock)`
62			`begin`
63			`v_sync_delay <= v_sync;`
64			`end`
65
66			`assign v_sync_flag = ~v_sync & v_sync_delay;`
67
68			`/########################################################################/`
69			`/########################################################################/`
70
71
72			`/########################################################################/`
73			`/######################## FINITE STATE MACHINE ########################/`
74			`/######################## SEGA GENESIS ########################/`
75			`/######################## 6-BUTTON CONTROLLER ########################/`
76			`/########################################################################/`
77
78			`output reg [3:0] current_state;`
79			`output reg [3:0] next_state;`
80
81			`// States`
82			`parameter Reset = 4'b0000; // Reset = 0`
83			`parameter Wait_Frame = 4'b0001; // Wait_Frame = 1`
84			`parameter Step_0 = 4'b0010; // Step_0 = 2`
85			`parameter Step_1 = 4'b0011; // Step_1 = 3`
86			`parameter Step_2 = 4'b0100; // Step_2 = 4`
87			`parameter Step_3 = 4'b0101; // Step_3 = 5`
88			`parameter Step_4 = 4'b0110; // Step_4 = 6`
89			`parameter Step_5 = 4'b0111; // Step_5 = 7`
90			`parameter Step_6 = 4'b1000; // Step_6 = 8`
91			`parameter Step_7 = 4'b1001; // Step_7 = 9`
92			`parameter Write_Data = 4'b1010; // Write_Data = 10`
93			`parameter Wait_Mem = 4'b1011; // Wait_Mem = 11`
94			`parameter Int_Req = 4'b1100; // Int_Req = 12`
95
96
97			`// Next State Decoder`
98			`always @ (*)`
99			`begin`
100			`case (current_state)`
101
102			`// State 0`
103			`Reset:`
104			`begin`
105			`next_state = Wait_Frame;`
106			`end`
107
108			`// State 1`
109			`Wait_Frame:`
110			`begin`
111			`//if (counter > 840000)`
112			`// next_state = Step_0;`
113			`//else`
114			`// next_state = Wait_Frame;`
115
116			`//ATENÇÃO!!!!!!!!`
117			`if (v_sync_flag)`
118			`next_state = Step_0;`
119			`else`
120			`next_state = Wait_Frame;`
121			`end`
122
123			`// State 2`
124			`Step_0:`
125			`begin`
126			`if (counter > 1000)`
127			`next_state = Step_1;`
128			`else`
129			`next_state = Step_0;`
130			`end`
131
132			`// State 3`
133			`Step_1:`
134			`begin`
135			`if (counter > 1000)`
136			`next_state = Step_2;`
137			`else`
138			`next_state = Step_1;`
139			`end`
140
141			`// State 4`
142			`Step_2:`
143			`begin`
144			`if (counter > 1000)`
145			`next_state = Step_3;`
146			`else`
147			`next_state = Step_2;`
148			`end`
149
150			`// State 5`
151			`Step_3:`
152			`begin`
153			`if (counter > 1000)`
154			`next_state = Step_4;`
155			`else`
156			`next_state = Step_3;`
157			`end`
158
159			`// State 6`
160			`Step_4:`
161			`begin`
162			`if (counter > 1000)`
163			`next_state = Step_5;`
164			`else`
165			`next_state = Step_4;`
166			`end`
167
168			`// State 7`
169			`Step_5:`
170			`begin`
171			`if (counter > 1000)`
172			`next_state = Step_6;`
173			`else`
174			`next_state = Step_5;`
175			`end`
176
177			`// State 8`
178			`Step_6:`
179			`begin`
180			`if (counter > 1000)`
181			`next_state = Step_7;`
182			`else`
183			`next_state = Step_6;`
184			`end`
185
186			`// State 9`
187			`Step_7:`
188			`begin`
189			`if (counter <= 1000)`
190			`begin`
191			`next_state = Step_7;`
192			`end`
193
194			`else if ( (counter > 1000) && (buttons != mem_data) && (buttons != 0) && (! int_ack) )`
195			`begin`
196			`next_state = Write_Data;`
197			`end`
198
199			`else if ( (counter > 1000) && (buttons == mem_data) && (buttons != 0) && (! int_ack) )`
200			`begin`
201			`next_state = Int_Req;`
202			`end`
203
204			`else`
205			`begin`
206			`next_state = Wait_Frame;`
207			`end`
208			`end`
209
210			`// State 10`
211			`Write_Data:`
212			`begin`
213			`if (mem_grant)`
214			`next_state = Wait_Mem;`
215			`else`
216			`next_state = Write_Data;`
217			`end`
218
219			`// State 11`
220			`Wait_Mem:`
221			`begin`
222			`next_state = Int_Req;`
223			`end`
224
225			`// State 12`
226			`Int_Req:`
227			`begin`
228			`if (int_ack)`
229			`next_state = Wait_Frame;`
230			`else`
231			`next_state = Int_Req;`
232			`end`
233
234			`default:`
235			`begin`
236			`next_state = Reset;`
237			`end`
238
239			`endcase`
240
241			`end`
242
243
244			`// Output Decoder`
245			`always @ (*)`
246			`begin`
247
248			`// Default Assignments`
249			`select = 1;`
250			`mem_addr = 16'd1025;`
251			`mem_wren = 0;`
252			`mem_req = 0;`
253			`int_req = 0;`
254
255
256			`case (current_state)`
257
258			`// State 0`
259			`Reset:`
260			`begin`
261
262			`end`
263
264			`// State 1`
265			`Wait_Frame:`
266			`begin`
267
268			`end`
269
270			`// State 2`
271			`Step_0:`
272			`begin`
273
274			`end`
275
276			`// State 3`
277			`Step_1:`
278			`begin`
279			`select = 0;`
280			`end`
281
282			`// State 4`
283			`Step_2:`
284			`begin`
285
286			`end`
287
288			`// State 5`
289			`Step_3:`
290			`begin`
291			`select = 0;`
292			`end`
293
294			`// State 6`
295			`Step_4:`
296			`begin`
297
298			`end`
299
300			`// State 7`
301			`Step_5:`
302			`begin`
303			`select = 0;`
304			`end`
305
306			`// State 8`
307			`Step_6:`
308			`begin`
309
310			`end`
311
312			`// State 9`
313			`Step_7:`
314			`begin`
315			`select = 0;`
316			`end`
317
318			`// State 10`
319			`Write_Data:`
320			`begin`
321			`mem_wren = 1;`
322			`mem_req = 1;`
323			`end`
324
325			`// State 11`
326			`Wait_Mem:`
327			`begin`
328			`mem_wren = 1;`
329			`mem_req = 1;`
330			`end`
331
332			`// State 12`
333			`Int_Req:`
334			`begin`
335			`int_req = 1;`
336			`end`
337
338			`default:`
339			`begin`
340
341			`end`
342
343			`endcase`
344			`end`
345
346
347			`// State Register and Reset Logic`
348			`always @ (posedge clock)`
349			`begin`
350
351			`if (reset)`
352			`begin`
353			`current_state <= Reset;`
354
355			`// State: Reset`
356			`mem_data <= 16'd0;`
357			`buttons <= 16'd0;`
358			`counter <= 20'd0;`
359
360			`end`
361
362			`else`
363			`begin`
364			`current_state <= next_state;`
365
366			`// State: Wait_Frame`
367			`//if (next_state == Wait_Frame)`
368			`// counter <= counter + 1'b1;`
369
370			`// State: Step_0`
371			`if (next_state == Step_0)`
372			`begin`
373			`if (counter > 1000)`
374			`counter <= 0;`
375			`else`
376			`counter <= counter + 1'b1;`
377			`end`
378
379			`// State: Step_1`
380			`if (next_state == Step_1)`
381			`begin`
382			`buttons[6] <= ~ b_a;`
383			`buttons[7] <= ~ c_start;`
384
385			`if (counter > 1000)`
386			`counter <= 0;`
387			`else`
388			`counter <= counter + 1'b1;`
389			`end`
390
391			`// State: Step_2`
392			`if (next_state == Step_2)`
393			`begin`
394			`buttons[0] <= ~ up_z;`
395			`buttons[1] <= ~ down_y;`
396			`buttons[2] <= ~ left_x;`
397			`buttons[3] <= ~ right_mode;`
398			`buttons[4] <= ~ b_a;`
399			`buttons[5] <= ~ c_start;`
400
401			`if (counter > 1000)`
402			`counter <= 0;`
403			`else`
404			`counter <= counter + 1'b1;`
405			`end`
406
407			`// State: Step_3`
408			`if (next_state == Step_3)`
409			`begin`
410			`if (counter > 1000)`
411			`counter <= 0;`
412			`else`
413			`counter <= counter + 1'b1;`
414			`end`
415
416			`// State: Step_4`
417			`if (next_state == Step_4)`
418			`begin`
419			`if (counter > 1000)`
420			`counter <= 0;`
421			`else`
422			`counter <= counter + 1'b1;`
423			`end`
424
425			`// State: Step_5`
426			`if (next_state == Step_5)`
427			`begin`
428			`if (counter > 1000)`
429			`counter <= 0;`
430			`else`
431			`counter <= counter + 1'b1;`
432			`end`
433
434			`// State: Step_6`
435			`if (next_state == Step_6)`
436			`begin`
437			`buttons[8] <= ~ up_z;`
438			`buttons[9] <= ~ down_y;`
439			`buttons[10] <= ~ left_x;`
440			`buttons[11] <= ~ right_mode;`
441
442			`if (counter > 1000)`
443			`counter <= 0;`
444			`else`
445			`counter <= counter + 1'b1;`
446			`end`
447
448			`// State: Step_7`
449			`if (next_state == Step_7)`
450			`begin`
451			`if (counter > 1000)`
452			`counter <= 0;`
453			`else`
454			`counter <= counter + 1'b1;`
455			`end`
456
457			`// State: Write_Data`
458			`if (next_state == Write_Data)`
459			`begin`
460			`mem_data <= buttons;`
461			`end`
462
463
464			`end`
465
466			`end`
467
468			`/########################################################################/`
469			`/########################################################################/`
470
471
472			`endmodule`