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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Interrupt_Controller.v] - Blame information for rev 2

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module Interrupt_Controller(
 
mem_q,
cpu_ack,
mem_grant,
clock,
reset,
int_req_0,
int_req_1,
int_req_2,
int_req_3,
 
 
mem_addr,
mem_wren,
mem_req,
isr_addr,
cpu_req,
int_mask,
current_state,
next_state,
int_ack_0,
int_ack_1,
int_ack_2,
int_ack_3
 
);
 
 
input           [15:0]   mem_q;
input   mem_grant;
input   cpu_ack;
input           int_req_0;
input           int_req_1;
input           int_req_2;
input           int_req_3;
input   clock;
input   reset;
 
 
output reg      [15:0]   int_mask;
output reg      [15:0]   isr_addr;
output reg      [15:0]   mem_addr;
output reg      mem_wren;
output reg      mem_req;
output reg      cpu_req;
output reg      int_ack_0;
output reg      int_ack_1;
output reg      int_ack_2;
output reg      int_ack_3;
 
 
/*########################################################################*/
/*########################  FINITE STATE MACHINE  ########################*/
/*########################  INTERRUPT CONTROLLER  ########################*/
/*########################################################################*/
 
output reg      [3:0]            current_state;
output reg      [3:0]            next_state;
 
// States
parameter       Idle                    = 4'b0000;      // Idle                 = 0
parameter       Read_Mask       = 4'b0001;      // Read_Mask    = 1
parameter       Wait_Mem_1      = 4'b0010;      // Wait_Mem_1   = 2
parameter       Wait_Mem_2      = 4'b0011;      // Wait_Mem_2   = 3
parameter       Get_Mask                = 4'b0100;      // Get_Mask             = 4
parameter       Int_Req_0       = 4'b0101;      // Int_Req_0    = 5
parameter       Int_Req_1       = 4'b0110;      // Int_Req_1    = 6
parameter       Int_Req_2       = 4'b0111;      // Int_Req_2    = 7
parameter       Int_Req_3       = 4'b1000;      // Int_Req_3    = 8
parameter       Wait_Req_0      = 4'b1001;      // Wait_Req_0   = 9
parameter       Wait_Req_1      = 4'b1010;      // Wait_Req_1   = 10
parameter       Wait_Req_2      = 4'b1011;      // Wait_Req_2   = 11
parameter       Wait_Req_3      = 4'b1100;      // Wait_Req_3   = 12
 
 
// Next State Decoder
always @ (*)
begin
        case (current_state)
 
                // State 0
                Idle:
                begin
                        if ( (int_req_0 || int_req_1 || int_req_2 || int_req_3) && (!cpu_ack) )
                                next_state = Read_Mask;
                        else
                                next_state = Idle;
                end
 
                // State 1
                Read_Mask:
                begin
                        if (mem_grant)
                                next_state = Wait_Mem_1;
                        else
                                next_state = Read_Mask;
                end
 
                // State 2
                Wait_Mem_1:
                begin
                        next_state = Wait_Mem_2;
                end
 
                // State 3
                Wait_Mem_2:
                begin
                        next_state = Get_Mask;
                end
 
                // State 4
                Get_Mask:
                begin
                        if (int_mask[0] && int_req_0)
                                next_state = Int_Req_0;
 
                        else if (int_mask[1] && int_req_1)
                                next_state = Int_Req_1;
 
                        else if (int_mask[2] && int_req_2)
                                next_state = Int_Req_2;
 
                        else if (int_mask[3] && int_req_3)
                                next_state = Int_Req_3;
 
                        else
                                next_state = Idle;
                end
 
                // State 5
                Int_Req_0:
                begin
                        if (cpu_ack)
                                next_state = Wait_Req_0;
                        else
                                next_state = Int_Req_0;
                end
 
                // State 6
                Int_Req_1:
                begin
                        if (cpu_ack)
                                next_state = Wait_Req_1;
                        else
                                next_state = Int_Req_1;
                end
 
                // State 7
                Int_Req_2:
                begin
                        if (cpu_ack)
                                next_state = Wait_Req_2;
                        else
                                next_state = Int_Req_2;
                end
 
                // State 8
                Int_Req_3:
                begin
                        if (cpu_ack)
                                next_state = Wait_Req_3;
                        else
                                next_state = Int_Req_3;
                end
 
                // State 9
                Wait_Req_0:
                begin
                        if (cpu_ack || int_req_0)
                                next_state = Wait_Req_0;
                        else
                                next_state = Idle;
                end
 
                // State 10
                Wait_Req_1:
                begin
                        if (cpu_ack || int_req_1)
                                next_state = Wait_Req_1;
                        else
                                next_state = Idle;
                end
 
                // State 11
                Wait_Req_2:
                begin
                        if (cpu_ack || int_req_2)
                                next_state = Wait_Req_2;
                        else
                                next_state = Idle;
                end
 
                // State 12
                Wait_Req_3:
                begin
                        if (cpu_ack || int_req_3)
                                next_state = Wait_Req_3;
                        else
                                next_state = Idle;
                end
 
                default:
                begin
                        next_state = Idle;
                end
 
        endcase
 
end
 
 
// Output Decoder
always @ (*)
begin
 
        // Default Assignments
        mem_addr = 16'd1024;
        mem_wren = 0;
        mem_req = 0;
        int_ack_0 = 0;
        int_ack_1 = 0;
        int_ack_2 = 0;
        int_ack_3 = 0;
        cpu_req = 0;
        isr_addr = 16'd0;
 
 
        case (current_state)
 
                // State 0
                Idle:
                begin
 
                end
 
                // State 1
                Read_Mask:
                begin
                        mem_req = 1;
                end
 
                // State 2
                Wait_Mem_1:
                begin
                        mem_req = 1;
                end
 
                // State 3
                Wait_Mem_2:
                begin
                        mem_req = 1;
                end
 
                // State 4
                Get_Mask:
                begin
                        mem_req = 1;
                end
 
                // State 5
                Int_Req_0:
                begin
                        cpu_req = 1;
                        isr_addr = 16'd0;
                end
 
                // State 6
                Int_Req_1:
                begin
                        cpu_req = 1;
                        isr_addr = 16'd1;
                end
 
                // State 7
                Int_Req_2:
                begin
                        cpu_req = 1;
                        isr_addr = 16'd2;
                end
 
                // State 8
                Int_Req_3:
                begin
                        cpu_req = 1;
                        isr_addr = 16'd3;
                end
 
                // State 9
                Wait_Req_0:
                begin
                        int_ack_0 = 1;
                end
 
                // State 10
                Wait_Req_1:
                begin
                        int_ack_1 = 1;
                end
 
                // State 11
                Wait_Req_2:
                begin
                        int_ack_2 = 1;
                end
 
                // State 12
                Wait_Req_3:
                begin
                        int_ack_3 = 1;
                end
 
                default:
                begin
 
                end
 
        endcase
end
 
 
// State Register and Reset Logic
always @ (posedge clock)
begin
 
        if (reset)
        begin
                current_state   <= Idle;
        end
 
        else
        begin
                current_state   <=      next_state;
 
                // State: Get_Mask
                if (next_state == Get_Mask)
                        int_mask <= mem_q;
 
        end
 
end
 
/*########################################################################*/
/*########################################################################*/
 
 
endmodule

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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Interrupt_Controller.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	lucas.vbal	`module Interrupt_Controller(`
2
3			`mem_q,`
4			`cpu_ack,`
5			`mem_grant,`
6			`clock,`
7			`reset,`
8			`int_req_0,`
9			`int_req_1,`
10			`int_req_2,`
11			`int_req_3,`
12
13
14			`mem_addr,`
15			`mem_wren,`
16			`mem_req,`
17			`isr_addr,`
18			`cpu_req,`
19			`int_mask,`
20			`current_state,`
21			`next_state,`
22			`int_ack_0,`
23			`int_ack_1,`
24			`int_ack_2,`
25			`int_ack_3`
26
27			`);`
28
29
30			`input [15:0] mem_q;`
31			`input mem_grant;`
32			`input cpu_ack;`
33			`input int_req_0;`
34			`input int_req_1;`
35			`input int_req_2;`
36			`input int_req_3;`
37			`input clock;`
38			`input reset;`
39
40
41			`output reg [15:0] int_mask;`
42			`output reg [15:0] isr_addr;`
43			`output reg [15:0] mem_addr;`
44			`output reg mem_wren;`
45			`output reg mem_req;`
46			`output reg cpu_req;`
47			`output reg int_ack_0;`
48			`output reg int_ack_1;`
49			`output reg int_ack_2;`
50			`output reg int_ack_3;`
51
52
53			`/########################################################################/`
54			`/######################## FINITE STATE MACHINE ########################/`
55			`/######################## INTERRUPT CONTROLLER ########################/`
56			`/########################################################################/`
57
58			`output reg [3:0] current_state;`
59			`output reg [3:0] next_state;`
60
61			`// States`
62			`parameter Idle = 4'b0000; // Idle = 0`
63			`parameter Read_Mask = 4'b0001; // Read_Mask = 1`
64			`parameter Wait_Mem_1 = 4'b0010; // Wait_Mem_1 = 2`
65			`parameter Wait_Mem_2 = 4'b0011; // Wait_Mem_2 = 3`
66			`parameter Get_Mask = 4'b0100; // Get_Mask = 4`
67			`parameter Int_Req_0 = 4'b0101; // Int_Req_0 = 5`
68			`parameter Int_Req_1 = 4'b0110; // Int_Req_1 = 6`
69			`parameter Int_Req_2 = 4'b0111; // Int_Req_2 = 7`
70			`parameter Int_Req_3 = 4'b1000; // Int_Req_3 = 8`
71			`parameter Wait_Req_0 = 4'b1001; // Wait_Req_0 = 9`
72			`parameter Wait_Req_1 = 4'b1010; // Wait_Req_1 = 10`
73			`parameter Wait_Req_2 = 4'b1011; // Wait_Req_2 = 11`
74			`parameter Wait_Req_3 = 4'b1100; // Wait_Req_3 = 12`
75
76
77			`// Next State Decoder`
78			`always @ (*)`
79			`begin`
80			`case (current_state)`
81
82			`// State 0`
83			`Idle:`
84			`begin`
85			`if ( (int_req_0 \|\| int_req_1 \|\| int_req_2 \|\| int_req_3) && (!cpu_ack) )`
86			`next_state = Read_Mask;`
87			`else`
88			`next_state = Idle;`
89			`end`
90
91			`// State 1`
92			`Read_Mask:`
93			`begin`
94			`if (mem_grant)`
95			`next_state = Wait_Mem_1;`
96			`else`
97			`next_state = Read_Mask;`
98			`end`
99
100			`// State 2`
101			`Wait_Mem_1:`
102			`begin`
103			`next_state = Wait_Mem_2;`
104			`end`
105
106			`// State 3`
107			`Wait_Mem_2:`
108			`begin`
109			`next_state = Get_Mask;`
110			`end`
111
112			`// State 4`
113			`Get_Mask:`
114			`begin`
115			`if (int_mask[0] && int_req_0)`
116			`next_state = Int_Req_0;`
117
118			`else if (int_mask[1] && int_req_1)`
119			`next_state = Int_Req_1;`
120
121			`else if (int_mask[2] && int_req_2)`
122			`next_state = Int_Req_2;`
123
124			`else if (int_mask[3] && int_req_3)`
125			`next_state = Int_Req_3;`
126
127			`else`
128			`next_state = Idle;`
129			`end`
130
131			`// State 5`
132			`Int_Req_0:`
133			`begin`
134			`if (cpu_ack)`
135			`next_state = Wait_Req_0;`
136			`else`
137			`next_state = Int_Req_0;`
138			`end`
139
140			`// State 6`
141			`Int_Req_1:`
142			`begin`
143			`if (cpu_ack)`
144			`next_state = Wait_Req_1;`
145			`else`
146			`next_state = Int_Req_1;`
147			`end`
148
149			`// State 7`
150			`Int_Req_2:`
151			`begin`
152			`if (cpu_ack)`
153			`next_state = Wait_Req_2;`
154			`else`
155			`next_state = Int_Req_2;`
156			`end`
157
158			`// State 8`
159			`Int_Req_3:`
160			`begin`
161			`if (cpu_ack)`
162			`next_state = Wait_Req_3;`
163			`else`
164			`next_state = Int_Req_3;`
165			`end`
166
167			`// State 9`
168			`Wait_Req_0:`
169			`begin`
170			`if (cpu_ack \|\| int_req_0)`
171			`next_state = Wait_Req_0;`
172			`else`
173			`next_state = Idle;`
174			`end`
175
176			`// State 10`
177			`Wait_Req_1:`
178			`begin`
179			`if (cpu_ack \|\| int_req_1)`
180			`next_state = Wait_Req_1;`
181			`else`
182			`next_state = Idle;`
183			`end`
184
185			`// State 11`
186			`Wait_Req_2:`
187			`begin`
188			`if (cpu_ack \|\| int_req_2)`
189			`next_state = Wait_Req_2;`
190			`else`
191			`next_state = Idle;`
192			`end`
193
194			`// State 12`
195			`Wait_Req_3:`
196			`begin`
197			`if (cpu_ack \|\| int_req_3)`
198			`next_state = Wait_Req_3;`
199			`else`
200			`next_state = Idle;`
201			`end`
202
203			`default:`
204			`begin`
205			`next_state = Idle;`
206			`end`
207
208			`endcase`
209
210			`end`
211
212
213			`// Output Decoder`
214			`always @ (*)`
215			`begin`
216
217			`// Default Assignments`
218			`mem_addr = 16'd1024;`
219			`mem_wren = 0;`
220			`mem_req = 0;`
221			`int_ack_0 = 0;`
222			`int_ack_1 = 0;`
223			`int_ack_2 = 0;`
224			`int_ack_3 = 0;`
225			`cpu_req = 0;`
226			`isr_addr = 16'd0;`
227
228
229			`case (current_state)`
230
231			`// State 0`
232			`Idle:`
233			`begin`
234
235			`end`
236
237			`// State 1`
238			`Read_Mask:`
239			`begin`
240			`mem_req = 1;`
241			`end`
242
243			`// State 2`
244			`Wait_Mem_1:`
245			`begin`
246			`mem_req = 1;`
247			`end`
248
249			`// State 3`
250			`Wait_Mem_2:`
251			`begin`
252			`mem_req = 1;`
253			`end`
254
255			`// State 4`
256			`Get_Mask:`
257			`begin`
258			`mem_req = 1;`
259			`end`
260
261			`// State 5`
262			`Int_Req_0:`
263			`begin`
264			`cpu_req = 1;`
265			`isr_addr = 16'd0;`
266			`end`
267
268			`// State 6`
269			`Int_Req_1:`
270			`begin`
271			`cpu_req = 1;`
272			`isr_addr = 16'd1;`
273			`end`
274
275			`// State 7`
276			`Int_Req_2:`
277			`begin`
278			`cpu_req = 1;`
279			`isr_addr = 16'd2;`
280			`end`
281
282			`// State 8`
283			`Int_Req_3:`
284			`begin`
285			`cpu_req = 1;`
286			`isr_addr = 16'd3;`
287			`end`
288
289			`// State 9`
290			`Wait_Req_0:`
291			`begin`
292			`int_ack_0 = 1;`
293			`end`
294
295			`// State 10`
296			`Wait_Req_1:`
297			`begin`
298			`int_ack_1 = 1;`
299			`end`
300
301			`// State 11`
302			`Wait_Req_2:`
303			`begin`
304			`int_ack_2 = 1;`
305			`end`
306
307			`// State 12`
308			`Wait_Req_3:`
309			`begin`
310			`int_ack_3 = 1;`
311			`end`
312
313			`default:`
314			`begin`
315
316			`end`
317
318			`endcase`
319			`end`
320
321
322			`// State Register and Reset Logic`
323			`always @ (posedge clock)`
324			`begin`
325
326			`if (reset)`
327			`begin`
328			`current_state <= Idle;`
329			`end`
330
331			`else`
332			`begin`
333			`current_state <= next_state;`
334
335			`// State: Get_Mask`
336			`if (next_state == Get_Mask)`
337			`int_mask <= mem_q;`
338
339			`end`
340
341			`end`
342
343			`/########################################################################/`
344			`/########################################################################/`
345
346
347			`endmodule`