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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Interrupt_Controller.v] - Blame information for rev 2

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1 2 lucas.vbal
module Interrupt_Controller(
2
 
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mem_q,
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cpu_ack,
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mem_grant,
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clock,
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reset,
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int_req_0,
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int_req_1,
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int_req_2,
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int_req_3,
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mem_addr,
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mem_wren,
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mem_req,
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isr_addr,
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cpu_req,
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int_mask,
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current_state,
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next_state,
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int_ack_0,
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int_ack_1,
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int_ack_2,
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int_ack_3
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);
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input           [15:0]   mem_q;
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input   mem_grant;
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input   cpu_ack;
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input           int_req_0;
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input           int_req_1;
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input           int_req_2;
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input           int_req_3;
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input   clock;
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input   reset;
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output reg      [15:0]   int_mask;
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output reg      [15:0]   isr_addr;
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output reg      [15:0]   mem_addr;
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output reg      mem_wren;
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output reg      mem_req;
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output reg      cpu_req;
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output reg      int_ack_0;
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output reg      int_ack_1;
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output reg      int_ack_2;
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output reg      int_ack_3;
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/*########################################################################*/
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/*########################  FINITE STATE MACHINE  ########################*/
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/*########################  INTERRUPT CONTROLLER  ########################*/
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/*########################################################################*/
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output reg      [3:0]            current_state;
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output reg      [3:0]            next_state;
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// States
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parameter       Idle                    = 4'b0000;      // Idle                 = 0
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parameter       Read_Mask       = 4'b0001;      // Read_Mask    = 1
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parameter       Wait_Mem_1      = 4'b0010;      // Wait_Mem_1   = 2
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parameter       Wait_Mem_2      = 4'b0011;      // Wait_Mem_2   = 3
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parameter       Get_Mask                = 4'b0100;      // Get_Mask             = 4
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parameter       Int_Req_0       = 4'b0101;      // Int_Req_0    = 5
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parameter       Int_Req_1       = 4'b0110;      // Int_Req_1    = 6
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parameter       Int_Req_2       = 4'b0111;      // Int_Req_2    = 7
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parameter       Int_Req_3       = 4'b1000;      // Int_Req_3    = 8
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parameter       Wait_Req_0      = 4'b1001;      // Wait_Req_0   = 9
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parameter       Wait_Req_1      = 4'b1010;      // Wait_Req_1   = 10
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parameter       Wait_Req_2      = 4'b1011;      // Wait_Req_2   = 11
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parameter       Wait_Req_3      = 4'b1100;      // Wait_Req_3   = 12
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// Next State Decoder
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always @ (*)
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begin
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        case (current_state)
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                // State 0
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                Idle:
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                begin
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                        if ( (int_req_0 || int_req_1 || int_req_2 || int_req_3) && (!cpu_ack) )
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                                next_state = Read_Mask;
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                        else
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                                next_state = Idle;
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                end
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                // State 1
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                Read_Mask:
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                begin
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                        if (mem_grant)
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                                next_state = Wait_Mem_1;
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                        else
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                                next_state = Read_Mask;
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                end
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                // State 2
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                Wait_Mem_1:
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                begin
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                        next_state = Wait_Mem_2;
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                end
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                // State 3
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                Wait_Mem_2:
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                begin
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                        next_state = Get_Mask;
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                end
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                // State 4
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                Get_Mask:
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                begin
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                        if (int_mask[0] && int_req_0)
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                                next_state = Int_Req_0;
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                        else if (int_mask[1] && int_req_1)
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                                next_state = Int_Req_1;
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                        else if (int_mask[2] && int_req_2)
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                                next_state = Int_Req_2;
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                        else if (int_mask[3] && int_req_3)
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                                next_state = Int_Req_3;
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                        else
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                                next_state = Idle;
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                end
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                // State 5
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                Int_Req_0:
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                begin
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                        if (cpu_ack)
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                                next_state = Wait_Req_0;
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                        else
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                                next_state = Int_Req_0;
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                end
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                // State 6
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                Int_Req_1:
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                begin
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                        if (cpu_ack)
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                                next_state = Wait_Req_1;
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                        else
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                                next_state = Int_Req_1;
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                end
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                // State 7
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                Int_Req_2:
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                begin
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                        if (cpu_ack)
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                                next_state = Wait_Req_2;
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                        else
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                                next_state = Int_Req_2;
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                end
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                // State 8
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                Int_Req_3:
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                begin
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                        if (cpu_ack)
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                                next_state = Wait_Req_3;
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                        else
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                                next_state = Int_Req_3;
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                end
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                // State 9
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                Wait_Req_0:
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                begin
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                        if (cpu_ack || int_req_0)
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                                next_state = Wait_Req_0;
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                        else
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                                next_state = Idle;
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                end
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                // State 10
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                Wait_Req_1:
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                begin
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                        if (cpu_ack || int_req_1)
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                                next_state = Wait_Req_1;
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                        else
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                                next_state = Idle;
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                end
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                // State 11
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                Wait_Req_2:
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                begin
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                        if (cpu_ack || int_req_2)
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                                next_state = Wait_Req_2;
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                        else
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                                next_state = Idle;
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                end
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                // State 12
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                Wait_Req_3:
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                begin
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                        if (cpu_ack || int_req_3)
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                                next_state = Wait_Req_3;
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                        else
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                                next_state = Idle;
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                end
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                default:
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                begin
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                        next_state = Idle;
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                end
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        endcase
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end
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// Output Decoder
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always @ (*)
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begin
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        // Default Assignments
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        mem_addr = 16'd1024;
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        mem_wren = 0;
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        mem_req = 0;
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        int_ack_0 = 0;
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        int_ack_1 = 0;
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        int_ack_2 = 0;
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        int_ack_3 = 0;
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        cpu_req = 0;
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        isr_addr = 16'd0;
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        case (current_state)
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                // State 0
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                Idle:
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                begin
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                end
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                // State 1
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                Read_Mask:
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                begin
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                        mem_req = 1;
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                end
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                // State 2
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                Wait_Mem_1:
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                begin
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                        mem_req = 1;
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                end
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                // State 3
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                Wait_Mem_2:
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                begin
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                        mem_req = 1;
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                end
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                // State 4
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                Get_Mask:
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                begin
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                        mem_req = 1;
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                end
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                // State 5
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                Int_Req_0:
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                begin
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                        cpu_req = 1;
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                        isr_addr = 16'd0;
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                end
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                // State 6
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                Int_Req_1:
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                begin
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                        cpu_req = 1;
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                        isr_addr = 16'd1;
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                end
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                // State 7
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                Int_Req_2:
277
                begin
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                        cpu_req = 1;
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                        isr_addr = 16'd2;
280
                end
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                // State 8
283
                Int_Req_3:
284
                begin
285
                        cpu_req = 1;
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                        isr_addr = 16'd3;
287
                end
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                // State 9
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                Wait_Req_0:
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                begin
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                        int_ack_0 = 1;
293
                end
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                // State 10
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                Wait_Req_1:
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                begin
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                        int_ack_1 = 1;
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                end
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301
                // State 11
302
                Wait_Req_2:
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                begin
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                        int_ack_2 = 1;
305
                end
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                // State 12
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                Wait_Req_3:
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                begin
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                        int_ack_3 = 1;
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                end
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                default:
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                begin
315
 
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                end
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        endcase
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end
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// State Register and Reset Logic
323
always @ (posedge clock)
324
begin
325
 
326
        if (reset)
327
        begin
328
                current_state   <= Idle;
329
        end
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        else
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        begin
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                current_state   <=      next_state;
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335
                // State: Get_Mask
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                if (next_state == Get_Mask)
337
                        int_mask <= mem_q;
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339
        end
340
 
341
end
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/*########################################################################*/
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/*########################################################################*/
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endmodule

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