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Subversion Repositories 2d_game_console

[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Processor_SDC.sdc] - Blame information for rev 2

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Line No. Rev Author Line
1 2 lucas.vbal
 
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# Constrain clock port "clock" with a 20-ns requirement (50 MHz)
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create_clock -period 20 [get_ports clock]
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# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
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# This command can be safely left in the SDC even if no PLLs exist in the design
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derive_pll_clocks
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# Clock Uncertainty and Jitter of a clock
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derive_clock_uncertainty
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# Constrain the input I/O path
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set_input_delay -clock clock -max 3 [all_inputs]
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set_input_delay -clock clock -min 2 [all_inputs]
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# Constrain the output I/O path
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set_output_delay -clock clock -max 3 [all_outputs]
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set_output_delay -clock clock -min 2 [all_outputs]

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