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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [VGA_Interface.v.bak] - Blame information for rev 2

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module VGA_Interface(
 
        clk,
        rst,
        R_in,
        G_in,
        B_in,
 
        oAddress,
        R,G,B,
        BLANK,
        VGA_SYNC,
        VGA_CLK,
        HS,VS,
        v_pos,
        h_pos
);
 
        input [7:0] R_in, G_in, B_in;
        input clk, rst;
 
        output reg [7:0] R, G, B;
        output reg HS, VS;
        output reg BLANK;
        output VGA_SYNC, VGA_CLK;
 
        output reg [9:0] h_pos, v_pos;
        output reg [19:0]       oAddress;
 
        parameter H_FRONT = 16; //16
        parameter H_SYNC = 96;  //96
        parameter H_BACK = 48;  //48
        parameter H_DISPLAY = 640;
        parameter H_BLANK = H_SYNC+H_BACK;
        parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_DISPLAY;
 
        parameter V_FRONT = 12; //12
        parameter V_SYNC = 2;   //2
        parameter V_BACK = 31;  //31
        parameter V_DISPLAY     = 480;
        parameter V_BLANK = V_SYNC+V_BACK;
        parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_DISPLAY;
 
        reg b_flag;
 
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        h_pos <= 10'b0000000000;
                        v_pos <= 10'b0000000000;
                end
 
                else
                begin
                        if (h_pos
                        begin
                                h_pos <= h_pos + 1'b1;
                        end
 
                        else
                        begin
                                h_pos <= 1'b0;
 
                                if (v_pos
                                begin
                                        v_pos <= v_pos + 1'b1;
                                end
 
                                else
                                begin
                                        v_pos <= 1'b0;
                                end
                        end
                end
        end
 
        // Sincronismo Horizontal
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        HS <= 1'b1;
                end
                else
                begin
                        if ( (h_pos > H_DISPLAY+H_FRONT-1) && (h_pos < H_TOTAL-H_BACK-1) )
                        begin
                                HS <= 1'b0;
                        end
                        else
                        begin
                                HS <= 1'b1;
                        end
                end
        end
 
        // Sincronismo Vertical
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        VS <= 1'b1;
                end
                else
                begin
                        if ( (v_pos > V_DISPLAY+V_FRONT-1) && (v_pos < V_TOTAL-V_BACK-1) )
                        begin
                                VS <= 1'b0;
                        end
                        else
                        begin
                                VS <= 1'b1;
                        end
                end
        end
 
        // Blank
        always @(posedge clk)
        begin
                if (rst == 1'b1)
                begin
                        BLANK <= 1'b1;
                end
                else
                begin
                        if (h_pos>(H_DISPLAY-1) || v_pos>(V_DISPLAY-1))
                        begin
                                BLANK <= 1'b0;
                        end
                        else
                        begin
                                BLANK <= 1'b1;
                        end
                end
        end
 
        assign VGA_CLK = clk;
        assign VGA_SYNC = 1'b1;
 
        always @(posedge clk )
        begin
                R <= R_in;
                G <= G_in;
                B <= B_in;
        end
 
 
        // Bloco para geracao dos enderecos de cada pixel na memoria
        // Cada pixel está guardado em um endereco diferente, sequencialmente
        always @(posedge clk )
        begin
 
                // Reset no circuito, endereco vai para zero
                if (rst == 1'b1)
                begin
                        oAddress <= 20'h00000;
                end
 
                // Operacao normal, apos reset
                else
                begin
                        // Operacao na parte visivel do video
                        if( h_pos<=(H_DISPLAY-1) && v_pos<=(V_DISPLAY-1) )
                        begin
 
                                // Enquanto nao tiver atingido o ultimo pixel
                                if ( oAddress < ((H_DISPLAY*V_DISPLAY) - 1)  )
                                begin
                                        oAddress <= oAddress + 1'b1;
                                end
 
                                // Retorna para o inicio apos atingir o ultimo pixel
                                else
                                begin
                                        oAddress <= 1'b0;
                                end
 
                        end
 
                        // Operacao na parte de sincronismo do video
                        else
                        begin
                                oAddress <= oAddress;
                        end
                end
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	lucas.vbal	`module VGA_Interface(`
2
3			`clk,`
4			`rst,`
5			`R_in,`
6			`G_in,`
7			`B_in,`
8
9			`oAddress,`
10			`R,G,B,`
11			`BLANK,`
12			`VGA_SYNC,`
13			`VGA_CLK,`
14			`HS,VS,`
15			`v_pos,`
16			`h_pos`
17			`);`
18
19			`input [7:0] R_in, G_in, B_in;`
20			`input clk, rst;`
21
22			`output reg [7:0] R, G, B;`
23			`output reg HS, VS;`
24			`output reg BLANK;`
25			`output VGA_SYNC, VGA_CLK;`
26
27			`output reg [9:0] h_pos, v_pos;`
28			`output reg [19:0] oAddress;`
29
30			`parameter H_FRONT = 16; //16`
31			`parameter H_SYNC = 96; //96`
32			`parameter H_BACK = 48; //48`
33			`parameter H_DISPLAY = 640;`
34			`parameter H_BLANK = H_SYNC+H_BACK;`
35			`parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_DISPLAY;`
36
37			`parameter V_FRONT = 12; //12`
38			`parameter V_SYNC = 2; //2`
39			`parameter V_BACK = 31; //31`
40			`parameter V_DISPLAY = 480;`
41			`parameter V_BLANK = V_SYNC+V_BACK;`
42			`parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_DISPLAY;`
43
44			`reg b_flag;`
45
46			`always @(posedge clk)`
47			`begin`
48			`if (rst == 1'b1)`
49			`begin`
50			`h_pos <= 10'b0000000000;`
51			`v_pos <= 10'b0000000000;`
52			`end`
53
54			`else`
55			`begin`
56			`if (h_pos`
57			`begin`
58			`h_pos <= h_pos + 1'b1;`
59			`end`
60
61			`else`
62			`begin`
63			`h_pos <= 1'b0;`
64
65			`if (v_pos`
66			`begin`
67			`v_pos <= v_pos + 1'b1;`
68			`end`
69
70			`else`
71			`begin`
72			`v_pos <= 1'b0;`
73			`end`
74			`end`
75			`end`
76			`end`
77
78			`// Sincronismo Horizontal`
79			`always @(posedge clk)`
80			`begin`
81			`if (rst == 1'b1)`
82			`begin`
83			`HS <= 1'b1;`
84			`end`
85			`else`
86			`begin`
87			`if ( (h_pos > H_DISPLAY+H_FRONT-1) && (h_pos < H_TOTAL-H_BACK-1) )`
88			`begin`
89			`HS <= 1'b0;`
90			`end`
91			`else`
92			`begin`
93			`HS <= 1'b1;`
94			`end`
95			`end`
96			`end`
97
98			`// Sincronismo Vertical`
99			`always @(posedge clk)`
100			`begin`
101			`if (rst == 1'b1)`
102			`begin`
103			`VS <= 1'b1;`
104			`end`
105			`else`
106			`begin`
107			`if ( (v_pos > V_DISPLAY+V_FRONT-1) && (v_pos < V_TOTAL-V_BACK-1) )`
108			`begin`
109			`VS <= 1'b0;`
110			`end`
111			`else`
112			`begin`
113			`VS <= 1'b1;`
114			`end`
115			`end`
116			`end`
117
118			`// Blank`
119			`always @(posedge clk)`
120			`begin`
121			`if (rst == 1'b1)`
122			`begin`
123			`BLANK <= 1'b1;`
124			`end`
125			`else`
126			`begin`
127			`if (h_pos>(H_DISPLAY-1) \|\| v_pos>(V_DISPLAY-1))`
128			`begin`
129			`BLANK <= 1'b0;`
130			`end`
131			`else`
132			`begin`
133			`BLANK <= 1'b1;`
134			`end`
135			`end`
136			`end`
137
138			`assign VGA_CLK = clk;`
139			`assign VGA_SYNC = 1'b1;`
140
141			`always @(posedge clk )`
142			`begin`
143			`R <= R_in;`
144			`G <= G_in;`
145			`B <= B_in;`
146			`end`
147
148
149			`// Bloco para geracao dos enderecos de cada pixel na memoria`
150			`// Cada pixel está guardado em um endereco diferente, sequencialmente`
151			`always @(posedge clk )`
152			`begin`
153
154			`// Reset no circuito, endereco vai para zero`
155			`if (rst == 1'b1)`
156			`begin`
157			`oAddress <= 20'h00000;`
158			`end`
159
160			`// Operacao normal, apos reset`
161			`else`
162			`begin`
163			`// Operacao na parte visivel do video`
164			`if( h_pos<=(H_DISPLAY-1) && v_pos<=(V_DISPLAY-1) )`
165			`begin`
166
167			`// Enquanto nao tiver atingido o ultimo pixel`
168			`if ( oAddress < ((H_DISPLAY*V_DISPLAY) - 1) )`
169			`begin`
170			`oAddress <= oAddress + 1'b1;`
171			`end`
172
173			`// Retorna para o inicio apos atingir o ultimo pixel`
174			`else`
175			`begin`
176			`oAddress <= 1'b0;`
177			`end`
178
179			`end`
180
181			`// Operacao na parte de sincronismo do video`
182			`else`
183			`begin`
184			`oAddress <= oAddress;`
185			`end`
186			`end`
187			`end`
188
189			`endmodule`

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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [VGA_Interface.v.bak] - Blame information for rev 2