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lucas.vbal |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1531701090312 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1531701090312 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "Processor EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"Processor\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1531701090782 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1531701090940 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1531701090940 ""}
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{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] 1 2 0 0 " "Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/ip_pll_altpll.v" "" { Text "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/db/ip_pll_altpll.v" 44 -1 0 } } { "" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 8505 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1531701091301 ""} } { { "db/ip_pll_altpll.v" "" { Text "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/db/ip_pll_altpll.v" 44 -1 0 } } { "" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 8505 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1531701091301 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1531701092354 ""}
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{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1531701092759 ""}
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{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531701094139 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1531701094139 ""}
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{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 50111 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531701094438 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 50113 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531701094438 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 50115 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531701094438 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 50117 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531701094438 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/17.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 50119 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531701094438 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1531701094438 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1531701094579 ""}
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{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1531701100035 ""}
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{ "Info" "ISTA_SDC_FOUND" "Processor_SDC.sdc " "Reading SDC File: 'Processor_SDC.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1531701107545 ""}
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{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst17\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{inst17\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst17\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst17\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{inst17\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst17\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1531701107625 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1531701107625 ""}
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{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1531701107625 ""}
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{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1531701108032 ""}
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{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1531701108032 ""}
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{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1531701108079 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1531701108079 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 clock " " 20.000 clock" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1531701108079 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 inst17\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 40.000 inst17\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1531701108079 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1531701108079 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node clock~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1531701111172 ""} } { { "Processor.bdf" "" { Schematic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/Processor.bdf" { { -528 -3184 -3008 -512 "clock" "" } } } } { "temporary_test_loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 50081 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1531701111172 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Automatically promoted node IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1531701111172 ""} } { { "db/ip_pll_altpll.v" "" { Text "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/db/ip_pll_altpll.v" 78 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 0 { 0 ""} 0 8505 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1531701111172 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1531701114619 ""}
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{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1531701114650 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1531701114650 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1531701114701 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1531701114763 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1531701114810 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1531701117207 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1531701117239 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1531701117239 ""}
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{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|pll1 clk\[0\] VGA_CLK~output " "PLL \"IP_PLL:inst17\|altpll:altpll_component\|IP_PLL_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"VGA_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/ip_pll_altpll.v" "" { Text "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/db/ip_pll_altpll.v" 44 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altpll.tdf" 898 0 0 } } { "IP_PLL.vhd" "" { Text "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/IP_PLL.vhd" 134 0 0 } } { "Processor.bdf" "" { Schematic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/Processor.bdf" { { -616 3072 3208 -536 "inst17" "" } } } } { "Processor.bdf" "" { Schematic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/Processor.bdf" { { -360 3816 3992 -344 "VGA_CLK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1531701117613 ""}
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{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:30 " "Fitter preparation operations ending: elapsed time is 00:00:30" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531701123073 ""}
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{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1531701123293 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1531701130426 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:16 " "Fitter placement preparation operations ending: elapsed time is 00:00:16" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531701146593 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1531701147032 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1531701336588 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:03:10 " "Fitter placement operations ending: elapsed time is 00:03:10" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531701336588 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1531701342057 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "15 " "Router estimated average interconnect usage is 15% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "69 X23_Y24 X33_Y36 " "Router estimated peak interconnect usage is 69% of the available device resources in the region that extends from location X23_Y24 to location X33_Y36" { } { { "loc" "" { Generic "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 69% of the available device resources in the region that extends from location X23_Y24 to location X33_Y36"} { { 12 { 0 ""} 23 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1531701378649 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1531701378649 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1531701399615 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1531701399615 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1531701399615 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:52 " "Fitter routing operations ending: elapsed time is 00:00:52" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531701399615 ""}
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| 41 |
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{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 35.70 " "Total time spent on timing analysis during the Fitter is 35.70 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1531701400602 ""}
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| 42 |
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1531701400867 ""}
|
| 43 |
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|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1531701405412 ""}
|
| 44 |
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1531701405427 ""}
|
| 45 |
|
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1531701409676 ""}
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| 46 |
|
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{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:16 " "Fitter post-fit operations ending: elapsed time is 00:00:16" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531701416304 ""}
|
| 47 |
|
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Lucas/Desktop/TCC/Processor_Quartus/output_files/Processor.fit.smsg " "Generated suppressed messages file C:/Users/Lucas/Desktop/TCC/Processor_Quartus/output_files/Processor.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1531701425521 ""}
|
| 48 |
|
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1546 " "Peak virtual memory: 1546 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1531701432366 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 15 21:37:12 2018 " "Processing ended: Sun Jul 15 21:37:12 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1531701432366 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:47 " "Elapsed time: 00:05:47" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1531701432366 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:48 " "Total CPU time (on all processors): 00:08:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1531701432366 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1531701432366 ""}
|
