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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=2 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=16 WIDTH_N=16 clock denominator numerator quotient remainder

--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_abs 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_divide 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END

-- Copyright (C) 2017  Intel Corporation. All rights reserved.

--  Your use of Intel Corporation's design tools, logic functions

--  and other software and tools, and its AMPP partner logic

--  functions, and any output files from any of the foregoing

--  (including device programming or simulation files), and any

--  associated documentation or information are expressly subject

--  to the terms and conditions of the Intel Program License

--  Subscription Agreement, the Intel Quartus Prime License Agreement,

--  the Intel MegaCore Function License Agreement, or other

--  applicable license agreement, including, without limitation,

--  that your use is for the sole purpose of programming logic

--  devices manufactured by Intel and sold by Intel or its

--  authorized distributors.  Please refer to the applicable

--  agreement for further details.

FUNCTION alt_u_div_srf (clock, denominator[15..0], numerator[15..0])

RETURNS ( quotient[15..0], remainder[15..0]);

FUNCTION lpm_abs_k0a (data[15..0])

RETURNS ( result[15..0]);

--synthesis_resources = lut 179 reg 132

OPTIONS ALTERA_INTERNAL_OPTION = "{-to DFF_diff_signs} POWER_UP_LEVEL=HIGH";

SUBDESIGN abs_divider_mug

(

        clock   :       input;

        denominator[15..0]      :       input;

        numerator[15..0]        :       input;

        quotient[15..0] :       output;

        remainder[15..0]        :       output;

)

VARIABLE

        divider : alt_u_div_srf;

        DFF_diff_signs[1..0] : dffe

                WITH (

                        power_up = "high"

                );

        DFF_num_sign[1..0] : dffe;

        my_abs_den : lpm_abs_k0a;

        my_abs_num : lpm_abs_k0a;

        compl_add_quot_result_int[16..0]        :       WIRE;

        compl_add_quot_cin      :       WIRE;

        compl_add_quot_dataa[15..0]     :       WIRE;

        compl_add_quot_datab[15..0]     :       WIRE;

        compl_add_quot_result[15..0]    :       WIRE;

        compl_add_rem_result_int[16..0] :       WIRE;

        compl_add_rem_cin       :       WIRE;

        compl_add_rem_dataa[15..0]      :       WIRE;

        compl_add_rem_datab[15..0]      :       WIRE;

        compl_add_rem_result[15..0]     :       WIRE;

        aclr    : NODE;

        clk_en  : NODE;

        dff_num_sign_q_out      : WIRE;

        diff_signs      : WIRE;

        gnd_wire        : WIRE;

        neg_quot[15..0] : WIRE;

        neg_rem[15..0]  : WIRE;

        norm_den[15..0] : WIRE;

        norm_num[15..0] : WIRE;

        num_sign        : WIRE;

        protect_quotient[15..0] : WIRE;

        protect_remainder[15..0]        : WIRE;

        vcc_wire        : WIRE;

BEGIN

        divider.clock = clock;

        divider.denominator[] = norm_den[];

        divider.numerator[] = norm_num[];

        DFF_diff_signs[].clk = clock;

        DFF_diff_signs[].d = ( ( diff_signs, DFF_diff_signs[1..1].q));

        DFF_diff_signs[].ena = clk_en;

        DFF_diff_signs[].prn = (! aclr);

        DFF_num_sign[].clk = clock;

        DFF_num_sign[].clrn = (! aclr);

        DFF_num_sign[].d = ( ( num_sign, DFF_num_sign[1..1].q));

        DFF_num_sign[].ena = clk_en;

        my_abs_den.data[] = denominator[];

        my_abs_num.data[] = numerator[];

        compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);

        compl_add_quot_result[] = compl_add_quot_result_int[16..1];

        compl_add_quot_cin = vcc_wire;

        compl_add_quot_dataa[] = (! protect_quotient[]);

        compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);

        compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);

        compl_add_rem_result[] = compl_add_rem_result_int[16..1];

        compl_add_rem_cin = vcc_wire;

        compl_add_rem_dataa[] = (! protect_remainder[]);

        compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);

        aclr = GND;

        clk_en = VCC;

        dff_num_sign_q_out = DFF_num_sign[0..0].q;

        diff_signs = (numerator[15..15] $ denominator[15..15]);

        gnd_wire = B"0";

        neg_quot[] = compl_add_quot_result[];

        neg_rem[] = compl_add_rem_result[];

        norm_den[] = my_abs_den.result[];

        norm_num[] = my_abs_num.result[];

        num_sign = numerator[15..15];

        protect_quotient[] = divider.quotient[];

        protect_remainder[] = divider.remainder[];

        quotient[] = ((protect_quotient[] & (! DFF_diff_signs[0..0].q)) # (neg_quot[] & DFF_diff_signs[0..0].q));

        remainder[] = ((protect_remainder[] & (! dff_num_sign_q_out)) # (neg_rem[] & dff_num_sign_q_out));

        vcc_wire = B"1";

END;

--VALID FILE