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lucas.vbal |
--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=5 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=16 WIDTH_N=16 clock denominator numerator quotient remainder
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--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_abs 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_divide 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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FUNCTION alt_u_div_vrf (clock, denominator[15..0], numerator[15..0])
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RETURNS ( quotient[15..0], remainder[15..0]);
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FUNCTION lpm_abs_k0a (data[15..0])
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RETURNS ( result[15..0]);
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--synthesis_resources = lut 179 reg 330
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OPTIONS ALTERA_INTERNAL_OPTION = "{-to DFF_diff_signs} POWER_UP_LEVEL=HIGH";
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SUBDESIGN abs_divider_pug
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(
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clock : input;
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denominator[15..0] : input;
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numerator[15..0] : input;
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quotient[15..0] : output;
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remainder[15..0] : output;
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)
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VARIABLE
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divider : alt_u_div_vrf;
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DFF_diff_signs[4..0] : dffe
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WITH (
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power_up = "high"
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);
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DFF_num_sign[4..0] : dffe;
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my_abs_den : lpm_abs_k0a;
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my_abs_num : lpm_abs_k0a;
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compl_add_quot_result_int[16..0] : WIRE;
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compl_add_quot_cin : WIRE;
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compl_add_quot_dataa[15..0] : WIRE;
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compl_add_quot_datab[15..0] : WIRE;
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compl_add_quot_result[15..0] : WIRE;
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compl_add_rem_result_int[16..0] : WIRE;
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compl_add_rem_cin : WIRE;
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compl_add_rem_dataa[15..0] : WIRE;
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compl_add_rem_datab[15..0] : WIRE;
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compl_add_rem_result[15..0] : WIRE;
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aclr : NODE;
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clk_en : NODE;
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dff_num_sign_q_out : WIRE;
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diff_signs : WIRE;
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gnd_wire : WIRE;
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neg_quot[15..0] : WIRE;
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neg_rem[15..0] : WIRE;
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norm_den[15..0] : WIRE;
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norm_num[15..0] : WIRE;
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num_sign : WIRE;
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protect_quotient[15..0] : WIRE;
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protect_remainder[15..0] : WIRE;
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vcc_wire : WIRE;
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BEGIN
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divider.clock = clock;
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divider.denominator[] = norm_den[];
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divider.numerator[] = norm_num[];
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DFF_diff_signs[].clk = clock;
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DFF_diff_signs[].d = ( ( diff_signs, DFF_diff_signs[4..1].q));
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DFF_diff_signs[].ena = clk_en;
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DFF_diff_signs[].prn = (! aclr);
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DFF_num_sign[].clk = clock;
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DFF_num_sign[].clrn = (! aclr);
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DFF_num_sign[].d = ( ( num_sign, DFF_num_sign[4..1].q));
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DFF_num_sign[].ena = clk_en;
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my_abs_den.data[] = denominator[];
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my_abs_num.data[] = numerator[];
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compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
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compl_add_quot_result[] = compl_add_quot_result_int[16..1];
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compl_add_quot_cin = vcc_wire;
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compl_add_quot_dataa[] = (! protect_quotient[]);
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compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
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compl_add_rem_result[] = compl_add_rem_result_int[16..1];
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compl_add_rem_cin = vcc_wire;
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compl_add_rem_dataa[] = (! protect_remainder[]);
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compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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aclr = GND;
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clk_en = VCC;
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dff_num_sign_q_out = DFF_num_sign[0..0].q;
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diff_signs = (numerator[15..15] $ denominator[15..15]);
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gnd_wire = B"0";
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neg_quot[] = compl_add_quot_result[];
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neg_rem[] = compl_add_rem_result[];
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norm_den[] = my_abs_den.result[];
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norm_num[] = my_abs_num.result[];
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num_sign = numerator[15..15];
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protect_quotient[] = divider.quotient[];
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protect_remainder[] = divider.remainder[];
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quotient[] = ((protect_quotient[] & (! DFF_diff_signs[0..0].q)) # (neg_quot[] & DFF_diff_signs[0..0].q));
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remainder[] = ((protect_remainder[] & (! dff_num_sign_q_out)) # (neg_rem[] & dff_num_sign_q_out));
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vcc_wire = B"1";
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END;
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--VALID FILE
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