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lucas.vbal |
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=16 ONE_INPUT_IS_CONSTANT="NO" clock dataa datab overflow result
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--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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--synthesis_resources = lut 18
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SUBDESIGN add_sub_nek
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(
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clock : input;
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dataa[15..0] : input;
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datab[15..0] : input;
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overflow : output;
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result[15..0] : output;
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)
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VARIABLE
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pipeline_dffe[15..0] : DFFE
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WITH (
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power_up ="low"
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);
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overflow_dffe[15..0] : DFFE
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WITH (
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power_up ="low"
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);
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result_int[15..0] : WIRE;
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BEGIN
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result_int[] = dataa[] - datab[];
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pipeline_dffe[].clk = clock;
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overflow_dffe[].clk = clock;
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result[] = pipeline_dffe[15..0].q;
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pipeline_dffe[15..0].d = result_int[];
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overflow = overflow_dffe[0..0].q;
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overflow_dffe[0].d = (dataa[15] $ datab[15]) & (dataa[15] $ result_int[15]);
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END;
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--VALID FILE
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