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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [altsyncram_jer3.tdf] - Blame information for rev 2

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1 2 lucas.vbal
--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE="program.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=2048 NUMWORDS_B=0 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=32 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=11 WIDTHAD_B=1 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
2
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END
3
 
4
 
5
-- Copyright (C) 2017  Intel Corporation. All rights reserved.
6
--  Your use of Intel Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Intel Program License
12
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
13
--  the Intel MegaCore Function License Agreement, or other
14
--  applicable license agreement, including, without limitation,
15
--  that your use is for the sole purpose of programming logic
16
--  devices manufactured by Intel and sold by Intel or its
17
--  authorized distributors.  Please refer to the applicable
18
--  agreement for further details.
19
 
20
 
21
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
22
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
23
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
24
 
25
--synthesis_resources = M9K 8
26
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
27
 
28
SUBDESIGN altsyncram_jer3
29
(
30
        address_a[10..0]        :       input;
31
        clock0  :       input;
32
        q_a[31..0]      :       output;
33
)
34
VARIABLE
35
        ram_block1a0 : cycloneive_ram_block
36
                WITH (
37
                        CLK0_CORE_CLOCK_ENABLE = "none",
38
                        CLK0_INPUT_CLOCK_ENABLE = "none",
39
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
40
                        CONNECTIVITY_CHECKING = "OFF",
41
                        INIT_FILE = "program.mif",
42
                        INIT_FILE_LAYOUT = "port_a",
43
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
44
                        OPERATION_MODE = "rom",
45
                        PORT_A_ADDRESS_CLEAR = "none",
46
                        PORT_A_ADDRESS_WIDTH = 11,
47
                        PORT_A_DATA_OUT_CLEAR = "none",
48
                        PORT_A_DATA_OUT_CLOCK = "clock0",
49
                        PORT_A_DATA_WIDTH = 1,
50
                        PORT_A_FIRST_ADDRESS = 0,
51
                        PORT_A_FIRST_BIT_NUMBER = 0,
52
                        PORT_A_LAST_ADDRESS = 2047,
53
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
54
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
55
                        POWER_UP_UNINITIALIZED = "false",
56
                        RAM_BLOCK_TYPE = "AUTO"
57
                );
58
        ram_block1a1 : cycloneive_ram_block
59
                WITH (
60
                        CLK0_CORE_CLOCK_ENABLE = "none",
61
                        CLK0_INPUT_CLOCK_ENABLE = "none",
62
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
63
                        CONNECTIVITY_CHECKING = "OFF",
64
                        INIT_FILE = "program.mif",
65
                        INIT_FILE_LAYOUT = "port_a",
66
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
67
                        OPERATION_MODE = "rom",
68
                        PORT_A_ADDRESS_CLEAR = "none",
69
                        PORT_A_ADDRESS_WIDTH = 11,
70
                        PORT_A_DATA_OUT_CLEAR = "none",
71
                        PORT_A_DATA_OUT_CLOCK = "clock0",
72
                        PORT_A_DATA_WIDTH = 1,
73
                        PORT_A_FIRST_ADDRESS = 0,
74
                        PORT_A_FIRST_BIT_NUMBER = 1,
75
                        PORT_A_LAST_ADDRESS = 2047,
76
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
77
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
78
                        POWER_UP_UNINITIALIZED = "false",
79
                        RAM_BLOCK_TYPE = "AUTO"
80
                );
81
        ram_block1a2 : cycloneive_ram_block
82
                WITH (
83
                        CLK0_CORE_CLOCK_ENABLE = "none",
84
                        CLK0_INPUT_CLOCK_ENABLE = "none",
85
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
86
                        CONNECTIVITY_CHECKING = "OFF",
87
                        INIT_FILE = "program.mif",
88
                        INIT_FILE_LAYOUT = "port_a",
89
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
90
                        OPERATION_MODE = "rom",
91
                        PORT_A_ADDRESS_CLEAR = "none",
92
                        PORT_A_ADDRESS_WIDTH = 11,
93
                        PORT_A_DATA_OUT_CLEAR = "none",
94
                        PORT_A_DATA_OUT_CLOCK = "clock0",
95
                        PORT_A_DATA_WIDTH = 1,
96
                        PORT_A_FIRST_ADDRESS = 0,
97
                        PORT_A_FIRST_BIT_NUMBER = 2,
98
                        PORT_A_LAST_ADDRESS = 2047,
99
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
100
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
101
                        POWER_UP_UNINITIALIZED = "false",
102
                        RAM_BLOCK_TYPE = "AUTO"
103
                );
104
        ram_block1a3 : cycloneive_ram_block
105
                WITH (
106
                        CLK0_CORE_CLOCK_ENABLE = "none",
107
                        CLK0_INPUT_CLOCK_ENABLE = "none",
108
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
109
                        CONNECTIVITY_CHECKING = "OFF",
110
                        INIT_FILE = "program.mif",
111
                        INIT_FILE_LAYOUT = "port_a",
112
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
113
                        OPERATION_MODE = "rom",
114
                        PORT_A_ADDRESS_CLEAR = "none",
115
                        PORT_A_ADDRESS_WIDTH = 11,
116
                        PORT_A_DATA_OUT_CLEAR = "none",
117
                        PORT_A_DATA_OUT_CLOCK = "clock0",
118
                        PORT_A_DATA_WIDTH = 1,
119
                        PORT_A_FIRST_ADDRESS = 0,
120
                        PORT_A_FIRST_BIT_NUMBER = 3,
121
                        PORT_A_LAST_ADDRESS = 2047,
122
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
123
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
124
                        POWER_UP_UNINITIALIZED = "false",
125
                        RAM_BLOCK_TYPE = "AUTO"
126
                );
127
        ram_block1a4 : cycloneive_ram_block
128
                WITH (
129
                        CLK0_CORE_CLOCK_ENABLE = "none",
130
                        CLK0_INPUT_CLOCK_ENABLE = "none",
131
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
132
                        CONNECTIVITY_CHECKING = "OFF",
133
                        INIT_FILE = "program.mif",
134
                        INIT_FILE_LAYOUT = "port_a",
135
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
136
                        OPERATION_MODE = "rom",
137
                        PORT_A_ADDRESS_CLEAR = "none",
138
                        PORT_A_ADDRESS_WIDTH = 11,
139
                        PORT_A_DATA_OUT_CLEAR = "none",
140
                        PORT_A_DATA_OUT_CLOCK = "clock0",
141
                        PORT_A_DATA_WIDTH = 1,
142
                        PORT_A_FIRST_ADDRESS = 0,
143
                        PORT_A_FIRST_BIT_NUMBER = 4,
144
                        PORT_A_LAST_ADDRESS = 2047,
145
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
146
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
147
                        POWER_UP_UNINITIALIZED = "false",
148
                        RAM_BLOCK_TYPE = "AUTO"
149
                );
150
        ram_block1a5 : cycloneive_ram_block
151
                WITH (
152
                        CLK0_CORE_CLOCK_ENABLE = "none",
153
                        CLK0_INPUT_CLOCK_ENABLE = "none",
154
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
155
                        CONNECTIVITY_CHECKING = "OFF",
156
                        INIT_FILE = "program.mif",
157
                        INIT_FILE_LAYOUT = "port_a",
158
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
159
                        OPERATION_MODE = "rom",
160
                        PORT_A_ADDRESS_CLEAR = "none",
161
                        PORT_A_ADDRESS_WIDTH = 11,
162
                        PORT_A_DATA_OUT_CLEAR = "none",
163
                        PORT_A_DATA_OUT_CLOCK = "clock0",
164
                        PORT_A_DATA_WIDTH = 1,
165
                        PORT_A_FIRST_ADDRESS = 0,
166
                        PORT_A_FIRST_BIT_NUMBER = 5,
167
                        PORT_A_LAST_ADDRESS = 2047,
168
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
169
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
170
                        POWER_UP_UNINITIALIZED = "false",
171
                        RAM_BLOCK_TYPE = "AUTO"
172
                );
173
        ram_block1a6 : cycloneive_ram_block
174
                WITH (
175
                        CLK0_CORE_CLOCK_ENABLE = "none",
176
                        CLK0_INPUT_CLOCK_ENABLE = "none",
177
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
178
                        CONNECTIVITY_CHECKING = "OFF",
179
                        INIT_FILE = "program.mif",
180
                        INIT_FILE_LAYOUT = "port_a",
181
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
182
                        OPERATION_MODE = "rom",
183
                        PORT_A_ADDRESS_CLEAR = "none",
184
                        PORT_A_ADDRESS_WIDTH = 11,
185
                        PORT_A_DATA_OUT_CLEAR = "none",
186
                        PORT_A_DATA_OUT_CLOCK = "clock0",
187
                        PORT_A_DATA_WIDTH = 1,
188
                        PORT_A_FIRST_ADDRESS = 0,
189
                        PORT_A_FIRST_BIT_NUMBER = 6,
190
                        PORT_A_LAST_ADDRESS = 2047,
191
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
192
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
193
                        POWER_UP_UNINITIALIZED = "false",
194
                        RAM_BLOCK_TYPE = "AUTO"
195
                );
196
        ram_block1a7 : cycloneive_ram_block
197
                WITH (
198
                        CLK0_CORE_CLOCK_ENABLE = "none",
199
                        CLK0_INPUT_CLOCK_ENABLE = "none",
200
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
201
                        CONNECTIVITY_CHECKING = "OFF",
202
                        INIT_FILE = "program.mif",
203
                        INIT_FILE_LAYOUT = "port_a",
204
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
205
                        OPERATION_MODE = "rom",
206
                        PORT_A_ADDRESS_CLEAR = "none",
207
                        PORT_A_ADDRESS_WIDTH = 11,
208
                        PORT_A_DATA_OUT_CLEAR = "none",
209
                        PORT_A_DATA_OUT_CLOCK = "clock0",
210
                        PORT_A_DATA_WIDTH = 1,
211
                        PORT_A_FIRST_ADDRESS = 0,
212
                        PORT_A_FIRST_BIT_NUMBER = 7,
213
                        PORT_A_LAST_ADDRESS = 2047,
214
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
215
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
216
                        POWER_UP_UNINITIALIZED = "false",
217
                        RAM_BLOCK_TYPE = "AUTO"
218
                );
219
        ram_block1a8 : cycloneive_ram_block
220
                WITH (
221
                        CLK0_CORE_CLOCK_ENABLE = "none",
222
                        CLK0_INPUT_CLOCK_ENABLE = "none",
223
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
224
                        CONNECTIVITY_CHECKING = "OFF",
225
                        INIT_FILE = "program.mif",
226
                        INIT_FILE_LAYOUT = "port_a",
227
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
228
                        OPERATION_MODE = "rom",
229
                        PORT_A_ADDRESS_CLEAR = "none",
230
                        PORT_A_ADDRESS_WIDTH = 11,
231
                        PORT_A_DATA_OUT_CLEAR = "none",
232
                        PORT_A_DATA_OUT_CLOCK = "clock0",
233
                        PORT_A_DATA_WIDTH = 1,
234
                        PORT_A_FIRST_ADDRESS = 0,
235
                        PORT_A_FIRST_BIT_NUMBER = 8,
236
                        PORT_A_LAST_ADDRESS = 2047,
237
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
238
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
239
                        POWER_UP_UNINITIALIZED = "false",
240
                        RAM_BLOCK_TYPE = "AUTO"
241
                );
242
        ram_block1a9 : cycloneive_ram_block
243
                WITH (
244
                        CLK0_CORE_CLOCK_ENABLE = "none",
245
                        CLK0_INPUT_CLOCK_ENABLE = "none",
246
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
247
                        CONNECTIVITY_CHECKING = "OFF",
248
                        INIT_FILE = "program.mif",
249
                        INIT_FILE_LAYOUT = "port_a",
250
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
251
                        OPERATION_MODE = "rom",
252
                        PORT_A_ADDRESS_CLEAR = "none",
253
                        PORT_A_ADDRESS_WIDTH = 11,
254
                        PORT_A_DATA_OUT_CLEAR = "none",
255
                        PORT_A_DATA_OUT_CLOCK = "clock0",
256
                        PORT_A_DATA_WIDTH = 1,
257
                        PORT_A_FIRST_ADDRESS = 0,
258
                        PORT_A_FIRST_BIT_NUMBER = 9,
259
                        PORT_A_LAST_ADDRESS = 2047,
260
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
261
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
262
                        POWER_UP_UNINITIALIZED = "false",
263
                        RAM_BLOCK_TYPE = "AUTO"
264
                );
265
        ram_block1a10 : cycloneive_ram_block
266
                WITH (
267
                        CLK0_CORE_CLOCK_ENABLE = "none",
268
                        CLK0_INPUT_CLOCK_ENABLE = "none",
269
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
270
                        CONNECTIVITY_CHECKING = "OFF",
271
                        INIT_FILE = "program.mif",
272
                        INIT_FILE_LAYOUT = "port_a",
273
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
274
                        OPERATION_MODE = "rom",
275
                        PORT_A_ADDRESS_CLEAR = "none",
276
                        PORT_A_ADDRESS_WIDTH = 11,
277
                        PORT_A_DATA_OUT_CLEAR = "none",
278
                        PORT_A_DATA_OUT_CLOCK = "clock0",
279
                        PORT_A_DATA_WIDTH = 1,
280
                        PORT_A_FIRST_ADDRESS = 0,
281
                        PORT_A_FIRST_BIT_NUMBER = 10,
282
                        PORT_A_LAST_ADDRESS = 2047,
283
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
284
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
285
                        POWER_UP_UNINITIALIZED = "false",
286
                        RAM_BLOCK_TYPE = "AUTO"
287
                );
288
        ram_block1a11 : cycloneive_ram_block
289
                WITH (
290
                        CLK0_CORE_CLOCK_ENABLE = "none",
291
                        CLK0_INPUT_CLOCK_ENABLE = "none",
292
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
293
                        CONNECTIVITY_CHECKING = "OFF",
294
                        INIT_FILE = "program.mif",
295
                        INIT_FILE_LAYOUT = "port_a",
296
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
297
                        OPERATION_MODE = "rom",
298
                        PORT_A_ADDRESS_CLEAR = "none",
299
                        PORT_A_ADDRESS_WIDTH = 11,
300
                        PORT_A_DATA_OUT_CLEAR = "none",
301
                        PORT_A_DATA_OUT_CLOCK = "clock0",
302
                        PORT_A_DATA_WIDTH = 1,
303
                        PORT_A_FIRST_ADDRESS = 0,
304
                        PORT_A_FIRST_BIT_NUMBER = 11,
305
                        PORT_A_LAST_ADDRESS = 2047,
306
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
307
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
308
                        POWER_UP_UNINITIALIZED = "false",
309
                        RAM_BLOCK_TYPE = "AUTO"
310
                );
311
        ram_block1a12 : cycloneive_ram_block
312
                WITH (
313
                        CLK0_CORE_CLOCK_ENABLE = "none",
314
                        CLK0_INPUT_CLOCK_ENABLE = "none",
315
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
316
                        CONNECTIVITY_CHECKING = "OFF",
317
                        INIT_FILE = "program.mif",
318
                        INIT_FILE_LAYOUT = "port_a",
319
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
320
                        OPERATION_MODE = "rom",
321
                        PORT_A_ADDRESS_CLEAR = "none",
322
                        PORT_A_ADDRESS_WIDTH = 11,
323
                        PORT_A_DATA_OUT_CLEAR = "none",
324
                        PORT_A_DATA_OUT_CLOCK = "clock0",
325
                        PORT_A_DATA_WIDTH = 1,
326
                        PORT_A_FIRST_ADDRESS = 0,
327
                        PORT_A_FIRST_BIT_NUMBER = 12,
328
                        PORT_A_LAST_ADDRESS = 2047,
329
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
330
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
331
                        POWER_UP_UNINITIALIZED = "false",
332
                        RAM_BLOCK_TYPE = "AUTO"
333
                );
334
        ram_block1a13 : cycloneive_ram_block
335
                WITH (
336
                        CLK0_CORE_CLOCK_ENABLE = "none",
337
                        CLK0_INPUT_CLOCK_ENABLE = "none",
338
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
339
                        CONNECTIVITY_CHECKING = "OFF",
340
                        INIT_FILE = "program.mif",
341
                        INIT_FILE_LAYOUT = "port_a",
342
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
343
                        OPERATION_MODE = "rom",
344
                        PORT_A_ADDRESS_CLEAR = "none",
345
                        PORT_A_ADDRESS_WIDTH = 11,
346
                        PORT_A_DATA_OUT_CLEAR = "none",
347
                        PORT_A_DATA_OUT_CLOCK = "clock0",
348
                        PORT_A_DATA_WIDTH = 1,
349
                        PORT_A_FIRST_ADDRESS = 0,
350
                        PORT_A_FIRST_BIT_NUMBER = 13,
351
                        PORT_A_LAST_ADDRESS = 2047,
352
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
353
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
354
                        POWER_UP_UNINITIALIZED = "false",
355
                        RAM_BLOCK_TYPE = "AUTO"
356
                );
357
        ram_block1a14 : cycloneive_ram_block
358
                WITH (
359
                        CLK0_CORE_CLOCK_ENABLE = "none",
360
                        CLK0_INPUT_CLOCK_ENABLE = "none",
361
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
362
                        CONNECTIVITY_CHECKING = "OFF",
363
                        INIT_FILE = "program.mif",
364
                        INIT_FILE_LAYOUT = "port_a",
365
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
366
                        OPERATION_MODE = "rom",
367
                        PORT_A_ADDRESS_CLEAR = "none",
368
                        PORT_A_ADDRESS_WIDTH = 11,
369
                        PORT_A_DATA_OUT_CLEAR = "none",
370
                        PORT_A_DATA_OUT_CLOCK = "clock0",
371
                        PORT_A_DATA_WIDTH = 1,
372
                        PORT_A_FIRST_ADDRESS = 0,
373
                        PORT_A_FIRST_BIT_NUMBER = 14,
374
                        PORT_A_LAST_ADDRESS = 2047,
375
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
376
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
377
                        POWER_UP_UNINITIALIZED = "false",
378
                        RAM_BLOCK_TYPE = "AUTO"
379
                );
380
        ram_block1a15 : cycloneive_ram_block
381
                WITH (
382
                        CLK0_CORE_CLOCK_ENABLE = "none",
383
                        CLK0_INPUT_CLOCK_ENABLE = "none",
384
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
385
                        CONNECTIVITY_CHECKING = "OFF",
386
                        INIT_FILE = "program.mif",
387
                        INIT_FILE_LAYOUT = "port_a",
388
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
389
                        OPERATION_MODE = "rom",
390
                        PORT_A_ADDRESS_CLEAR = "none",
391
                        PORT_A_ADDRESS_WIDTH = 11,
392
                        PORT_A_DATA_OUT_CLEAR = "none",
393
                        PORT_A_DATA_OUT_CLOCK = "clock0",
394
                        PORT_A_DATA_WIDTH = 1,
395
                        PORT_A_FIRST_ADDRESS = 0,
396
                        PORT_A_FIRST_BIT_NUMBER = 15,
397
                        PORT_A_LAST_ADDRESS = 2047,
398
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
399
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
400
                        POWER_UP_UNINITIALIZED = "false",
401
                        RAM_BLOCK_TYPE = "AUTO"
402
                );
403
        ram_block1a16 : cycloneive_ram_block
404
                WITH (
405
                        CLK0_CORE_CLOCK_ENABLE = "none",
406
                        CLK0_INPUT_CLOCK_ENABLE = "none",
407
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
408
                        CONNECTIVITY_CHECKING = "OFF",
409
                        INIT_FILE = "program.mif",
410
                        INIT_FILE_LAYOUT = "port_a",
411
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
412
                        OPERATION_MODE = "rom",
413
                        PORT_A_ADDRESS_CLEAR = "none",
414
                        PORT_A_ADDRESS_WIDTH = 11,
415
                        PORT_A_DATA_OUT_CLEAR = "none",
416
                        PORT_A_DATA_OUT_CLOCK = "clock0",
417
                        PORT_A_DATA_WIDTH = 1,
418
                        PORT_A_FIRST_ADDRESS = 0,
419
                        PORT_A_FIRST_BIT_NUMBER = 16,
420
                        PORT_A_LAST_ADDRESS = 2047,
421
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
422
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
423
                        POWER_UP_UNINITIALIZED = "false",
424
                        RAM_BLOCK_TYPE = "AUTO"
425
                );
426
        ram_block1a17 : cycloneive_ram_block
427
                WITH (
428
                        CLK0_CORE_CLOCK_ENABLE = "none",
429
                        CLK0_INPUT_CLOCK_ENABLE = "none",
430
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
431
                        CONNECTIVITY_CHECKING = "OFF",
432
                        INIT_FILE = "program.mif",
433
                        INIT_FILE_LAYOUT = "port_a",
434
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
435
                        OPERATION_MODE = "rom",
436
                        PORT_A_ADDRESS_CLEAR = "none",
437
                        PORT_A_ADDRESS_WIDTH = 11,
438
                        PORT_A_DATA_OUT_CLEAR = "none",
439
                        PORT_A_DATA_OUT_CLOCK = "clock0",
440
                        PORT_A_DATA_WIDTH = 1,
441
                        PORT_A_FIRST_ADDRESS = 0,
442
                        PORT_A_FIRST_BIT_NUMBER = 17,
443
                        PORT_A_LAST_ADDRESS = 2047,
444
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
445
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
446
                        POWER_UP_UNINITIALIZED = "false",
447
                        RAM_BLOCK_TYPE = "AUTO"
448
                );
449
        ram_block1a18 : cycloneive_ram_block
450
                WITH (
451
                        CLK0_CORE_CLOCK_ENABLE = "none",
452
                        CLK0_INPUT_CLOCK_ENABLE = "none",
453
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
454
                        CONNECTIVITY_CHECKING = "OFF",
455
                        INIT_FILE = "program.mif",
456
                        INIT_FILE_LAYOUT = "port_a",
457
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
458
                        OPERATION_MODE = "rom",
459
                        PORT_A_ADDRESS_CLEAR = "none",
460
                        PORT_A_ADDRESS_WIDTH = 11,
461
                        PORT_A_DATA_OUT_CLEAR = "none",
462
                        PORT_A_DATA_OUT_CLOCK = "clock0",
463
                        PORT_A_DATA_WIDTH = 1,
464
                        PORT_A_FIRST_ADDRESS = 0,
465
                        PORT_A_FIRST_BIT_NUMBER = 18,
466
                        PORT_A_LAST_ADDRESS = 2047,
467
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
468
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
469
                        POWER_UP_UNINITIALIZED = "false",
470
                        RAM_BLOCK_TYPE = "AUTO"
471
                );
472
        ram_block1a19 : cycloneive_ram_block
473
                WITH (
474
                        CLK0_CORE_CLOCK_ENABLE = "none",
475
                        CLK0_INPUT_CLOCK_ENABLE = "none",
476
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
477
                        CONNECTIVITY_CHECKING = "OFF",
478
                        INIT_FILE = "program.mif",
479
                        INIT_FILE_LAYOUT = "port_a",
480
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
481
                        OPERATION_MODE = "rom",
482
                        PORT_A_ADDRESS_CLEAR = "none",
483
                        PORT_A_ADDRESS_WIDTH = 11,
484
                        PORT_A_DATA_OUT_CLEAR = "none",
485
                        PORT_A_DATA_OUT_CLOCK = "clock0",
486
                        PORT_A_DATA_WIDTH = 1,
487
                        PORT_A_FIRST_ADDRESS = 0,
488
                        PORT_A_FIRST_BIT_NUMBER = 19,
489
                        PORT_A_LAST_ADDRESS = 2047,
490
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
491
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
492
                        POWER_UP_UNINITIALIZED = "false",
493
                        RAM_BLOCK_TYPE = "AUTO"
494
                );
495
        ram_block1a20 : cycloneive_ram_block
496
                WITH (
497
                        CLK0_CORE_CLOCK_ENABLE = "none",
498
                        CLK0_INPUT_CLOCK_ENABLE = "none",
499
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
500
                        CONNECTIVITY_CHECKING = "OFF",
501
                        INIT_FILE = "program.mif",
502
                        INIT_FILE_LAYOUT = "port_a",
503
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
504
                        OPERATION_MODE = "rom",
505
                        PORT_A_ADDRESS_CLEAR = "none",
506
                        PORT_A_ADDRESS_WIDTH = 11,
507
                        PORT_A_DATA_OUT_CLEAR = "none",
508
                        PORT_A_DATA_OUT_CLOCK = "clock0",
509
                        PORT_A_DATA_WIDTH = 1,
510
                        PORT_A_FIRST_ADDRESS = 0,
511
                        PORT_A_FIRST_BIT_NUMBER = 20,
512
                        PORT_A_LAST_ADDRESS = 2047,
513
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
514
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
515
                        POWER_UP_UNINITIALIZED = "false",
516
                        RAM_BLOCK_TYPE = "AUTO"
517
                );
518
        ram_block1a21 : cycloneive_ram_block
519
                WITH (
520
                        CLK0_CORE_CLOCK_ENABLE = "none",
521
                        CLK0_INPUT_CLOCK_ENABLE = "none",
522
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
523
                        CONNECTIVITY_CHECKING = "OFF",
524
                        INIT_FILE = "program.mif",
525
                        INIT_FILE_LAYOUT = "port_a",
526
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
527
                        OPERATION_MODE = "rom",
528
                        PORT_A_ADDRESS_CLEAR = "none",
529
                        PORT_A_ADDRESS_WIDTH = 11,
530
                        PORT_A_DATA_OUT_CLEAR = "none",
531
                        PORT_A_DATA_OUT_CLOCK = "clock0",
532
                        PORT_A_DATA_WIDTH = 1,
533
                        PORT_A_FIRST_ADDRESS = 0,
534
                        PORT_A_FIRST_BIT_NUMBER = 21,
535
                        PORT_A_LAST_ADDRESS = 2047,
536
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
537
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
538
                        POWER_UP_UNINITIALIZED = "false",
539
                        RAM_BLOCK_TYPE = "AUTO"
540
                );
541
        ram_block1a22 : cycloneive_ram_block
542
                WITH (
543
                        CLK0_CORE_CLOCK_ENABLE = "none",
544
                        CLK0_INPUT_CLOCK_ENABLE = "none",
545
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
546
                        CONNECTIVITY_CHECKING = "OFF",
547
                        INIT_FILE = "program.mif",
548
                        INIT_FILE_LAYOUT = "port_a",
549
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
550
                        OPERATION_MODE = "rom",
551
                        PORT_A_ADDRESS_CLEAR = "none",
552
                        PORT_A_ADDRESS_WIDTH = 11,
553
                        PORT_A_DATA_OUT_CLEAR = "none",
554
                        PORT_A_DATA_OUT_CLOCK = "clock0",
555
                        PORT_A_DATA_WIDTH = 1,
556
                        PORT_A_FIRST_ADDRESS = 0,
557
                        PORT_A_FIRST_BIT_NUMBER = 22,
558
                        PORT_A_LAST_ADDRESS = 2047,
559
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
560
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
561
                        POWER_UP_UNINITIALIZED = "false",
562
                        RAM_BLOCK_TYPE = "AUTO"
563
                );
564
        ram_block1a23 : cycloneive_ram_block
565
                WITH (
566
                        CLK0_CORE_CLOCK_ENABLE = "none",
567
                        CLK0_INPUT_CLOCK_ENABLE = "none",
568
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
569
                        CONNECTIVITY_CHECKING = "OFF",
570
                        INIT_FILE = "program.mif",
571
                        INIT_FILE_LAYOUT = "port_a",
572
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
573
                        OPERATION_MODE = "rom",
574
                        PORT_A_ADDRESS_CLEAR = "none",
575
                        PORT_A_ADDRESS_WIDTH = 11,
576
                        PORT_A_DATA_OUT_CLEAR = "none",
577
                        PORT_A_DATA_OUT_CLOCK = "clock0",
578
                        PORT_A_DATA_WIDTH = 1,
579
                        PORT_A_FIRST_ADDRESS = 0,
580
                        PORT_A_FIRST_BIT_NUMBER = 23,
581
                        PORT_A_LAST_ADDRESS = 2047,
582
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
583
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
584
                        POWER_UP_UNINITIALIZED = "false",
585
                        RAM_BLOCK_TYPE = "AUTO"
586
                );
587
        ram_block1a24 : cycloneive_ram_block
588
                WITH (
589
                        CLK0_CORE_CLOCK_ENABLE = "none",
590
                        CLK0_INPUT_CLOCK_ENABLE = "none",
591
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
592
                        CONNECTIVITY_CHECKING = "OFF",
593
                        INIT_FILE = "program.mif",
594
                        INIT_FILE_LAYOUT = "port_a",
595
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
596
                        OPERATION_MODE = "rom",
597
                        PORT_A_ADDRESS_CLEAR = "none",
598
                        PORT_A_ADDRESS_WIDTH = 11,
599
                        PORT_A_DATA_OUT_CLEAR = "none",
600
                        PORT_A_DATA_OUT_CLOCK = "clock0",
601
                        PORT_A_DATA_WIDTH = 1,
602
                        PORT_A_FIRST_ADDRESS = 0,
603
                        PORT_A_FIRST_BIT_NUMBER = 24,
604
                        PORT_A_LAST_ADDRESS = 2047,
605
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
606
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
607
                        POWER_UP_UNINITIALIZED = "false",
608
                        RAM_BLOCK_TYPE = "AUTO"
609
                );
610
        ram_block1a25 : cycloneive_ram_block
611
                WITH (
612
                        CLK0_CORE_CLOCK_ENABLE = "none",
613
                        CLK0_INPUT_CLOCK_ENABLE = "none",
614
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
615
                        CONNECTIVITY_CHECKING = "OFF",
616
                        INIT_FILE = "program.mif",
617
                        INIT_FILE_LAYOUT = "port_a",
618
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
619
                        OPERATION_MODE = "rom",
620
                        PORT_A_ADDRESS_CLEAR = "none",
621
                        PORT_A_ADDRESS_WIDTH = 11,
622
                        PORT_A_DATA_OUT_CLEAR = "none",
623
                        PORT_A_DATA_OUT_CLOCK = "clock0",
624
                        PORT_A_DATA_WIDTH = 1,
625
                        PORT_A_FIRST_ADDRESS = 0,
626
                        PORT_A_FIRST_BIT_NUMBER = 25,
627
                        PORT_A_LAST_ADDRESS = 2047,
628
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
629
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
630
                        POWER_UP_UNINITIALIZED = "false",
631
                        RAM_BLOCK_TYPE = "AUTO"
632
                );
633
        ram_block1a26 : cycloneive_ram_block
634
                WITH (
635
                        CLK0_CORE_CLOCK_ENABLE = "none",
636
                        CLK0_INPUT_CLOCK_ENABLE = "none",
637
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
638
                        CONNECTIVITY_CHECKING = "OFF",
639
                        INIT_FILE = "program.mif",
640
                        INIT_FILE_LAYOUT = "port_a",
641
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
642
                        OPERATION_MODE = "rom",
643
                        PORT_A_ADDRESS_CLEAR = "none",
644
                        PORT_A_ADDRESS_WIDTH = 11,
645
                        PORT_A_DATA_OUT_CLEAR = "none",
646
                        PORT_A_DATA_OUT_CLOCK = "clock0",
647
                        PORT_A_DATA_WIDTH = 1,
648
                        PORT_A_FIRST_ADDRESS = 0,
649
                        PORT_A_FIRST_BIT_NUMBER = 26,
650
                        PORT_A_LAST_ADDRESS = 2047,
651
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
652
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
653
                        POWER_UP_UNINITIALIZED = "false",
654
                        RAM_BLOCK_TYPE = "AUTO"
655
                );
656
        ram_block1a27 : cycloneive_ram_block
657
                WITH (
658
                        CLK0_CORE_CLOCK_ENABLE = "none",
659
                        CLK0_INPUT_CLOCK_ENABLE = "none",
660
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
661
                        CONNECTIVITY_CHECKING = "OFF",
662
                        INIT_FILE = "program.mif",
663
                        INIT_FILE_LAYOUT = "port_a",
664
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
665
                        OPERATION_MODE = "rom",
666
                        PORT_A_ADDRESS_CLEAR = "none",
667
                        PORT_A_ADDRESS_WIDTH = 11,
668
                        PORT_A_DATA_OUT_CLEAR = "none",
669
                        PORT_A_DATA_OUT_CLOCK = "clock0",
670
                        PORT_A_DATA_WIDTH = 1,
671
                        PORT_A_FIRST_ADDRESS = 0,
672
                        PORT_A_FIRST_BIT_NUMBER = 27,
673
                        PORT_A_LAST_ADDRESS = 2047,
674
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
675
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
676
                        POWER_UP_UNINITIALIZED = "false",
677
                        RAM_BLOCK_TYPE = "AUTO"
678
                );
679
        ram_block1a28 : cycloneive_ram_block
680
                WITH (
681
                        CLK0_CORE_CLOCK_ENABLE = "none",
682
                        CLK0_INPUT_CLOCK_ENABLE = "none",
683
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
684
                        CONNECTIVITY_CHECKING = "OFF",
685
                        INIT_FILE = "program.mif",
686
                        INIT_FILE_LAYOUT = "port_a",
687
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
688
                        OPERATION_MODE = "rom",
689
                        PORT_A_ADDRESS_CLEAR = "none",
690
                        PORT_A_ADDRESS_WIDTH = 11,
691
                        PORT_A_DATA_OUT_CLEAR = "none",
692
                        PORT_A_DATA_OUT_CLOCK = "clock0",
693
                        PORT_A_DATA_WIDTH = 1,
694
                        PORT_A_FIRST_ADDRESS = 0,
695
                        PORT_A_FIRST_BIT_NUMBER = 28,
696
                        PORT_A_LAST_ADDRESS = 2047,
697
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
698
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
699
                        POWER_UP_UNINITIALIZED = "false",
700
                        RAM_BLOCK_TYPE = "AUTO"
701
                );
702
        ram_block1a29 : cycloneive_ram_block
703
                WITH (
704
                        CLK0_CORE_CLOCK_ENABLE = "none",
705
                        CLK0_INPUT_CLOCK_ENABLE = "none",
706
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
707
                        CONNECTIVITY_CHECKING = "OFF",
708
                        INIT_FILE = "program.mif",
709
                        INIT_FILE_LAYOUT = "port_a",
710
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
711
                        OPERATION_MODE = "rom",
712
                        PORT_A_ADDRESS_CLEAR = "none",
713
                        PORT_A_ADDRESS_WIDTH = 11,
714
                        PORT_A_DATA_OUT_CLEAR = "none",
715
                        PORT_A_DATA_OUT_CLOCK = "clock0",
716
                        PORT_A_DATA_WIDTH = 1,
717
                        PORT_A_FIRST_ADDRESS = 0,
718
                        PORT_A_FIRST_BIT_NUMBER = 29,
719
                        PORT_A_LAST_ADDRESS = 2047,
720
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
721
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
722
                        POWER_UP_UNINITIALIZED = "false",
723
                        RAM_BLOCK_TYPE = "AUTO"
724
                );
725
        ram_block1a30 : cycloneive_ram_block
726
                WITH (
727
                        CLK0_CORE_CLOCK_ENABLE = "none",
728
                        CLK0_INPUT_CLOCK_ENABLE = "none",
729
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
730
                        CONNECTIVITY_CHECKING = "OFF",
731
                        INIT_FILE = "program.mif",
732
                        INIT_FILE_LAYOUT = "port_a",
733
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
734
                        OPERATION_MODE = "rom",
735
                        PORT_A_ADDRESS_CLEAR = "none",
736
                        PORT_A_ADDRESS_WIDTH = 11,
737
                        PORT_A_DATA_OUT_CLEAR = "none",
738
                        PORT_A_DATA_OUT_CLOCK = "clock0",
739
                        PORT_A_DATA_WIDTH = 1,
740
                        PORT_A_FIRST_ADDRESS = 0,
741
                        PORT_A_FIRST_BIT_NUMBER = 30,
742
                        PORT_A_LAST_ADDRESS = 2047,
743
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
744
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
745
                        POWER_UP_UNINITIALIZED = "false",
746
                        RAM_BLOCK_TYPE = "AUTO"
747
                );
748
        ram_block1a31 : cycloneive_ram_block
749
                WITH (
750
                        CLK0_CORE_CLOCK_ENABLE = "none",
751
                        CLK0_INPUT_CLOCK_ENABLE = "none",
752
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
753
                        CONNECTIVITY_CHECKING = "OFF",
754
                        INIT_FILE = "program.mif",
755
                        INIT_FILE_LAYOUT = "port_a",
756
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
757
                        OPERATION_MODE = "rom",
758
                        PORT_A_ADDRESS_CLEAR = "none",
759
                        PORT_A_ADDRESS_WIDTH = 11,
760
                        PORT_A_DATA_OUT_CLEAR = "none",
761
                        PORT_A_DATA_OUT_CLOCK = "clock0",
762
                        PORT_A_DATA_WIDTH = 1,
763
                        PORT_A_FIRST_ADDRESS = 0,
764
                        PORT_A_FIRST_BIT_NUMBER = 31,
765
                        PORT_A_LAST_ADDRESS = 2047,
766
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
767
                        PORT_A_LOGICAL_RAM_WIDTH = 32,
768
                        POWER_UP_UNINITIALIZED = "false",
769
                        RAM_BLOCK_TYPE = "AUTO"
770
                );
771
        address_a_wire[10..0]   : WIRE;
772
 
773
BEGIN
774
        ram_block1a[31..0].clk0 = clock0;
775
        ram_block1a[31..0].portaaddr[] = ( address_a_wire[10..0]);
776
        ram_block1a[31..0].portare = B"11111111111111111111111111111111";
777
        address_a_wire[] = address_a[];
778
        q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
779
END;
780
--VALID FILE

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