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lucas.vbal |
--altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=2048 NUMWORDS_B=0 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=16 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=11 WIDTHAD_B=1 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
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WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = M9K 4
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_lcp3
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(
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address_a[10..0] : input;
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clock0 : input;
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data_a[15..0] : input;
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q_a[15..0] : output;
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wren_a : input;
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)
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VARIABLE
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ram_block1a0 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a2 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 2,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a3 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 3,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a4 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 4,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a5 : cycloneive_ram_block
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WITH (
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| 154 |
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 5,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a6 : cycloneive_ram_block
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WITH (
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| 177 |
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 6,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a7 : cycloneive_ram_block
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WITH (
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| 200 |
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 11,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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| 210 |
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PORT_A_DATA_OUT_CLOCK = "clock0",
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| 211 |
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 7,
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PORT_A_LAST_ADDRESS = 2047,
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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| 216 |
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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| 217 |
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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| 218 |
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POWER_UP_UNINITIALIZED = "false",
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| 219 |
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RAM_BLOCK_TYPE = "AUTO"
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| 220 |
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);
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| 221 |
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ram_block1a8 : cycloneive_ram_block
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| 222 |
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WITH (
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| 223 |
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CLK0_CORE_CLOCK_ENABLE = "none",
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| 224 |
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CLK0_INPUT_CLOCK_ENABLE = "none",
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| 225 |
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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| 226 |
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CONNECTIVITY_CHECKING = "OFF",
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| 227 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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| 228 |
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OPERATION_MODE = "single_port",
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| 229 |
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PORT_A_ADDRESS_WIDTH = 11,
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| 230 |
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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| 231 |
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PORT_A_BYTE_SIZE = 1,
|
| 232 |
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PORT_A_DATA_OUT_CLEAR = "none",
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| 233 |
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PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 234 |
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PORT_A_DATA_WIDTH = 1,
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| 235 |
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PORT_A_FIRST_ADDRESS = 0,
|
| 236 |
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PORT_A_FIRST_BIT_NUMBER = 8,
|
| 237 |
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PORT_A_LAST_ADDRESS = 2047,
|
| 238 |
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PORT_A_LOGICAL_RAM_DEPTH = 2048,
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| 239 |
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PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 240 |
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 241 |
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POWER_UP_UNINITIALIZED = "false",
|
| 242 |
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|
RAM_BLOCK_TYPE = "AUTO"
|
| 243 |
|
|
);
|
| 244 |
|
|
ram_block1a9 : cycloneive_ram_block
|
| 245 |
|
|
WITH (
|
| 246 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 247 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 248 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 249 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 250 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 251 |
|
|
OPERATION_MODE = "single_port",
|
| 252 |
|
|
PORT_A_ADDRESS_WIDTH = 11,
|
| 253 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 254 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 255 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 256 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 257 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 258 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 259 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 260 |
|
|
PORT_A_LAST_ADDRESS = 2047,
|
| 261 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2048,
|
| 262 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 263 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 264 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 265 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 266 |
|
|
);
|
| 267 |
|
|
ram_block1a10 : cycloneive_ram_block
|
| 268 |
|
|
WITH (
|
| 269 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 270 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 271 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 272 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 273 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 274 |
|
|
OPERATION_MODE = "single_port",
|
| 275 |
|
|
PORT_A_ADDRESS_WIDTH = 11,
|
| 276 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 277 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 278 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 279 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 280 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 281 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 282 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 283 |
|
|
PORT_A_LAST_ADDRESS = 2047,
|
| 284 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2048,
|
| 285 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 286 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 287 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 288 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 289 |
|
|
);
|
| 290 |
|
|
ram_block1a11 : cycloneive_ram_block
|
| 291 |
|
|
WITH (
|
| 292 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 293 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 294 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 295 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 296 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 297 |
|
|
OPERATION_MODE = "single_port",
|
| 298 |
|
|
PORT_A_ADDRESS_WIDTH = 11,
|
| 299 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 300 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 301 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 302 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 303 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 304 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 305 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 306 |
|
|
PORT_A_LAST_ADDRESS = 2047,
|
| 307 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2048,
|
| 308 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 309 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 310 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 311 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 312 |
|
|
);
|
| 313 |
|
|
ram_block1a12 : cycloneive_ram_block
|
| 314 |
|
|
WITH (
|
| 315 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 316 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 317 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 318 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 319 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 320 |
|
|
OPERATION_MODE = "single_port",
|
| 321 |
|
|
PORT_A_ADDRESS_WIDTH = 11,
|
| 322 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 323 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 324 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 325 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 326 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 327 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 328 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 329 |
|
|
PORT_A_LAST_ADDRESS = 2047,
|
| 330 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2048,
|
| 331 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 332 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 333 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 334 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 335 |
|
|
);
|
| 336 |
|
|
ram_block1a13 : cycloneive_ram_block
|
| 337 |
|
|
WITH (
|
| 338 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 339 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 340 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 341 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 342 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 343 |
|
|
OPERATION_MODE = "single_port",
|
| 344 |
|
|
PORT_A_ADDRESS_WIDTH = 11,
|
| 345 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 346 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 347 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 348 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 349 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 350 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 351 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 352 |
|
|
PORT_A_LAST_ADDRESS = 2047,
|
| 353 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2048,
|
| 354 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 355 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 356 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 357 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 358 |
|
|
);
|
| 359 |
|
|
ram_block1a14 : cycloneive_ram_block
|
| 360 |
|
|
WITH (
|
| 361 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 362 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 363 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 364 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 365 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 366 |
|
|
OPERATION_MODE = "single_port",
|
| 367 |
|
|
PORT_A_ADDRESS_WIDTH = 11,
|
| 368 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 369 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 370 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 371 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 372 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 373 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 374 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 375 |
|
|
PORT_A_LAST_ADDRESS = 2047,
|
| 376 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2048,
|
| 377 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 378 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 379 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 380 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 381 |
|
|
);
|
| 382 |
|
|
ram_block1a15 : cycloneive_ram_block
|
| 383 |
|
|
WITH (
|
| 384 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 385 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 386 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 387 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 388 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 389 |
|
|
OPERATION_MODE = "single_port",
|
| 390 |
|
|
PORT_A_ADDRESS_WIDTH = 11,
|
| 391 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 392 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 393 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 394 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 395 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 396 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 397 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 398 |
|
|
PORT_A_LAST_ADDRESS = 2047,
|
| 399 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2048,
|
| 400 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 401 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 402 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 403 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 404 |
|
|
);
|
| 405 |
|
|
address_a_wire[10..0] : WIRE;
|
| 406 |
|
|
|
| 407 |
|
|
BEGIN
|
| 408 |
|
|
ram_block1a[15..0].clk0 = clock0;
|
| 409 |
|
|
ram_block1a[15..0].portaaddr[] = ( address_a_wire[10..0]);
|
| 410 |
|
|
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
| 411 |
|
|
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
| 412 |
|
|
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
| 413 |
|
|
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
| 414 |
|
|
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
| 415 |
|
|
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
| 416 |
|
|
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
| 417 |
|
|
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
| 418 |
|
|
ram_block1a[8].portadatain[] = ( data_a[8..8]);
|
| 419 |
|
|
ram_block1a[9].portadatain[] = ( data_a[9..9]);
|
| 420 |
|
|
ram_block1a[10].portadatain[] = ( data_a[10..10]);
|
| 421 |
|
|
ram_block1a[11].portadatain[] = ( data_a[11..11]);
|
| 422 |
|
|
ram_block1a[12].portadatain[] = ( data_a[12..12]);
|
| 423 |
|
|
ram_block1a[13].portadatain[] = ( data_a[13..13]);
|
| 424 |
|
|
ram_block1a[14].portadatain[] = ( data_a[14..14]);
|
| 425 |
|
|
ram_block1a[15].portadatain[] = ( data_a[15..15]);
|
| 426 |
|
|
ram_block1a[15..0].portare = B"1111111111111111";
|
| 427 |
|
|
ram_block1a[15..0].portawe = wren_a;
|
| 428 |
|
|
address_a_wire[] = address_a[];
|
| 429 |
|
|
q_a[] = ( ram_block1a[15..0].portadataout[0..0]);
|
| 430 |
|
|
END;
|
| 431 |
|
|
--VALID FILE
|
