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lucas.vbal |
--altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=65536 NUMWORDS_B=0 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=16 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=16 WIDTHAD_B=1 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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FUNCTION decode_rsa (data[2..0], enable)
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RETURNS ( eq[7..0]);
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FUNCTION decode_k8a (data[2..0])
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RETURNS ( eq[7..0]);
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FUNCTION mux_qob (data[127..0], sel[2..0])
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RETURNS ( result[15..0]);
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FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
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WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = lut 88 M9K 128 reg 6
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_lep3
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(
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address_a[15..0] : input;
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clock0 : input;
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data_a[15..0] : input;
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q_a[15..0] : output;
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wren_a : input;
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)
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VARIABLE
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address_reg_a[2..0] : dffe;
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out_address_reg_a[2..0] : dffe;
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decode3 : decode_rsa;
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rden_decode : decode_k8a;
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mux2 : mux_qob;
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ram_block1a0 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a2 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 2,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a3 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 3,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a4 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 4,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a5 : cycloneive_ram_block
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WITH (
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| 165 |
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 5,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a6 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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| 192 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "single_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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PORT_A_BYTE_SIZE = 1,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "clock0",
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 6,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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POWER_UP_UNINITIALIZED = "false",
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RAM_BLOCK_TYPE = "AUTO"
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);
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| 209 |
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ram_block1a7 : cycloneive_ram_block
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| 210 |
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WITH (
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| 211 |
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CLK0_CORE_CLOCK_ENABLE = "ena0",
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| 212 |
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CLK0_INPUT_CLOCK_ENABLE = "none",
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| 213 |
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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| 215 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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| 216 |
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OPERATION_MODE = "single_port",
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| 217 |
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PORT_A_ADDRESS_WIDTH = 13,
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| 218 |
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
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| 219 |
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PORT_A_BYTE_SIZE = 1,
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| 220 |
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PORT_A_DATA_OUT_CLEAR = "none",
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| 221 |
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PORT_A_DATA_OUT_CLOCK = "clock0",
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| 222 |
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PORT_A_DATA_WIDTH = 1,
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| 223 |
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PORT_A_FIRST_ADDRESS = 0,
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| 224 |
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PORT_A_FIRST_BIT_NUMBER = 7,
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| 225 |
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PORT_A_LAST_ADDRESS = 8191,
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| 226 |
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PORT_A_LOGICAL_RAM_DEPTH = 65536,
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| 227 |
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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| 228 |
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PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
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| 229 |
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POWER_UP_UNINITIALIZED = "false",
|
| 230 |
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RAM_BLOCK_TYPE = "AUTO"
|
| 231 |
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);
|
| 232 |
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ram_block1a8 : cycloneive_ram_block
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| 233 |
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WITH (
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| 234 |
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CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 235 |
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CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 236 |
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CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 237 |
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CONNECTIVITY_CHECKING = "OFF",
|
| 238 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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| 239 |
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OPERATION_MODE = "single_port",
|
| 240 |
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PORT_A_ADDRESS_WIDTH = 13,
|
| 241 |
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PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 242 |
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|
PORT_A_BYTE_SIZE = 1,
|
| 243 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 244 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 245 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 246 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 247 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 248 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 249 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 250 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 251 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 252 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 253 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 254 |
|
|
);
|
| 255 |
|
|
ram_block1a9 : cycloneive_ram_block
|
| 256 |
|
|
WITH (
|
| 257 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 258 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 259 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 260 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 261 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 262 |
|
|
OPERATION_MODE = "single_port",
|
| 263 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 264 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 265 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 266 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 267 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 268 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 269 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 270 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 271 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 272 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 273 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 274 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 275 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 276 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 277 |
|
|
);
|
| 278 |
|
|
ram_block1a10 : cycloneive_ram_block
|
| 279 |
|
|
WITH (
|
| 280 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 281 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 282 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 283 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 284 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 285 |
|
|
OPERATION_MODE = "single_port",
|
| 286 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 287 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 288 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 289 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 290 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 291 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 292 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 293 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 294 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 295 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 296 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 297 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 298 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 299 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 300 |
|
|
);
|
| 301 |
|
|
ram_block1a11 : cycloneive_ram_block
|
| 302 |
|
|
WITH (
|
| 303 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 304 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 305 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 306 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 307 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 308 |
|
|
OPERATION_MODE = "single_port",
|
| 309 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 310 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 311 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 312 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 313 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 314 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 315 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 316 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 317 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 318 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 319 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 320 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 321 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 322 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 323 |
|
|
);
|
| 324 |
|
|
ram_block1a12 : cycloneive_ram_block
|
| 325 |
|
|
WITH (
|
| 326 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 327 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 328 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 329 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 330 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 331 |
|
|
OPERATION_MODE = "single_port",
|
| 332 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 333 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 334 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 335 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 336 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 337 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 338 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 339 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 340 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 341 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 342 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 343 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 344 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 345 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 346 |
|
|
);
|
| 347 |
|
|
ram_block1a13 : cycloneive_ram_block
|
| 348 |
|
|
WITH (
|
| 349 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 350 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 351 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 352 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 353 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 354 |
|
|
OPERATION_MODE = "single_port",
|
| 355 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 356 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 357 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 358 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 359 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 360 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 361 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 362 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 363 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 364 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 365 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 366 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 367 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 368 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 369 |
|
|
);
|
| 370 |
|
|
ram_block1a14 : cycloneive_ram_block
|
| 371 |
|
|
WITH (
|
| 372 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 373 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 374 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 375 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 376 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 377 |
|
|
OPERATION_MODE = "single_port",
|
| 378 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 379 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 380 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 381 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 382 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 383 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 384 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 385 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 386 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 387 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 388 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 389 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 390 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 391 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 392 |
|
|
);
|
| 393 |
|
|
ram_block1a15 : cycloneive_ram_block
|
| 394 |
|
|
WITH (
|
| 395 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 396 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 397 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 398 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 399 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 400 |
|
|
OPERATION_MODE = "single_port",
|
| 401 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 402 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 403 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 404 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 405 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 406 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 407 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 408 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 409 |
|
|
PORT_A_LAST_ADDRESS = 8191,
|
| 410 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 411 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 412 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 413 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 414 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 415 |
|
|
);
|
| 416 |
|
|
ram_block1a16 : cycloneive_ram_block
|
| 417 |
|
|
WITH (
|
| 418 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 419 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 420 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 421 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 422 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 423 |
|
|
OPERATION_MODE = "single_port",
|
| 424 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 425 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 426 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 427 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 428 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 429 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 430 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 431 |
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
| 432 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 433 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 434 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 435 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 436 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 437 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 438 |
|
|
);
|
| 439 |
|
|
ram_block1a17 : cycloneive_ram_block
|
| 440 |
|
|
WITH (
|
| 441 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 442 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 443 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 444 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 445 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 446 |
|
|
OPERATION_MODE = "single_port",
|
| 447 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 448 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 449 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 450 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 451 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 452 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 453 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 454 |
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
| 455 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 456 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 457 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 458 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 459 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 460 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 461 |
|
|
);
|
| 462 |
|
|
ram_block1a18 : cycloneive_ram_block
|
| 463 |
|
|
WITH (
|
| 464 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 465 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 466 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 467 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 468 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 469 |
|
|
OPERATION_MODE = "single_port",
|
| 470 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 471 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 472 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 473 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 474 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 475 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 476 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 477 |
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
| 478 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 479 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 480 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 481 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 482 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 483 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 484 |
|
|
);
|
| 485 |
|
|
ram_block1a19 : cycloneive_ram_block
|
| 486 |
|
|
WITH (
|
| 487 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 488 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 489 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 490 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 491 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 492 |
|
|
OPERATION_MODE = "single_port",
|
| 493 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 494 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 495 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 496 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 497 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 498 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 499 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 500 |
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
| 501 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 502 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 503 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 504 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 505 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 506 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 507 |
|
|
);
|
| 508 |
|
|
ram_block1a20 : cycloneive_ram_block
|
| 509 |
|
|
WITH (
|
| 510 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 511 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 512 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 513 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 514 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 515 |
|
|
OPERATION_MODE = "single_port",
|
| 516 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 517 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 518 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 519 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 520 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 521 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 522 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 523 |
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
| 524 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 525 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 526 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 527 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 528 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 529 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 530 |
|
|
);
|
| 531 |
|
|
ram_block1a21 : cycloneive_ram_block
|
| 532 |
|
|
WITH (
|
| 533 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 534 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 535 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 536 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 537 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 538 |
|
|
OPERATION_MODE = "single_port",
|
| 539 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 540 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 541 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 542 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 543 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 544 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 545 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 546 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
| 547 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 548 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 549 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 550 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 551 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 552 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 553 |
|
|
);
|
| 554 |
|
|
ram_block1a22 : cycloneive_ram_block
|
| 555 |
|
|
WITH (
|
| 556 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 557 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 558 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 559 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 560 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 561 |
|
|
OPERATION_MODE = "single_port",
|
| 562 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 563 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 564 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 565 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 566 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 567 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 568 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 569 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 570 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 571 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 572 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 573 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 574 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 575 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 576 |
|
|
);
|
| 577 |
|
|
ram_block1a23 : cycloneive_ram_block
|
| 578 |
|
|
WITH (
|
| 579 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 580 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 581 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 582 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 583 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 584 |
|
|
OPERATION_MODE = "single_port",
|
| 585 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 586 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 587 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 588 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 589 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 590 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 591 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 592 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 593 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 594 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 595 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 596 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 597 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 598 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 599 |
|
|
);
|
| 600 |
|
|
ram_block1a24 : cycloneive_ram_block
|
| 601 |
|
|
WITH (
|
| 602 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 603 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 604 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 605 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 606 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 607 |
|
|
OPERATION_MODE = "single_port",
|
| 608 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 609 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 610 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 611 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 612 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 613 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 614 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 615 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 616 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 617 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 618 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 619 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 620 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 621 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 622 |
|
|
);
|
| 623 |
|
|
ram_block1a25 : cycloneive_ram_block
|
| 624 |
|
|
WITH (
|
| 625 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 626 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 627 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 628 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 629 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 630 |
|
|
OPERATION_MODE = "single_port",
|
| 631 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 632 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 633 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 634 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 635 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 636 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 637 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 638 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 639 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 640 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 641 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 642 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 643 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 644 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 645 |
|
|
);
|
| 646 |
|
|
ram_block1a26 : cycloneive_ram_block
|
| 647 |
|
|
WITH (
|
| 648 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 649 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 650 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 651 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 652 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 653 |
|
|
OPERATION_MODE = "single_port",
|
| 654 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 655 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 656 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 657 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 658 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 659 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 660 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 661 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 662 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 663 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 664 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 665 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 666 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 667 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 668 |
|
|
);
|
| 669 |
|
|
ram_block1a27 : cycloneive_ram_block
|
| 670 |
|
|
WITH (
|
| 671 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 672 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 673 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 674 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 675 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 676 |
|
|
OPERATION_MODE = "single_port",
|
| 677 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 678 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 679 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 680 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 681 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 682 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 683 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 684 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 685 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 686 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 687 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 688 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 689 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 690 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 691 |
|
|
);
|
| 692 |
|
|
ram_block1a28 : cycloneive_ram_block
|
| 693 |
|
|
WITH (
|
| 694 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 695 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 696 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 697 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 698 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 699 |
|
|
OPERATION_MODE = "single_port",
|
| 700 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 701 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 702 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 703 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 704 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 705 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 706 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 707 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 708 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 709 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 710 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 711 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 712 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 713 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 714 |
|
|
);
|
| 715 |
|
|
ram_block1a29 : cycloneive_ram_block
|
| 716 |
|
|
WITH (
|
| 717 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 718 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 719 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 720 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 721 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 722 |
|
|
OPERATION_MODE = "single_port",
|
| 723 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 724 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 725 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 726 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 727 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 728 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 729 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 730 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 731 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 732 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 733 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 734 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 735 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 736 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 737 |
|
|
);
|
| 738 |
|
|
ram_block1a30 : cycloneive_ram_block
|
| 739 |
|
|
WITH (
|
| 740 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 741 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 742 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 743 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 744 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 745 |
|
|
OPERATION_MODE = "single_port",
|
| 746 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 747 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 748 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 749 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 750 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 751 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 752 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 753 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 754 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 755 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 756 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 757 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 758 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 759 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 760 |
|
|
);
|
| 761 |
|
|
ram_block1a31 : cycloneive_ram_block
|
| 762 |
|
|
WITH (
|
| 763 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 764 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 765 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 766 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 767 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 768 |
|
|
OPERATION_MODE = "single_port",
|
| 769 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 770 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 771 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 772 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 773 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 774 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 775 |
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
| 776 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 777 |
|
|
PORT_A_LAST_ADDRESS = 16383,
|
| 778 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 779 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 780 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 781 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 782 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 783 |
|
|
);
|
| 784 |
|
|
ram_block1a32 : cycloneive_ram_block
|
| 785 |
|
|
WITH (
|
| 786 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 787 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 788 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 789 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 790 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 791 |
|
|
OPERATION_MODE = "single_port",
|
| 792 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 793 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 794 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 795 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 796 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 797 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 798 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 799 |
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
| 800 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 801 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 802 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 803 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 804 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 805 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 806 |
|
|
);
|
| 807 |
|
|
ram_block1a33 : cycloneive_ram_block
|
| 808 |
|
|
WITH (
|
| 809 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 810 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 811 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 812 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 813 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 814 |
|
|
OPERATION_MODE = "single_port",
|
| 815 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 816 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 817 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 818 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 819 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 820 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 821 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 822 |
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
| 823 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 824 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 825 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 826 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 827 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 828 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 829 |
|
|
);
|
| 830 |
|
|
ram_block1a34 : cycloneive_ram_block
|
| 831 |
|
|
WITH (
|
| 832 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 833 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 834 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 835 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 836 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 837 |
|
|
OPERATION_MODE = "single_port",
|
| 838 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 839 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 840 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 841 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 842 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 843 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 844 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 845 |
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
| 846 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 847 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 848 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 849 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 850 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 851 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 852 |
|
|
);
|
| 853 |
|
|
ram_block1a35 : cycloneive_ram_block
|
| 854 |
|
|
WITH (
|
| 855 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 856 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 857 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 858 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 859 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 860 |
|
|
OPERATION_MODE = "single_port",
|
| 861 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 862 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 863 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 864 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 865 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 866 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 867 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 868 |
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
| 869 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 870 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 871 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 872 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 873 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 874 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 875 |
|
|
);
|
| 876 |
|
|
ram_block1a36 : cycloneive_ram_block
|
| 877 |
|
|
WITH (
|
| 878 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 879 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 880 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 881 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 882 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 883 |
|
|
OPERATION_MODE = "single_port",
|
| 884 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 885 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 886 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 887 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 888 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 889 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 890 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 891 |
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
| 892 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 893 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 894 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 895 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 896 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 897 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 898 |
|
|
);
|
| 899 |
|
|
ram_block1a37 : cycloneive_ram_block
|
| 900 |
|
|
WITH (
|
| 901 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 902 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 903 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 904 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 905 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 906 |
|
|
OPERATION_MODE = "single_port",
|
| 907 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 908 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 909 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 910 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 911 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 912 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 913 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 914 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
| 915 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 916 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 917 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 918 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 919 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 920 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 921 |
|
|
);
|
| 922 |
|
|
ram_block1a38 : cycloneive_ram_block
|
| 923 |
|
|
WITH (
|
| 924 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 925 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 926 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 927 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 928 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 929 |
|
|
OPERATION_MODE = "single_port",
|
| 930 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 931 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 932 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 933 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 934 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 935 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 936 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 937 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 938 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 939 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 940 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 941 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 942 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 943 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 944 |
|
|
);
|
| 945 |
|
|
ram_block1a39 : cycloneive_ram_block
|
| 946 |
|
|
WITH (
|
| 947 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 948 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 949 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 950 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 951 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 952 |
|
|
OPERATION_MODE = "single_port",
|
| 953 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 954 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 955 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 956 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 957 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 958 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 959 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 960 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 961 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 962 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 963 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 964 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 965 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 966 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 967 |
|
|
);
|
| 968 |
|
|
ram_block1a40 : cycloneive_ram_block
|
| 969 |
|
|
WITH (
|
| 970 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 971 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 972 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 973 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 974 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 975 |
|
|
OPERATION_MODE = "single_port",
|
| 976 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 977 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 978 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 979 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 980 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 981 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 982 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 983 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 984 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 985 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 986 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 987 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 988 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 989 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 990 |
|
|
);
|
| 991 |
|
|
ram_block1a41 : cycloneive_ram_block
|
| 992 |
|
|
WITH (
|
| 993 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 994 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 995 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 996 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 997 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 998 |
|
|
OPERATION_MODE = "single_port",
|
| 999 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1000 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1001 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1002 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1003 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1004 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1005 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 1006 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 1007 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 1008 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1009 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1010 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1011 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1012 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1013 |
|
|
);
|
| 1014 |
|
|
ram_block1a42 : cycloneive_ram_block
|
| 1015 |
|
|
WITH (
|
| 1016 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1017 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1018 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1019 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1020 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1021 |
|
|
OPERATION_MODE = "single_port",
|
| 1022 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1023 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1024 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1025 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1026 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1027 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1028 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 1029 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 1030 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 1031 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1032 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1033 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1034 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1035 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1036 |
|
|
);
|
| 1037 |
|
|
ram_block1a43 : cycloneive_ram_block
|
| 1038 |
|
|
WITH (
|
| 1039 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1040 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1041 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1042 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1043 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1044 |
|
|
OPERATION_MODE = "single_port",
|
| 1045 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1046 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1047 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1048 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1049 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1050 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1051 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 1052 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 1053 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 1054 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1055 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1056 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1057 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1058 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1059 |
|
|
);
|
| 1060 |
|
|
ram_block1a44 : cycloneive_ram_block
|
| 1061 |
|
|
WITH (
|
| 1062 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1063 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1064 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1065 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1066 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1067 |
|
|
OPERATION_MODE = "single_port",
|
| 1068 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1069 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1070 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1071 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1072 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1073 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1074 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 1075 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 1076 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 1077 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1078 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1079 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1080 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1081 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1082 |
|
|
);
|
| 1083 |
|
|
ram_block1a45 : cycloneive_ram_block
|
| 1084 |
|
|
WITH (
|
| 1085 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1086 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1087 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1088 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1089 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1090 |
|
|
OPERATION_MODE = "single_port",
|
| 1091 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1092 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1093 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1094 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1095 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1096 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1097 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 1098 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 1099 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 1100 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1101 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1102 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1103 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1104 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1105 |
|
|
);
|
| 1106 |
|
|
ram_block1a46 : cycloneive_ram_block
|
| 1107 |
|
|
WITH (
|
| 1108 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1109 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1110 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1111 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1112 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1113 |
|
|
OPERATION_MODE = "single_port",
|
| 1114 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1115 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1116 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1117 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1118 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1119 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1120 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 1121 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 1122 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 1123 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1124 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1125 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1126 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1127 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1128 |
|
|
);
|
| 1129 |
|
|
ram_block1a47 : cycloneive_ram_block
|
| 1130 |
|
|
WITH (
|
| 1131 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1132 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1133 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1134 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1135 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1136 |
|
|
OPERATION_MODE = "single_port",
|
| 1137 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1138 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1139 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1140 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1141 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1142 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1143 |
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
| 1144 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 1145 |
|
|
PORT_A_LAST_ADDRESS = 24575,
|
| 1146 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1147 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1148 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1149 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1150 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1151 |
|
|
);
|
| 1152 |
|
|
ram_block1a48 : cycloneive_ram_block
|
| 1153 |
|
|
WITH (
|
| 1154 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1155 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1156 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1157 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1158 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1159 |
|
|
OPERATION_MODE = "single_port",
|
| 1160 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1161 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1162 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1163 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1164 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1165 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1166 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1167 |
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
| 1168 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1169 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1170 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1171 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1172 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1173 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1174 |
|
|
);
|
| 1175 |
|
|
ram_block1a49 : cycloneive_ram_block
|
| 1176 |
|
|
WITH (
|
| 1177 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1178 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1179 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1180 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1181 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1182 |
|
|
OPERATION_MODE = "single_port",
|
| 1183 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1184 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1185 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1186 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1187 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1188 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1189 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1190 |
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
| 1191 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1192 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1193 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1194 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1195 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1196 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1197 |
|
|
);
|
| 1198 |
|
|
ram_block1a50 : cycloneive_ram_block
|
| 1199 |
|
|
WITH (
|
| 1200 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1201 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1202 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1203 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1204 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1205 |
|
|
OPERATION_MODE = "single_port",
|
| 1206 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1207 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1208 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1209 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1210 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1211 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1212 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1213 |
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
| 1214 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1215 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1216 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1217 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1218 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1219 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1220 |
|
|
);
|
| 1221 |
|
|
ram_block1a51 : cycloneive_ram_block
|
| 1222 |
|
|
WITH (
|
| 1223 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1224 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1225 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1226 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1227 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1228 |
|
|
OPERATION_MODE = "single_port",
|
| 1229 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1230 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1231 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1232 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1233 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1234 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1235 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1236 |
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
| 1237 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1238 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1239 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1240 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1241 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1242 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1243 |
|
|
);
|
| 1244 |
|
|
ram_block1a52 : cycloneive_ram_block
|
| 1245 |
|
|
WITH (
|
| 1246 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1247 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1248 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1249 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1250 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1251 |
|
|
OPERATION_MODE = "single_port",
|
| 1252 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1253 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1254 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1255 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1256 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1257 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1258 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1259 |
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
| 1260 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1261 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1262 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1263 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1264 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1265 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1266 |
|
|
);
|
| 1267 |
|
|
ram_block1a53 : cycloneive_ram_block
|
| 1268 |
|
|
WITH (
|
| 1269 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1270 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1271 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1272 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1273 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1274 |
|
|
OPERATION_MODE = "single_port",
|
| 1275 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1276 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1277 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1278 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1279 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1280 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1281 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1282 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
| 1283 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1284 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1285 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1286 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1287 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1288 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1289 |
|
|
);
|
| 1290 |
|
|
ram_block1a54 : cycloneive_ram_block
|
| 1291 |
|
|
WITH (
|
| 1292 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1293 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1294 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1295 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1296 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1297 |
|
|
OPERATION_MODE = "single_port",
|
| 1298 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1299 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1300 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1301 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1302 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1303 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1304 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1305 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 1306 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1307 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1308 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1309 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1310 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1311 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1312 |
|
|
);
|
| 1313 |
|
|
ram_block1a55 : cycloneive_ram_block
|
| 1314 |
|
|
WITH (
|
| 1315 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1316 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1317 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1318 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1319 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1320 |
|
|
OPERATION_MODE = "single_port",
|
| 1321 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1322 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1323 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1324 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1325 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1326 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1327 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1328 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 1329 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1330 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1331 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1332 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1333 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1334 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1335 |
|
|
);
|
| 1336 |
|
|
ram_block1a56 : cycloneive_ram_block
|
| 1337 |
|
|
WITH (
|
| 1338 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1339 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1340 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1341 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1342 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1343 |
|
|
OPERATION_MODE = "single_port",
|
| 1344 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1345 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1346 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1347 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1348 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1349 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1350 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1351 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 1352 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1353 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1354 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1355 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1356 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1357 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1358 |
|
|
);
|
| 1359 |
|
|
ram_block1a57 : cycloneive_ram_block
|
| 1360 |
|
|
WITH (
|
| 1361 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1362 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1363 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1364 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1365 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1366 |
|
|
OPERATION_MODE = "single_port",
|
| 1367 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1368 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1369 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1370 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1371 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1372 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1373 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1374 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 1375 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1376 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1377 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1378 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1379 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1380 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1381 |
|
|
);
|
| 1382 |
|
|
ram_block1a58 : cycloneive_ram_block
|
| 1383 |
|
|
WITH (
|
| 1384 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1385 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1386 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1387 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1388 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1389 |
|
|
OPERATION_MODE = "single_port",
|
| 1390 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1391 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1392 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1393 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1394 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1395 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1396 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1397 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 1398 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1399 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1400 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1401 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1402 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1403 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1404 |
|
|
);
|
| 1405 |
|
|
ram_block1a59 : cycloneive_ram_block
|
| 1406 |
|
|
WITH (
|
| 1407 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1408 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1409 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1410 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1411 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1412 |
|
|
OPERATION_MODE = "single_port",
|
| 1413 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1414 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1415 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1416 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1417 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1418 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1419 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1420 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 1421 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1422 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1423 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1424 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1425 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1426 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1427 |
|
|
);
|
| 1428 |
|
|
ram_block1a60 : cycloneive_ram_block
|
| 1429 |
|
|
WITH (
|
| 1430 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1431 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1432 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1433 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1434 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1435 |
|
|
OPERATION_MODE = "single_port",
|
| 1436 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1437 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1438 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1439 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1440 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1441 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1442 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1443 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 1444 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1445 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1446 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1447 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1448 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1449 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1450 |
|
|
);
|
| 1451 |
|
|
ram_block1a61 : cycloneive_ram_block
|
| 1452 |
|
|
WITH (
|
| 1453 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1454 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1455 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1456 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1457 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1458 |
|
|
OPERATION_MODE = "single_port",
|
| 1459 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1460 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1461 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1462 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1463 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1464 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1465 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1466 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 1467 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1468 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1469 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1470 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1471 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1472 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1473 |
|
|
);
|
| 1474 |
|
|
ram_block1a62 : cycloneive_ram_block
|
| 1475 |
|
|
WITH (
|
| 1476 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1477 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1478 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1479 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1480 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1481 |
|
|
OPERATION_MODE = "single_port",
|
| 1482 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1483 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1484 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1485 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1486 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1487 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1488 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1489 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 1490 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1491 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1492 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1493 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1494 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1495 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1496 |
|
|
);
|
| 1497 |
|
|
ram_block1a63 : cycloneive_ram_block
|
| 1498 |
|
|
WITH (
|
| 1499 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1500 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1501 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1502 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1503 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1504 |
|
|
OPERATION_MODE = "single_port",
|
| 1505 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1506 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1507 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1508 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1509 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1510 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1511 |
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
| 1512 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 1513 |
|
|
PORT_A_LAST_ADDRESS = 32767,
|
| 1514 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1515 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1516 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1517 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1518 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1519 |
|
|
);
|
| 1520 |
|
|
ram_block1a64 : cycloneive_ram_block
|
| 1521 |
|
|
WITH (
|
| 1522 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1523 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1524 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1525 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1526 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1527 |
|
|
OPERATION_MODE = "single_port",
|
| 1528 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1529 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1530 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1531 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1532 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1533 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1534 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1535 |
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
| 1536 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1537 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1538 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1539 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1540 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1541 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1542 |
|
|
);
|
| 1543 |
|
|
ram_block1a65 : cycloneive_ram_block
|
| 1544 |
|
|
WITH (
|
| 1545 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1546 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1547 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1548 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1549 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1550 |
|
|
OPERATION_MODE = "single_port",
|
| 1551 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1552 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1553 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1554 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1555 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1556 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1557 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1558 |
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
| 1559 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1560 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1561 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1562 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1563 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1564 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1565 |
|
|
);
|
| 1566 |
|
|
ram_block1a66 : cycloneive_ram_block
|
| 1567 |
|
|
WITH (
|
| 1568 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1569 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1570 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1571 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1572 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1573 |
|
|
OPERATION_MODE = "single_port",
|
| 1574 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1575 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1576 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1577 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1578 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1579 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1580 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1581 |
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
| 1582 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1583 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1584 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1585 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1586 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1587 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1588 |
|
|
);
|
| 1589 |
|
|
ram_block1a67 : cycloneive_ram_block
|
| 1590 |
|
|
WITH (
|
| 1591 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1592 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1593 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1594 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1595 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1596 |
|
|
OPERATION_MODE = "single_port",
|
| 1597 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1598 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1599 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1600 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1601 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1602 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1603 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1604 |
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
| 1605 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1606 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1607 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1608 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1609 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1610 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1611 |
|
|
);
|
| 1612 |
|
|
ram_block1a68 : cycloneive_ram_block
|
| 1613 |
|
|
WITH (
|
| 1614 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1615 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1616 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1617 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1618 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1619 |
|
|
OPERATION_MODE = "single_port",
|
| 1620 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1621 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1622 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1623 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1624 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1625 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1626 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1627 |
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
| 1628 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1629 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1630 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1631 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1632 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1633 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1634 |
|
|
);
|
| 1635 |
|
|
ram_block1a69 : cycloneive_ram_block
|
| 1636 |
|
|
WITH (
|
| 1637 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1638 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1639 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1640 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1641 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1642 |
|
|
OPERATION_MODE = "single_port",
|
| 1643 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1644 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1645 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1646 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1647 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1648 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1649 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1650 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
| 1651 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1652 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1653 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1654 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1655 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1656 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1657 |
|
|
);
|
| 1658 |
|
|
ram_block1a70 : cycloneive_ram_block
|
| 1659 |
|
|
WITH (
|
| 1660 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1661 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1662 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1663 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1664 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1665 |
|
|
OPERATION_MODE = "single_port",
|
| 1666 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1667 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1668 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1669 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1670 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1671 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1672 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1673 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 1674 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1675 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1676 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1677 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1678 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1679 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1680 |
|
|
);
|
| 1681 |
|
|
ram_block1a71 : cycloneive_ram_block
|
| 1682 |
|
|
WITH (
|
| 1683 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1684 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1685 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1686 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1687 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1688 |
|
|
OPERATION_MODE = "single_port",
|
| 1689 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1690 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1691 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1692 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1693 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1694 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1695 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1696 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 1697 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1698 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1699 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1700 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1701 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1702 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1703 |
|
|
);
|
| 1704 |
|
|
ram_block1a72 : cycloneive_ram_block
|
| 1705 |
|
|
WITH (
|
| 1706 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1707 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1708 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1709 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1710 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1711 |
|
|
OPERATION_MODE = "single_port",
|
| 1712 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1713 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1714 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1715 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1716 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1717 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1718 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1719 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 1720 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1721 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1722 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1723 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1724 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1725 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1726 |
|
|
);
|
| 1727 |
|
|
ram_block1a73 : cycloneive_ram_block
|
| 1728 |
|
|
WITH (
|
| 1729 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1730 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1731 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1732 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1733 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1734 |
|
|
OPERATION_MODE = "single_port",
|
| 1735 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1736 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1737 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1738 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1739 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1740 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1741 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1742 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 1743 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1744 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1745 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1746 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1747 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1748 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1749 |
|
|
);
|
| 1750 |
|
|
ram_block1a74 : cycloneive_ram_block
|
| 1751 |
|
|
WITH (
|
| 1752 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1753 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1754 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1755 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1756 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1757 |
|
|
OPERATION_MODE = "single_port",
|
| 1758 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1759 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1760 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1761 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1762 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1763 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1764 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1765 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 1766 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1767 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1768 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1769 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1770 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1771 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1772 |
|
|
);
|
| 1773 |
|
|
ram_block1a75 : cycloneive_ram_block
|
| 1774 |
|
|
WITH (
|
| 1775 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1776 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1777 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1778 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1779 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1780 |
|
|
OPERATION_MODE = "single_port",
|
| 1781 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1782 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1783 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1784 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1785 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1786 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1787 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1788 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 1789 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1790 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1791 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1792 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1793 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1794 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1795 |
|
|
);
|
| 1796 |
|
|
ram_block1a76 : cycloneive_ram_block
|
| 1797 |
|
|
WITH (
|
| 1798 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1799 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1800 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1801 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1802 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1803 |
|
|
OPERATION_MODE = "single_port",
|
| 1804 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1805 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1806 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1807 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1808 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1809 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1810 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1811 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 1812 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1813 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1814 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1815 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1816 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1817 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1818 |
|
|
);
|
| 1819 |
|
|
ram_block1a77 : cycloneive_ram_block
|
| 1820 |
|
|
WITH (
|
| 1821 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1822 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1823 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1824 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1825 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1826 |
|
|
OPERATION_MODE = "single_port",
|
| 1827 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1828 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1829 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1830 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1831 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1832 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1833 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1834 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 1835 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1836 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1837 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1838 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1839 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1840 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1841 |
|
|
);
|
| 1842 |
|
|
ram_block1a78 : cycloneive_ram_block
|
| 1843 |
|
|
WITH (
|
| 1844 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1845 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1846 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1847 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1848 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1849 |
|
|
OPERATION_MODE = "single_port",
|
| 1850 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1851 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1852 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1853 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1854 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1855 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1856 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1857 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 1858 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1859 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1860 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1861 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1862 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1863 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1864 |
|
|
);
|
| 1865 |
|
|
ram_block1a79 : cycloneive_ram_block
|
| 1866 |
|
|
WITH (
|
| 1867 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1868 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1869 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1870 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1871 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1872 |
|
|
OPERATION_MODE = "single_port",
|
| 1873 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1874 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1875 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1876 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1877 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1878 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1879 |
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
| 1880 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 1881 |
|
|
PORT_A_LAST_ADDRESS = 40959,
|
| 1882 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1883 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1884 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1885 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1886 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1887 |
|
|
);
|
| 1888 |
|
|
ram_block1a80 : cycloneive_ram_block
|
| 1889 |
|
|
WITH (
|
| 1890 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1891 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1892 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1893 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1894 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1895 |
|
|
OPERATION_MODE = "single_port",
|
| 1896 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1897 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1898 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1899 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1900 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1901 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1902 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 1903 |
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
| 1904 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 1905 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1906 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1907 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1908 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1909 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1910 |
|
|
);
|
| 1911 |
|
|
ram_block1a81 : cycloneive_ram_block
|
| 1912 |
|
|
WITH (
|
| 1913 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1914 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1915 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1916 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1917 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1918 |
|
|
OPERATION_MODE = "single_port",
|
| 1919 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1920 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1921 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1922 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1923 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1924 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1925 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 1926 |
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
| 1927 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 1928 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1929 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1930 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1931 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1932 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1933 |
|
|
);
|
| 1934 |
|
|
ram_block1a82 : cycloneive_ram_block
|
| 1935 |
|
|
WITH (
|
| 1936 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1937 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1938 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1939 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1940 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1941 |
|
|
OPERATION_MODE = "single_port",
|
| 1942 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1943 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1944 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1945 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1946 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1947 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1948 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 1949 |
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
| 1950 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 1951 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1952 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1953 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1954 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1955 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1956 |
|
|
);
|
| 1957 |
|
|
ram_block1a83 : cycloneive_ram_block
|
| 1958 |
|
|
WITH (
|
| 1959 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1960 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1961 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1962 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1963 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1964 |
|
|
OPERATION_MODE = "single_port",
|
| 1965 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1966 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1967 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1968 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1969 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1970 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1971 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 1972 |
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
| 1973 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 1974 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1975 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1976 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 1977 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 1978 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 1979 |
|
|
);
|
| 1980 |
|
|
ram_block1a84 : cycloneive_ram_block
|
| 1981 |
|
|
WITH (
|
| 1982 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 1983 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 1984 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 1985 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 1986 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 1987 |
|
|
OPERATION_MODE = "single_port",
|
| 1988 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 1989 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 1990 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 1991 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 1992 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 1993 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 1994 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 1995 |
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
| 1996 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 1997 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 1998 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 1999 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2000 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2001 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2002 |
|
|
);
|
| 2003 |
|
|
ram_block1a85 : cycloneive_ram_block
|
| 2004 |
|
|
WITH (
|
| 2005 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2006 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2007 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2008 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2009 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2010 |
|
|
OPERATION_MODE = "single_port",
|
| 2011 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2012 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2013 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2014 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2015 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2016 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2017 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2018 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
| 2019 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2020 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2021 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2022 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2023 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2024 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2025 |
|
|
);
|
| 2026 |
|
|
ram_block1a86 : cycloneive_ram_block
|
| 2027 |
|
|
WITH (
|
| 2028 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2029 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2030 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2031 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2032 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2033 |
|
|
OPERATION_MODE = "single_port",
|
| 2034 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2035 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2036 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2037 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2038 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2039 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2040 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2041 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 2042 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2043 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2044 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2045 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2046 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2047 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2048 |
|
|
);
|
| 2049 |
|
|
ram_block1a87 : cycloneive_ram_block
|
| 2050 |
|
|
WITH (
|
| 2051 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2052 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2053 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2054 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2055 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2056 |
|
|
OPERATION_MODE = "single_port",
|
| 2057 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2058 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2059 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2060 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2061 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2062 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2063 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2064 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 2065 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2066 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2067 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2068 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2069 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2070 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2071 |
|
|
);
|
| 2072 |
|
|
ram_block1a88 : cycloneive_ram_block
|
| 2073 |
|
|
WITH (
|
| 2074 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2075 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2076 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2077 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2078 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2079 |
|
|
OPERATION_MODE = "single_port",
|
| 2080 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2081 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2082 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2083 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2084 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2085 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2086 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2087 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 2088 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2089 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2090 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2091 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2092 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2093 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2094 |
|
|
);
|
| 2095 |
|
|
ram_block1a89 : cycloneive_ram_block
|
| 2096 |
|
|
WITH (
|
| 2097 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2098 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2099 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2100 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2101 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2102 |
|
|
OPERATION_MODE = "single_port",
|
| 2103 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2104 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2105 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2106 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2107 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2108 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2109 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2110 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 2111 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2112 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2113 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2114 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2115 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2116 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2117 |
|
|
);
|
| 2118 |
|
|
ram_block1a90 : cycloneive_ram_block
|
| 2119 |
|
|
WITH (
|
| 2120 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2121 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2122 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2123 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2124 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2125 |
|
|
OPERATION_MODE = "single_port",
|
| 2126 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2127 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2128 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2129 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2130 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2131 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2132 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2133 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 2134 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2135 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2136 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2137 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2138 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2139 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2140 |
|
|
);
|
| 2141 |
|
|
ram_block1a91 : cycloneive_ram_block
|
| 2142 |
|
|
WITH (
|
| 2143 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2144 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2145 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2146 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2147 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2148 |
|
|
OPERATION_MODE = "single_port",
|
| 2149 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2150 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2151 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2152 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2153 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2154 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2155 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2156 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 2157 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2158 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2159 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2160 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2161 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2162 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2163 |
|
|
);
|
| 2164 |
|
|
ram_block1a92 : cycloneive_ram_block
|
| 2165 |
|
|
WITH (
|
| 2166 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2167 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2168 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2169 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2170 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2171 |
|
|
OPERATION_MODE = "single_port",
|
| 2172 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2173 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2174 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2175 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2176 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2177 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2178 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2179 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 2180 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2181 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2182 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2183 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2184 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2185 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2186 |
|
|
);
|
| 2187 |
|
|
ram_block1a93 : cycloneive_ram_block
|
| 2188 |
|
|
WITH (
|
| 2189 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2190 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2191 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2192 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2193 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2194 |
|
|
OPERATION_MODE = "single_port",
|
| 2195 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2196 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2197 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2198 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2199 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2200 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2201 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2202 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 2203 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2204 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2205 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2206 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2207 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2208 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2209 |
|
|
);
|
| 2210 |
|
|
ram_block1a94 : cycloneive_ram_block
|
| 2211 |
|
|
WITH (
|
| 2212 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2213 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2214 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2215 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2216 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2217 |
|
|
OPERATION_MODE = "single_port",
|
| 2218 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2219 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2220 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2221 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2222 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2223 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2224 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2225 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 2226 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2227 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2228 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2229 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2230 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2231 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2232 |
|
|
);
|
| 2233 |
|
|
ram_block1a95 : cycloneive_ram_block
|
| 2234 |
|
|
WITH (
|
| 2235 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2236 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2237 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2238 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2239 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2240 |
|
|
OPERATION_MODE = "single_port",
|
| 2241 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2242 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2243 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2244 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2245 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2246 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2247 |
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
| 2248 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 2249 |
|
|
PORT_A_LAST_ADDRESS = 49151,
|
| 2250 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2251 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2252 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2253 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2254 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2255 |
|
|
);
|
| 2256 |
|
|
ram_block1a96 : cycloneive_ram_block
|
| 2257 |
|
|
WITH (
|
| 2258 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2259 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2260 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2261 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2262 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2263 |
|
|
OPERATION_MODE = "single_port",
|
| 2264 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2265 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2266 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2267 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2268 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2269 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2270 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2271 |
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
| 2272 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2273 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2274 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2275 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2276 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2277 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2278 |
|
|
);
|
| 2279 |
|
|
ram_block1a97 : cycloneive_ram_block
|
| 2280 |
|
|
WITH (
|
| 2281 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2282 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2283 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2284 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2285 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2286 |
|
|
OPERATION_MODE = "single_port",
|
| 2287 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2288 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2289 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2290 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2291 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2292 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2293 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2294 |
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
| 2295 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2296 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2297 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2298 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2299 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2300 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2301 |
|
|
);
|
| 2302 |
|
|
ram_block1a98 : cycloneive_ram_block
|
| 2303 |
|
|
WITH (
|
| 2304 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2305 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2306 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2307 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2308 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2309 |
|
|
OPERATION_MODE = "single_port",
|
| 2310 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2311 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2312 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2313 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2314 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2315 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2316 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2317 |
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
| 2318 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2319 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2320 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2321 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2322 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2323 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2324 |
|
|
);
|
| 2325 |
|
|
ram_block1a99 : cycloneive_ram_block
|
| 2326 |
|
|
WITH (
|
| 2327 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2328 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2329 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2330 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2331 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2332 |
|
|
OPERATION_MODE = "single_port",
|
| 2333 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2334 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2335 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2336 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2337 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2338 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2339 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2340 |
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
| 2341 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2342 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2343 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2344 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2345 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2346 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2347 |
|
|
);
|
| 2348 |
|
|
ram_block1a100 : cycloneive_ram_block
|
| 2349 |
|
|
WITH (
|
| 2350 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2351 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2352 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2353 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2354 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2355 |
|
|
OPERATION_MODE = "single_port",
|
| 2356 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2357 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2358 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2359 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2360 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2361 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2362 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2363 |
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
| 2364 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2365 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2366 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2367 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2368 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2369 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2370 |
|
|
);
|
| 2371 |
|
|
ram_block1a101 : cycloneive_ram_block
|
| 2372 |
|
|
WITH (
|
| 2373 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2374 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2375 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2376 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2377 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2378 |
|
|
OPERATION_MODE = "single_port",
|
| 2379 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2380 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2381 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2382 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2383 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2384 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2385 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2386 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
| 2387 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2388 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2389 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2390 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2391 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2392 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2393 |
|
|
);
|
| 2394 |
|
|
ram_block1a102 : cycloneive_ram_block
|
| 2395 |
|
|
WITH (
|
| 2396 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2397 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2398 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2399 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2400 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2401 |
|
|
OPERATION_MODE = "single_port",
|
| 2402 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2403 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2404 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2405 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2406 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2407 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2408 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2409 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 2410 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2411 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2412 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2413 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2414 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2415 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2416 |
|
|
);
|
| 2417 |
|
|
ram_block1a103 : cycloneive_ram_block
|
| 2418 |
|
|
WITH (
|
| 2419 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2420 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2421 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2422 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2423 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2424 |
|
|
OPERATION_MODE = "single_port",
|
| 2425 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2426 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2427 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2428 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2429 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2430 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2431 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2432 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 2433 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2434 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2435 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2436 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2437 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2438 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2439 |
|
|
);
|
| 2440 |
|
|
ram_block1a104 : cycloneive_ram_block
|
| 2441 |
|
|
WITH (
|
| 2442 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2443 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2444 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2445 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2446 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2447 |
|
|
OPERATION_MODE = "single_port",
|
| 2448 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2449 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2450 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2451 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2452 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2453 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2454 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2455 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 2456 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2457 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2458 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2459 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2460 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2461 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2462 |
|
|
);
|
| 2463 |
|
|
ram_block1a105 : cycloneive_ram_block
|
| 2464 |
|
|
WITH (
|
| 2465 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2466 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2467 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2468 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2469 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2470 |
|
|
OPERATION_MODE = "single_port",
|
| 2471 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2472 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2473 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2474 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2475 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2476 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2477 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2478 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 2479 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2480 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2481 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2482 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2483 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2484 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2485 |
|
|
);
|
| 2486 |
|
|
ram_block1a106 : cycloneive_ram_block
|
| 2487 |
|
|
WITH (
|
| 2488 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2489 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2490 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2491 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2492 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2493 |
|
|
OPERATION_MODE = "single_port",
|
| 2494 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2495 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2496 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2497 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2498 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2499 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2500 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2501 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 2502 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2503 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2504 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2505 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2506 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2507 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2508 |
|
|
);
|
| 2509 |
|
|
ram_block1a107 : cycloneive_ram_block
|
| 2510 |
|
|
WITH (
|
| 2511 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2512 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2513 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2514 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2515 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2516 |
|
|
OPERATION_MODE = "single_port",
|
| 2517 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2518 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2519 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2520 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2521 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2522 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2523 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2524 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 2525 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2526 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2527 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2528 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2529 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2530 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2531 |
|
|
);
|
| 2532 |
|
|
ram_block1a108 : cycloneive_ram_block
|
| 2533 |
|
|
WITH (
|
| 2534 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2535 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2536 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2537 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2538 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2539 |
|
|
OPERATION_MODE = "single_port",
|
| 2540 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2541 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2542 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2543 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2544 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2545 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2546 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2547 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 2548 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2549 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2550 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2551 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2552 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2553 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2554 |
|
|
);
|
| 2555 |
|
|
ram_block1a109 : cycloneive_ram_block
|
| 2556 |
|
|
WITH (
|
| 2557 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2558 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2559 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2560 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2561 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2562 |
|
|
OPERATION_MODE = "single_port",
|
| 2563 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2564 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2565 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2566 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2567 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2568 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2569 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2570 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 2571 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2572 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2573 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2574 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2575 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2576 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2577 |
|
|
);
|
| 2578 |
|
|
ram_block1a110 : cycloneive_ram_block
|
| 2579 |
|
|
WITH (
|
| 2580 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2581 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2582 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2583 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2584 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2585 |
|
|
OPERATION_MODE = "single_port",
|
| 2586 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2587 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2588 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2589 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2590 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2591 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2592 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2593 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 2594 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2595 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2596 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2597 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2598 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2599 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2600 |
|
|
);
|
| 2601 |
|
|
ram_block1a111 : cycloneive_ram_block
|
| 2602 |
|
|
WITH (
|
| 2603 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2604 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2605 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2606 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2607 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2608 |
|
|
OPERATION_MODE = "single_port",
|
| 2609 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2610 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2611 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2612 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2613 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2614 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2615 |
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
| 2616 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 2617 |
|
|
PORT_A_LAST_ADDRESS = 57343,
|
| 2618 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2619 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2620 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2621 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2622 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2623 |
|
|
);
|
| 2624 |
|
|
ram_block1a112 : cycloneive_ram_block
|
| 2625 |
|
|
WITH (
|
| 2626 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2627 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2628 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2629 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2630 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2631 |
|
|
OPERATION_MODE = "single_port",
|
| 2632 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2633 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2634 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2635 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2636 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2637 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2638 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2639 |
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
| 2640 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2641 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2642 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2643 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2644 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2645 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2646 |
|
|
);
|
| 2647 |
|
|
ram_block1a113 : cycloneive_ram_block
|
| 2648 |
|
|
WITH (
|
| 2649 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2650 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2651 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2652 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2653 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2654 |
|
|
OPERATION_MODE = "single_port",
|
| 2655 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2656 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2657 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2658 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2659 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2660 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2661 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2662 |
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
| 2663 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2664 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2665 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2666 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2667 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2668 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2669 |
|
|
);
|
| 2670 |
|
|
ram_block1a114 : cycloneive_ram_block
|
| 2671 |
|
|
WITH (
|
| 2672 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2673 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2674 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2675 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2676 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2677 |
|
|
OPERATION_MODE = "single_port",
|
| 2678 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2679 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2680 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2681 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2682 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2683 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2684 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2685 |
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
| 2686 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2687 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2688 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2689 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2690 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2691 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2692 |
|
|
);
|
| 2693 |
|
|
ram_block1a115 : cycloneive_ram_block
|
| 2694 |
|
|
WITH (
|
| 2695 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2696 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2697 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2698 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2699 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2700 |
|
|
OPERATION_MODE = "single_port",
|
| 2701 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2702 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2703 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2704 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2705 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2706 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2707 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2708 |
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
| 2709 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2710 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2711 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2712 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2713 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2714 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2715 |
|
|
);
|
| 2716 |
|
|
ram_block1a116 : cycloneive_ram_block
|
| 2717 |
|
|
WITH (
|
| 2718 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2719 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2720 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2721 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2722 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2723 |
|
|
OPERATION_MODE = "single_port",
|
| 2724 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2725 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2726 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2727 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2728 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2729 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2730 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2731 |
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
| 2732 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2733 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2734 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2735 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2736 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2737 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2738 |
|
|
);
|
| 2739 |
|
|
ram_block1a117 : cycloneive_ram_block
|
| 2740 |
|
|
WITH (
|
| 2741 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2742 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2743 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2744 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2745 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2746 |
|
|
OPERATION_MODE = "single_port",
|
| 2747 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2748 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2749 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2750 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2751 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2752 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2753 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2754 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
| 2755 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2756 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2757 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2758 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2759 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2760 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2761 |
|
|
);
|
| 2762 |
|
|
ram_block1a118 : cycloneive_ram_block
|
| 2763 |
|
|
WITH (
|
| 2764 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2765 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2766 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2767 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2768 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2769 |
|
|
OPERATION_MODE = "single_port",
|
| 2770 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2771 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2772 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2773 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2774 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2775 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2776 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2777 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 2778 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2779 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2780 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2781 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2782 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2783 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2784 |
|
|
);
|
| 2785 |
|
|
ram_block1a119 : cycloneive_ram_block
|
| 2786 |
|
|
WITH (
|
| 2787 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2788 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2789 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2790 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2791 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2792 |
|
|
OPERATION_MODE = "single_port",
|
| 2793 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2794 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2795 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2796 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2797 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2798 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2799 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2800 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 2801 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2802 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2803 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2804 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2805 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2806 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2807 |
|
|
);
|
| 2808 |
|
|
ram_block1a120 : cycloneive_ram_block
|
| 2809 |
|
|
WITH (
|
| 2810 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2811 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2812 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2813 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2814 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2815 |
|
|
OPERATION_MODE = "single_port",
|
| 2816 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2817 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2818 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2819 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2820 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2821 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2822 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2823 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 2824 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2825 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2826 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2827 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2828 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2829 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2830 |
|
|
);
|
| 2831 |
|
|
ram_block1a121 : cycloneive_ram_block
|
| 2832 |
|
|
WITH (
|
| 2833 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2834 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2835 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2836 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2837 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2838 |
|
|
OPERATION_MODE = "single_port",
|
| 2839 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2840 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2841 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2842 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2843 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2844 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2845 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2846 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
| 2847 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2848 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2849 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2850 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2851 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2852 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2853 |
|
|
);
|
| 2854 |
|
|
ram_block1a122 : cycloneive_ram_block
|
| 2855 |
|
|
WITH (
|
| 2856 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2857 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2858 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2859 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2860 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2861 |
|
|
OPERATION_MODE = "single_port",
|
| 2862 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2863 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2864 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2865 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2866 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2867 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2868 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2869 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
| 2870 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2871 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2872 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2873 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2874 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2875 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2876 |
|
|
);
|
| 2877 |
|
|
ram_block1a123 : cycloneive_ram_block
|
| 2878 |
|
|
WITH (
|
| 2879 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2880 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2881 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2882 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2883 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2884 |
|
|
OPERATION_MODE = "single_port",
|
| 2885 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2886 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2887 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2888 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2889 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2890 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2891 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2892 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
| 2893 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2894 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2895 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2896 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2897 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2898 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2899 |
|
|
);
|
| 2900 |
|
|
ram_block1a124 : cycloneive_ram_block
|
| 2901 |
|
|
WITH (
|
| 2902 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2903 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2904 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2905 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2906 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2907 |
|
|
OPERATION_MODE = "single_port",
|
| 2908 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2909 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2910 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2911 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2912 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2913 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2914 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2915 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
| 2916 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2917 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2918 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2919 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2920 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2921 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2922 |
|
|
);
|
| 2923 |
|
|
ram_block1a125 : cycloneive_ram_block
|
| 2924 |
|
|
WITH (
|
| 2925 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2926 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2927 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2928 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2929 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2930 |
|
|
OPERATION_MODE = "single_port",
|
| 2931 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2932 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2933 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2934 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2935 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2936 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2937 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2938 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
| 2939 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2940 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2941 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2942 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2943 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2944 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2945 |
|
|
);
|
| 2946 |
|
|
ram_block1a126 : cycloneive_ram_block
|
| 2947 |
|
|
WITH (
|
| 2948 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2949 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2950 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2951 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2952 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2953 |
|
|
OPERATION_MODE = "single_port",
|
| 2954 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2955 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2956 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2957 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2958 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2959 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2960 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2961 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
| 2962 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2963 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2964 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2965 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2966 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2967 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2968 |
|
|
);
|
| 2969 |
|
|
ram_block1a127 : cycloneive_ram_block
|
| 2970 |
|
|
WITH (
|
| 2971 |
|
|
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
| 2972 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 2973 |
|
|
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
| 2974 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 2975 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 2976 |
|
|
OPERATION_MODE = "single_port",
|
| 2977 |
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
| 2978 |
|
|
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
|
| 2979 |
|
|
PORT_A_BYTE_SIZE = 1,
|
| 2980 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
| 2981 |
|
|
PORT_A_DATA_OUT_CLOCK = "clock0",
|
| 2982 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 2983 |
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
| 2984 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
| 2985 |
|
|
PORT_A_LAST_ADDRESS = 65535,
|
| 2986 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 65536,
|
| 2987 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
| 2988 |
|
|
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
|
| 2989 |
|
|
POWER_UP_UNINITIALIZED = "false",
|
| 2990 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 2991 |
|
|
);
|
| 2992 |
|
|
address_a_sel[2..0] : WIRE;
|
| 2993 |
|
|
address_a_wire[15..0] : WIRE;
|
| 2994 |
|
|
rden_decode_addr_sel_a[2..0] : WIRE;
|
| 2995 |
|
|
w_addr_val_a4w[2..0] : WIRE;
|
| 2996 |
|
|
|
| 2997 |
|
|
BEGIN
|
| 2998 |
|
|
address_reg_a[].clk = clock0;
|
| 2999 |
|
|
address_reg_a[].d = address_a_sel[];
|
| 3000 |
|
|
out_address_reg_a[].clk = clock0;
|
| 3001 |
|
|
out_address_reg_a[].d = address_reg_a[].q;
|
| 3002 |
|
|
decode3.data[2..0] = address_a_wire[15..13];
|
| 3003 |
|
|
decode3.enable = wren_a;
|
| 3004 |
|
|
rden_decode.data[] = w_addr_val_a4w[];
|
| 3005 |
|
|
mux2.data[] = ( ram_block1a[127..0].portadataout[0..0]);
|
| 3006 |
|
|
mux2.sel[] = out_address_reg_a[].q;
|
| 3007 |
|
|
ram_block1a[127..0].clk0 = clock0;
|
| 3008 |
|
|
ram_block1a[127..0].ena0 = ( rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]);
|
| 3009 |
|
|
ram_block1a[127..0].portaaddr[] = ( address_a_wire[12..0]);
|
| 3010 |
|
|
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
| 3011 |
|
|
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
| 3012 |
|
|
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
| 3013 |
|
|
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
| 3014 |
|
|
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
| 3015 |
|
|
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
| 3016 |
|
|
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
| 3017 |
|
|
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
| 3018 |
|
|
ram_block1a[8].portadatain[] = ( data_a[8..8]);
|
| 3019 |
|
|
ram_block1a[9].portadatain[] = ( data_a[9..9]);
|
| 3020 |
|
|
ram_block1a[10].portadatain[] = ( data_a[10..10]);
|
| 3021 |
|
|
ram_block1a[11].portadatain[] = ( data_a[11..11]);
|
| 3022 |
|
|
ram_block1a[12].portadatain[] = ( data_a[12..12]);
|
| 3023 |
|
|
ram_block1a[13].portadatain[] = ( data_a[13..13]);
|
| 3024 |
|
|
ram_block1a[14].portadatain[] = ( data_a[14..14]);
|
| 3025 |
|
|
ram_block1a[15].portadatain[] = ( data_a[15..15]);
|
| 3026 |
|
|
ram_block1a[16].portadatain[] = ( data_a[0..0]);
|
| 3027 |
|
|
ram_block1a[17].portadatain[] = ( data_a[1..1]);
|
| 3028 |
|
|
ram_block1a[18].portadatain[] = ( data_a[2..2]);
|
| 3029 |
|
|
ram_block1a[19].portadatain[] = ( data_a[3..3]);
|
| 3030 |
|
|
ram_block1a[20].portadatain[] = ( data_a[4..4]);
|
| 3031 |
|
|
ram_block1a[21].portadatain[] = ( data_a[5..5]);
|
| 3032 |
|
|
ram_block1a[22].portadatain[] = ( data_a[6..6]);
|
| 3033 |
|
|
ram_block1a[23].portadatain[] = ( data_a[7..7]);
|
| 3034 |
|
|
ram_block1a[24].portadatain[] = ( data_a[8..8]);
|
| 3035 |
|
|
ram_block1a[25].portadatain[] = ( data_a[9..9]);
|
| 3036 |
|
|
ram_block1a[26].portadatain[] = ( data_a[10..10]);
|
| 3037 |
|
|
ram_block1a[27].portadatain[] = ( data_a[11..11]);
|
| 3038 |
|
|
ram_block1a[28].portadatain[] = ( data_a[12..12]);
|
| 3039 |
|
|
ram_block1a[29].portadatain[] = ( data_a[13..13]);
|
| 3040 |
|
|
ram_block1a[30].portadatain[] = ( data_a[14..14]);
|
| 3041 |
|
|
ram_block1a[31].portadatain[] = ( data_a[15..15]);
|
| 3042 |
|
|
ram_block1a[32].portadatain[] = ( data_a[0..0]);
|
| 3043 |
|
|
ram_block1a[33].portadatain[] = ( data_a[1..1]);
|
| 3044 |
|
|
ram_block1a[34].portadatain[] = ( data_a[2..2]);
|
| 3045 |
|
|
ram_block1a[35].portadatain[] = ( data_a[3..3]);
|
| 3046 |
|
|
ram_block1a[36].portadatain[] = ( data_a[4..4]);
|
| 3047 |
|
|
ram_block1a[37].portadatain[] = ( data_a[5..5]);
|
| 3048 |
|
|
ram_block1a[38].portadatain[] = ( data_a[6..6]);
|
| 3049 |
|
|
ram_block1a[39].portadatain[] = ( data_a[7..7]);
|
| 3050 |
|
|
ram_block1a[40].portadatain[] = ( data_a[8..8]);
|
| 3051 |
|
|
ram_block1a[41].portadatain[] = ( data_a[9..9]);
|
| 3052 |
|
|
ram_block1a[42].portadatain[] = ( data_a[10..10]);
|
| 3053 |
|
|
ram_block1a[43].portadatain[] = ( data_a[11..11]);
|
| 3054 |
|
|
ram_block1a[44].portadatain[] = ( data_a[12..12]);
|
| 3055 |
|
|
ram_block1a[45].portadatain[] = ( data_a[13..13]);
|
| 3056 |
|
|
ram_block1a[46].portadatain[] = ( data_a[14..14]);
|
| 3057 |
|
|
ram_block1a[47].portadatain[] = ( data_a[15..15]);
|
| 3058 |
|
|
ram_block1a[48].portadatain[] = ( data_a[0..0]);
|
| 3059 |
|
|
ram_block1a[49].portadatain[] = ( data_a[1..1]);
|
| 3060 |
|
|
ram_block1a[50].portadatain[] = ( data_a[2..2]);
|
| 3061 |
|
|
ram_block1a[51].portadatain[] = ( data_a[3..3]);
|
| 3062 |
|
|
ram_block1a[52].portadatain[] = ( data_a[4..4]);
|
| 3063 |
|
|
ram_block1a[53].portadatain[] = ( data_a[5..5]);
|
| 3064 |
|
|
ram_block1a[54].portadatain[] = ( data_a[6..6]);
|
| 3065 |
|
|
ram_block1a[55].portadatain[] = ( data_a[7..7]);
|
| 3066 |
|
|
ram_block1a[56].portadatain[] = ( data_a[8..8]);
|
| 3067 |
|
|
ram_block1a[57].portadatain[] = ( data_a[9..9]);
|
| 3068 |
|
|
ram_block1a[58].portadatain[] = ( data_a[10..10]);
|
| 3069 |
|
|
ram_block1a[59].portadatain[] = ( data_a[11..11]);
|
| 3070 |
|
|
ram_block1a[60].portadatain[] = ( data_a[12..12]);
|
| 3071 |
|
|
ram_block1a[61].portadatain[] = ( data_a[13..13]);
|
| 3072 |
|
|
ram_block1a[62].portadatain[] = ( data_a[14..14]);
|
| 3073 |
|
|
ram_block1a[63].portadatain[] = ( data_a[15..15]);
|
| 3074 |
|
|
ram_block1a[64].portadatain[] = ( data_a[0..0]);
|
| 3075 |
|
|
ram_block1a[65].portadatain[] = ( data_a[1..1]);
|
| 3076 |
|
|
ram_block1a[66].portadatain[] = ( data_a[2..2]);
|
| 3077 |
|
|
ram_block1a[67].portadatain[] = ( data_a[3..3]);
|
| 3078 |
|
|
ram_block1a[68].portadatain[] = ( data_a[4..4]);
|
| 3079 |
|
|
ram_block1a[69].portadatain[] = ( data_a[5..5]);
|
| 3080 |
|
|
ram_block1a[70].portadatain[] = ( data_a[6..6]);
|
| 3081 |
|
|
ram_block1a[71].portadatain[] = ( data_a[7..7]);
|
| 3082 |
|
|
ram_block1a[72].portadatain[] = ( data_a[8..8]);
|
| 3083 |
|
|
ram_block1a[73].portadatain[] = ( data_a[9..9]);
|
| 3084 |
|
|
ram_block1a[74].portadatain[] = ( data_a[10..10]);
|
| 3085 |
|
|
ram_block1a[75].portadatain[] = ( data_a[11..11]);
|
| 3086 |
|
|
ram_block1a[76].portadatain[] = ( data_a[12..12]);
|
| 3087 |
|
|
ram_block1a[77].portadatain[] = ( data_a[13..13]);
|
| 3088 |
|
|
ram_block1a[78].portadatain[] = ( data_a[14..14]);
|
| 3089 |
|
|
ram_block1a[79].portadatain[] = ( data_a[15..15]);
|
| 3090 |
|
|
ram_block1a[80].portadatain[] = ( data_a[0..0]);
|
| 3091 |
|
|
ram_block1a[81].portadatain[] = ( data_a[1..1]);
|
| 3092 |
|
|
ram_block1a[82].portadatain[] = ( data_a[2..2]);
|
| 3093 |
|
|
ram_block1a[83].portadatain[] = ( data_a[3..3]);
|
| 3094 |
|
|
ram_block1a[84].portadatain[] = ( data_a[4..4]);
|
| 3095 |
|
|
ram_block1a[85].portadatain[] = ( data_a[5..5]);
|
| 3096 |
|
|
ram_block1a[86].portadatain[] = ( data_a[6..6]);
|
| 3097 |
|
|
ram_block1a[87].portadatain[] = ( data_a[7..7]);
|
| 3098 |
|
|
ram_block1a[88].portadatain[] = ( data_a[8..8]);
|
| 3099 |
|
|
ram_block1a[89].portadatain[] = ( data_a[9..9]);
|
| 3100 |
|
|
ram_block1a[90].portadatain[] = ( data_a[10..10]);
|
| 3101 |
|
|
ram_block1a[91].portadatain[] = ( data_a[11..11]);
|
| 3102 |
|
|
ram_block1a[92].portadatain[] = ( data_a[12..12]);
|
| 3103 |
|
|
ram_block1a[93].portadatain[] = ( data_a[13..13]);
|
| 3104 |
|
|
ram_block1a[94].portadatain[] = ( data_a[14..14]);
|
| 3105 |
|
|
ram_block1a[95].portadatain[] = ( data_a[15..15]);
|
| 3106 |
|
|
ram_block1a[96].portadatain[] = ( data_a[0..0]);
|
| 3107 |
|
|
ram_block1a[97].portadatain[] = ( data_a[1..1]);
|
| 3108 |
|
|
ram_block1a[98].portadatain[] = ( data_a[2..2]);
|
| 3109 |
|
|
ram_block1a[99].portadatain[] = ( data_a[3..3]);
|
| 3110 |
|
|
ram_block1a[100].portadatain[] = ( data_a[4..4]);
|
| 3111 |
|
|
ram_block1a[101].portadatain[] = ( data_a[5..5]);
|
| 3112 |
|
|
ram_block1a[102].portadatain[] = ( data_a[6..6]);
|
| 3113 |
|
|
ram_block1a[103].portadatain[] = ( data_a[7..7]);
|
| 3114 |
|
|
ram_block1a[104].portadatain[] = ( data_a[8..8]);
|
| 3115 |
|
|
ram_block1a[105].portadatain[] = ( data_a[9..9]);
|
| 3116 |
|
|
ram_block1a[106].portadatain[] = ( data_a[10..10]);
|
| 3117 |
|
|
ram_block1a[107].portadatain[] = ( data_a[11..11]);
|
| 3118 |
|
|
ram_block1a[108].portadatain[] = ( data_a[12..12]);
|
| 3119 |
|
|
ram_block1a[109].portadatain[] = ( data_a[13..13]);
|
| 3120 |
|
|
ram_block1a[110].portadatain[] = ( data_a[14..14]);
|
| 3121 |
|
|
ram_block1a[111].portadatain[] = ( data_a[15..15]);
|
| 3122 |
|
|
ram_block1a[112].portadatain[] = ( data_a[0..0]);
|
| 3123 |
|
|
ram_block1a[113].portadatain[] = ( data_a[1..1]);
|
| 3124 |
|
|
ram_block1a[114].portadatain[] = ( data_a[2..2]);
|
| 3125 |
|
|
ram_block1a[115].portadatain[] = ( data_a[3..3]);
|
| 3126 |
|
|
ram_block1a[116].portadatain[] = ( data_a[4..4]);
|
| 3127 |
|
|
ram_block1a[117].portadatain[] = ( data_a[5..5]);
|
| 3128 |
|
|
ram_block1a[118].portadatain[] = ( data_a[6..6]);
|
| 3129 |
|
|
ram_block1a[119].portadatain[] = ( data_a[7..7]);
|
| 3130 |
|
|
ram_block1a[120].portadatain[] = ( data_a[8..8]);
|
| 3131 |
|
|
ram_block1a[121].portadatain[] = ( data_a[9..9]);
|
| 3132 |
|
|
ram_block1a[122].portadatain[] = ( data_a[10..10]);
|
| 3133 |
|
|
ram_block1a[123].portadatain[] = ( data_a[11..11]);
|
| 3134 |
|
|
ram_block1a[124].portadatain[] = ( data_a[12..12]);
|
| 3135 |
|
|
ram_block1a[125].portadatain[] = ( data_a[13..13]);
|
| 3136 |
|
|
ram_block1a[126].portadatain[] = ( data_a[14..14]);
|
| 3137 |
|
|
ram_block1a[127].portadatain[] = ( data_a[15..15]);
|
| 3138 |
|
|
ram_block1a[127..0].portare = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";
|
| 3139 |
|
|
ram_block1a[127..0].portawe = ( decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
|
| 3140 |
|
|
address_a_sel[2..0] = address_a[15..13];
|
| 3141 |
|
|
address_a_wire[] = address_a[];
|
| 3142 |
|
|
q_a[] = mux2.result[];
|
| 3143 |
|
|
rden_decode_addr_sel_a[2..0] = address_a_wire[15..13];
|
| 3144 |
|
|
w_addr_val_a4w[] = rden_decode_addr_sel_a[];
|
| 3145 |
|
|
END;
|
| 3146 |
|
|
--VALID FILE
|
