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lucas.vbal |
--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=3 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
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--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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--synthesis_resources =
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SUBDESIGN cmpr_pgc
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(
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aeb : output;
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dataa[2..0] : input;
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datab[2..0] : input;
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)
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VARIABLE
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aeb_result_wire[0..0] : WIRE;
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aneb_result_wire[0..0] : WIRE;
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data_wire[7..0] : WIRE;
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eq_wire : WIRE;
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BEGIN
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aeb = eq_wire;
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aeb_result_wire[] = (! aneb_result_wire[]);
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aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
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data_wire[] = ( datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[6..6] $ data_wire[7..7]), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5])));
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eq_wire = aeb_result_wire[];
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END;
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--VALID FILE
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