OpenCores
URL https://opencores.org/ocsvn/2d_game_console/2d_game_console/trunk

Subversion Repositories 2d_game_console

[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [decode_k8a.tdf] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 lucas.vbal
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=8 LPM_WIDTH=3 data eq
2
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ  VERSION_END
3
 
4
 
5
-- Copyright (C) 2017  Intel Corporation. All rights reserved.
6
--  Your use of Intel Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Intel Program License
12
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
13
--  the Intel MegaCore Function License Agreement, or other
14
--  applicable license agreement, including, without limitation,
15
--  that your use is for the sole purpose of programming logic
16
--  devices manufactured by Intel and sold by Intel or its
17
--  authorized distributors.  Please refer to the applicable
18
--  agreement for further details.
19
 
20
 
21
 
22
--synthesis_resources = lut 8
23
SUBDESIGN decode_k8a
24
(
25
        data[2..0]      :       input;
26
        eq[7..0]        :       output;
27
)
28
VARIABLE
29
        data_wire[2..0] : WIRE;
30
        eq_node[7..0]   : WIRE;
31
        eq_wire[7..0]   : WIRE;
32
        w_anode1046w[3..0]      : WIRE;
33
        w_anode1064w[3..0]      : WIRE;
34
        w_anode1075w[3..0]      : WIRE;
35
        w_anode1086w[3..0]      : WIRE;
36
        w_anode1097w[3..0]      : WIRE;
37
        w_anode1108w[3..0]      : WIRE;
38
        w_anode1119w[3..0]      : WIRE;
39
        w_anode1130w[3..0]      : WIRE;
40
 
41
BEGIN
42
        data_wire[] = data[];
43
        eq[] = eq_node[];
44
        eq_node[7..0] = eq_wire[7..0];
45
        eq_wire[] = ( w_anode1130w[3..3], w_anode1119w[3..3], w_anode1108w[3..3], w_anode1097w[3..3], w_anode1086w[3..3], w_anode1075w[3..3], w_anode1064w[3..3], w_anode1046w[3..3]);
46
        w_anode1046w[] = ( (w_anode1046w[2..2] & (! data_wire[2..2])), (w_anode1046w[1..1] & (! data_wire[1..1])), (w_anode1046w[0..0] & (! data_wire[0..0])), B"1");
47
        w_anode1064w[] = ( (w_anode1064w[2..2] & (! data_wire[2..2])), (w_anode1064w[1..1] & (! data_wire[1..1])), (w_anode1064w[0..0] & data_wire[0..0]), B"1");
48
        w_anode1075w[] = ( (w_anode1075w[2..2] & (! data_wire[2..2])), (w_anode1075w[1..1] & data_wire[1..1]), (w_anode1075w[0..0] & (! data_wire[0..0])), B"1");
49
        w_anode1086w[] = ( (w_anode1086w[2..2] & (! data_wire[2..2])), (w_anode1086w[1..1] & data_wire[1..1]), (w_anode1086w[0..0] & data_wire[0..0]), B"1");
50
        w_anode1097w[] = ( (w_anode1097w[2..2] & data_wire[2..2]), (w_anode1097w[1..1] & (! data_wire[1..1])), (w_anode1097w[0..0] & (! data_wire[0..0])), B"1");
51
        w_anode1108w[] = ( (w_anode1108w[2..2] & data_wire[2..2]), (w_anode1108w[1..1] & (! data_wire[1..1])), (w_anode1108w[0..0] & data_wire[0..0]), B"1");
52
        w_anode1119w[] = ( (w_anode1119w[2..2] & data_wire[2..2]), (w_anode1119w[1..1] & data_wire[1..1]), (w_anode1119w[0..0] & (! data_wire[0..0])), B"1");
53
        w_anode1130w[] = ( (w_anode1130w[2..2] & data_wire[2..2]), (w_anode1130w[1..1] & data_wire[1..1]), (w_anode1130w[0..0] & data_wire[0..0]), B"1");
54
END;
55
--VALID FILE

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.