Subversion Repositories 2d_game_console

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=8 LPM_WIDTH=3 data enable eq

--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ  VERSION_END

-- Copyright (C) 2017  Intel Corporation. All rights reserved.

--  Your use of Intel Corporation's design tools, logic functions

--  and other software and tools, and its AMPP partner logic

--  functions, and any output files from any of the foregoing

--  (including device programming or simulation files), and any

--  associated documentation or information are expressly subject

--  to the terms and conditions of the Intel Program License

--  Subscription Agreement, the Intel Quartus Prime License Agreement,

--  the Intel MegaCore Function License Agreement, or other

--  applicable license agreement, including, without limitation,

--  that your use is for the sole purpose of programming logic

--  devices manufactured by Intel and sold by Intel or its

--  authorized distributors.  Please refer to the applicable

--  agreement for further details.

--synthesis_resources = lut 8

SUBDESIGN decode_rsa

(

        data[2..0]      :       input;

        enable  :       input;

        eq[7..0]        :       output;

)

VARIABLE

        data_wire[2..0] : WIRE;

        enable_wire     : WIRE;

        eq_node[7..0]   : WIRE;

        eq_wire[7..0]   : WIRE;

        w_anode823w[3..0]       : WIRE;

        w_anode840w[3..0]       : WIRE;

        w_anode850w[3..0]       : WIRE;

        w_anode860w[3..0]       : WIRE;

        w_anode870w[3..0]       : WIRE;

        w_anode880w[3..0]       : WIRE;

        w_anode890w[3..0]       : WIRE;

        w_anode900w[3..0]       : WIRE;

BEGIN

        data_wire[] = data[];

        enable_wire = enable;

        eq[] = eq_node[];

        eq_node[7..0] = eq_wire[7..0];

        eq_wire[] = ( w_anode900w[3..3], w_anode890w[3..3], w_anode880w[3..3], w_anode870w[3..3], w_anode860w[3..3], w_anode850w[3..3], w_anode840w[3..3], w_anode823w[3..3]);

        w_anode823w[] = ( (w_anode823w[2..2] & (! data_wire[2..2])), (w_anode823w[1..1] & (! data_wire[1..1])), (w_anode823w[0..0] & (! data_wire[0..0])), enable_wire);

        w_anode840w[] = ( (w_anode840w[2..2] & (! data_wire[2..2])), (w_anode840w[1..1] & (! data_wire[1..1])), (w_anode840w[0..0] & data_wire[0..0]), enable_wire);

        w_anode850w[] = ( (w_anode850w[2..2] & (! data_wire[2..2])), (w_anode850w[1..1] & data_wire[1..1]), (w_anode850w[0..0] & (! data_wire[0..0])), enable_wire);

        w_anode860w[] = ( (w_anode860w[2..2] & (! data_wire[2..2])), (w_anode860w[1..1] & data_wire[1..1]), (w_anode860w[0..0] & data_wire[0..0]), enable_wire);

        w_anode870w[] = ( (w_anode870w[2..2] & data_wire[2..2]), (w_anode870w[1..1] & (! data_wire[1..1])), (w_anode870w[0..0] & (! data_wire[0..0])), enable_wire);

        w_anode880w[] = ( (w_anode880w[2..2] & data_wire[2..2]), (w_anode880w[1..1] & (! data_wire[1..1])), (w_anode880w[0..0] & data_wire[0..0]), enable_wire);

        w_anode890w[] = ( (w_anode890w[2..2] & data_wire[2..2]), (w_anode890w[1..1] & data_wire[1..1]), (w_anode890w[0..0] & (! data_wire[0..0])), enable_wire);

        w_anode900w[] = ( (w_anode900w[2..2] & data_wire[2..2]), (w_anode900w[1..1] & data_wire[1..1]), (w_anode900w[0..0] & data_wire[0..0]), enable_wire);

END;

--VALID FILE