Subversion Repositories 2d_game_console

--sign_div_unsign DEN_REPRESENTATION="SIGNED" DEN_WIDTH=16 LPM_PIPELINE=2 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" NUM_WIDTH=16 SKIP_BITS=0 clock denominator numerator quotient remainder

--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_abs 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_divide 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END

-- Copyright (C) 2017  Intel Corporation. All rights reserved.

--  Your use of Intel Corporation's design tools, logic functions

--  and other software and tools, and its AMPP partner logic

--  functions, and any output files from any of the foregoing

--  (including device programming or simulation files), and any

--  associated documentation or information are expressly subject

--  to the terms and conditions of the Intel Program License

--  Subscription Agreement, the Intel Quartus Prime License Agreement,

--  the Intel MegaCore Function License Agreement, or other

--  applicable license agreement, including, without limitation,

--  that your use is for the sole purpose of programming logic

--  devices manufactured by Intel and sold by Intel or its

--  authorized distributors.  Please refer to the applicable

--  agreement for further details.

FUNCTION alt_u_div_akg (clock, denominator[15..0], numerator[15..0])

RETURNS ( den_out[15..0], quotient[15..0], remainder[15..0]);

--synthesis_resources = lut 196 reg 132

SUBDESIGN sign_div_unsign_lqh

(

        clock   :       input;

        denominator[15..0]      :       input;

        numerator[15..0]        :       input;

        quotient[15..0] :       output;

        remainder[15..0]        :       output;

)

VARIABLE

        divider : alt_u_div_akg;

        DFF_Num_Sign[1..0] : dffe;

        DFF_q_is_neg[1..0] : dffe;

        adder_result_int[16..0] :       WIRE;

        adder_cin       :       WIRE;

        adder_dataa[15..0]      :       WIRE;

        adder_datab[15..0]      :       WIRE;

        adder_result[15..0]     :       WIRE;

        compl_adder1_result_int[16..0]  :       WIRE;

        compl_adder1_cin        :       WIRE;

        compl_adder1_dataa[15..0]       :       WIRE;

        compl_adder1_datab[15..0]       :       WIRE;

        compl_adder1_result[15..0]      :       WIRE;

        compl_adder_2_result_int[16..0] :       WIRE;

        compl_adder_2_cin       :       WIRE;

        compl_adder_2_dataa[15..0]      :       WIRE;

        compl_adder_2_datab[15..0]      :       WIRE;

        compl_adder_2_result[15..0]     :       WIRE;

        aclr    : NODE;

        adder_out[15..0]        : WIRE;

        clken   : NODE;

        den_choice[15..0]       : WIRE;

        gnd_wire        : WIRE;

        neg_num[15..0]  : WIRE;

        neg_quot[15..0] : WIRE;

        norm_num[15..0] : WIRE;

        num_choice[15..0]       : WIRE;

        pre_neg_den[15..0]      : WIRE;

        pre_neg_quot[15..0]     : WIRE;

        pre_quot[15..0] : WIRE;

        protect_quotient[15..0] : WIRE;

        protect_remainder[15..0]        : WIRE;

        q_is_neg        : WIRE;

        vcc_wire        : WIRE;

        zero_wire[15..0]        : WIRE;

        zero_wire_2w[15..0]     : WIRE;

BEGIN

        divider.clock = clock;

        divider.denominator[] = den_choice[];

        divider.numerator[] = norm_num[];

        DFF_Num_Sign[].clk = clock;

        DFF_Num_Sign[].clrn = (! aclr);

        DFF_Num_Sign[].d = ( num_choice[15..15], DFF_Num_Sign[1].q);

        DFF_Num_Sign[].ena = clken;

        DFF_q_is_neg[].clk = clock;

        DFF_q_is_neg[].clrn = (! aclr);

        DFF_q_is_neg[].d = ( q_is_neg, DFF_q_is_neg[1].q);

        DFF_q_is_neg[].ena = clken;

        adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);

        adder_result[] = adder_result_int[16..1];

        adder_cin = gnd_wire;

        adder_dataa[] = divider.den_out[];

        adder_datab[] = protect_remainder[];

        compl_adder1_result_int[] = (compl_adder1_dataa[], compl_adder1_cin) + (compl_adder1_datab[], compl_adder1_cin);

        compl_adder1_result[] = compl_adder1_result_int[16..1];

        compl_adder1_cin = vcc_wire;

        compl_adder1_dataa[] = (! denominator[]);

        compl_adder1_datab[] = zero_wire[];

        compl_adder_2_result_int[] = (compl_adder_2_dataa[], compl_adder_2_cin) + (compl_adder_2_datab[], compl_adder_2_cin);

        compl_adder_2_result[] = compl_adder_2_result_int[16..1];

        compl_adder_2_cin = vcc_wire;

        compl_adder_2_dataa[] = (! pre_quot[]);

        compl_adder_2_datab[] = zero_wire_2w[];

        aclr = GND;

        adder_out[] = adder_result[];

        clken = VCC;

        den_choice[] = ((denominator[] & (! denominator[15..15])) # (pre_neg_den[] & denominator[15..15]));

        gnd_wire = B"0";

        neg_num[] = (! num_choice[]);

        neg_quot[] = (! protect_quotient[]);

        norm_num[] = ((num_choice[] & (! num_choice[15..15])) # (neg_num[] & num_choice[15..15]));

        num_choice[] = numerator[];

        pre_neg_den[] = compl_adder1_result[];

        pre_neg_quot[] = compl_adder_2_result[];

        pre_quot[] = ((protect_quotient[] & (! DFF_Num_Sign[0].q)) # (neg_quot[] & DFF_Num_Sign[0].q));

        protect_quotient[] = divider.quotient[];

        protect_remainder[] = divider.remainder[];

        q_is_neg = denominator[15..15];

        quotient[] = ((pre_quot[] & (! DFF_q_is_neg[0].q)) # (pre_neg_quot[] & DFF_q_is_neg[0].q));

        remainder[] = ((protect_remainder[] & (! DFF_Num_Sign[0].q)) # (adder_out[] & DFF_Num_Sign[0].q));

        vcc_wire = B"1";

        zero_wire[] = B"0000000000000000";

        zero_wire_2w[] = B"0000000000000000";

END;

--VALID FILE