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lucas.vbal |
--sign_div_unsign DEN_REPRESENTATION="SIGNED" DEN_WIDTH=16 LPM_PIPELINE=3 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" NUM_WIDTH=16 SKIP_BITS=0 clock denominator numerator quotient remainder
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--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_abs 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_divide 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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FUNCTION alt_u_div_bkg (clock, denominator[15..0], numerator[15..0])
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RETURNS ( den_out[15..0], quotient[15..0], remainder[15..0]);
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--synthesis_resources = lut 196 reg 198
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SUBDESIGN sign_div_unsign_mqh
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(
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clock : input;
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denominator[15..0] : input;
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numerator[15..0] : input;
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quotient[15..0] : output;
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remainder[15..0] : output;
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)
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VARIABLE
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divider : alt_u_div_bkg;
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DFF_Num_Sign[2..0] : dffe;
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DFF_q_is_neg[2..0] : dffe;
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adder_result_int[16..0] : WIRE;
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adder_cin : WIRE;
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adder_dataa[15..0] : WIRE;
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adder_datab[15..0] : WIRE;
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adder_result[15..0] : WIRE;
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compl_adder1_result_int[16..0] : WIRE;
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compl_adder1_cin : WIRE;
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compl_adder1_dataa[15..0] : WIRE;
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compl_adder1_datab[15..0] : WIRE;
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compl_adder1_result[15..0] : WIRE;
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compl_adder_2_result_int[16..0] : WIRE;
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compl_adder_2_cin : WIRE;
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compl_adder_2_dataa[15..0] : WIRE;
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compl_adder_2_datab[15..0] : WIRE;
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compl_adder_2_result[15..0] : WIRE;
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aclr : NODE;
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adder_out[15..0] : WIRE;
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clken : NODE;
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den_choice[15..0] : WIRE;
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gnd_wire : WIRE;
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neg_num[15..0] : WIRE;
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neg_quot[15..0] : WIRE;
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norm_num[15..0] : WIRE;
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num_choice[15..0] : WIRE;
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pre_neg_den[15..0] : WIRE;
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pre_neg_quot[15..0] : WIRE;
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pre_quot[15..0] : WIRE;
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protect_quotient[15..0] : WIRE;
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protect_remainder[15..0] : WIRE;
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q_is_neg : WIRE;
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vcc_wire : WIRE;
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zero_wire[15..0] : WIRE;
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zero_wire_2w[15..0] : WIRE;
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BEGIN
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divider.clock = clock;
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divider.denominator[] = den_choice[];
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divider.numerator[] = norm_num[];
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DFF_Num_Sign[].clk = clock;
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DFF_Num_Sign[].clrn = (! aclr);
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DFF_Num_Sign[].d = ( num_choice[15..15], DFF_Num_Sign[2..1].q);
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DFF_Num_Sign[].ena = clken;
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DFF_q_is_neg[].clk = clock;
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DFF_q_is_neg[].clrn = (! aclr);
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DFF_q_is_neg[].d = ( q_is_neg, DFF_q_is_neg[2..1].q);
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DFF_q_is_neg[].ena = clken;
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adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);
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adder_result[] = adder_result_int[16..1];
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adder_cin = gnd_wire;
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adder_dataa[] = divider.den_out[];
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adder_datab[] = protect_remainder[];
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compl_adder1_result_int[] = (compl_adder1_dataa[], compl_adder1_cin) + (compl_adder1_datab[], compl_adder1_cin);
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compl_adder1_result[] = compl_adder1_result_int[16..1];
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compl_adder1_cin = vcc_wire;
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compl_adder1_dataa[] = (! denominator[]);
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compl_adder1_datab[] = zero_wire[];
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compl_adder_2_result_int[] = (compl_adder_2_dataa[], compl_adder_2_cin) + (compl_adder_2_datab[], compl_adder_2_cin);
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compl_adder_2_result[] = compl_adder_2_result_int[16..1];
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compl_adder_2_cin = vcc_wire;
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compl_adder_2_dataa[] = (! pre_quot[]);
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compl_adder_2_datab[] = zero_wire_2w[];
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aclr = GND;
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adder_out[] = adder_result[];
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clken = VCC;
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den_choice[] = ((denominator[] & (! denominator[15..15])) # (pre_neg_den[] & denominator[15..15]));
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gnd_wire = B"0";
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neg_num[] = (! num_choice[]);
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neg_quot[] = (! protect_quotient[]);
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norm_num[] = ((num_choice[] & (! num_choice[15..15])) # (neg_num[] & num_choice[15..15]));
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num_choice[] = numerator[];
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pre_neg_den[] = compl_adder1_result[];
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pre_neg_quot[] = compl_adder_2_result[];
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pre_quot[] = ((protect_quotient[] & (! DFF_Num_Sign[0].q)) # (neg_quot[] & DFF_Num_Sign[0].q));
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protect_quotient[] = divider.quotient[];
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protect_remainder[] = divider.remainder[];
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q_is_neg = denominator[15..15];
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quotient[] = ((pre_quot[] & (! DFF_q_is_neg[0].q)) # (pre_neg_quot[] & DFF_q_is_neg[0].q));
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remainder[] = ((protect_remainder[] & (! DFF_Num_Sign[0].q)) # (adder_out[] & DFF_Num_Sign[0].q));
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vcc_wire = B"1";
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zero_wire[] = B"0000000000000000";
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zero_wire_2w[] = B"0000000000000000";
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END;
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--VALID FILE
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