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--ECE395 GPU:
--Top Level HDL
--=====================================================
--Designed by:
--Zuofu Cheng
--James Cavanaugh
--Eric Sands
--
--of the University of Illinois at Urbana Champaign
--under the direction of Dr. Lippold Haken
--====================================================
--
--Heavily based off of HDL examples provided by XESS Corporation
--www.xess.com
--
--Based in part on Doug Hodson's work which in turn
--was based off of the XSOC from Gray Research LLC.
--                                                                              
--
--release under the GNU General Public License
--and kindly hosted by www.opencores.org
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.xsasdram.all;
use WORK.sdram.all;
use WORK.vga_pckg.all;
use WORK.blitter_pckg.all;
 
entity gpuChip is
 
        generic(
      FREQ            :       natural                       := 50_000;  -- frequency of operation in KHz
      PIPE_EN         :       boolean                       := true;  -- enable fast, pipelined SDRAM operation
      MULTIPLE_ACTIVE_ROWS:   boolean                                                           := true;  -- if true, allow an active row in each bank
                CLK_DIV         :       real                                                               := 1.0;  -- SDRAM Clock div
                NROWS           :       natural                       := 4096;  -- number of rows in the SDRAM
      NCOLS           :       natural                       := 256;  -- number of columns in each SDRAM row
        SADDR_WIDTH      :              natural                                                         := 12;
                DATA_WIDTH      :       natural                                                                 := 16;  -- SDRAM databus width
                ADDR_WIDTH      :       natural                                                                 := 23;  -- host-side address width
                VGA_CLK_DIV     :       natural                                                                 := 4;  -- pixel clock = FREQ / CLK_DIV
        PIXEL_WIDTH     :       natural                                                                 := 8;  -- width of a pixel in memory
        NUM_RGB_BITS    :       natural                                                                 := 2;  -- #bits in each R,G,B component of a pixel
        PIXELS_PER_LINE :       natural                                                                 := 320; -- width of image in pixels
        LINES_PER_FRAME :       natural                                                                 := 240;  -- height of image in scanlines
        FIT_TO_SCREEN   :       boolean                                                                 := true;  -- adapt video timing to fit image width x             
           PORT_TIME_SLOTS :       std_logic_vector(15 downto 0) := "0000111111111111"
   );
 
        port(
                pin_clkin   : in std_logic;       -- main clock input from external clock source
                pin_ce_n    : out std_logic;      -- Flash RAM chip-enable
                pin_pushbtn : in std_logic;
 
                -- vga port connections
                pin_red     : out std_logic_vector(1 downto 0);
                pin_green   : out std_logic_vector(1 downto 0);
                pin_blue    : out std_logic_vector(1 downto 0);
                pin_hsync_n : out std_logic;
                pin_vsync_n : out std_logic;
 
                -- SDRAM pin connections
                pin_sclkfb : in std_logic;                   -- feedback SDRAM clock with PCB delays
                pin_sclk   : out std_logic;                  -- clock to SDRAM
                pin_cke    : out std_logic;                  -- SDRAM clock-enable
                pin_cs_n   : out std_logic;                  -- SDRAM chip-select
                pin_ras_n  : out std_logic;                  -- SDRAM RAS
                pin_cas_n  : out std_logic;                  -- SDRAM CAS
                pin_we_n   : out std_logic;                  -- SDRAM write-enable
                pin_ba     : out std_logic_vector( 1 downto 0);      -- SDRAM bank-address
                pin_sAddr  : out std_logic_vector(11 downto 0);      -- SDRAM address bus
                pin_sData  : inout std_logic_vector (16-1 downto 0);  -- data bus to SDRAM
                pin_dqmh   : out std_logic;                  -- SDRAM DQMH
                pin_dqml   : out std_logic                   -- SDRAM DQML                      
        );
end gpuChip;
 
architecture arch of gpuChip is
 
        constant YES:   std_logic := '1';
        constant NO:    std_logic := '0';
        constant HI:    std_logic := '1';
        constant LO:    std_logic := '0';
 
        type gpuState is (
         INIT,                           -- init
    INIT_BKG,
         DRAW_BKG,
         BLIT_REST,
    INIT_SPRITE,
         DRAW_SPRITE,
         UPDATE
         );
 
        signal state_r, state_x : gpuState;  -- state register and next state
 
        --registers
        signal plane0_dest_r, plane0_dest_x             : std_logic_vector (ADDR_WIDTH - 1 downto 0);  -- sprite dest register
        signal plane0_ypos_r, plane0_ypos_x                     : std_logic_vector (11 downto 0);
        signal delay_r, delay_x                                                 : std_logic_vector (19 downto 0);                                  --20 bit counter for delay
        signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
        signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
        signal line_size_x, line_size_r                                 : std_logic_vector (11 downto 0);
        signal source_lines_x, source_lines_r           : std_logic_vector (15 downto 0);
        signal alphaOp_x, alphaOp_r                                     : std_logic;
        signal front_buffer_x, front_buffer_r           : std_logic;
 
        --internal signals
   signal sysReset                                                                              : std_logic;  -- system reset
        signal blit_reset                                                                               : std_logic;
        signal reset_blitter                                                                    : std_logic;
 
        -- Blitter signals
        signal blit_begin                                                                               : std_logic;
        signal source_address                                       : std_logic_vector(ADDR_WIDTH-1 downto 0);
        signal source_lines                                                                     : std_logic_vector (15 downto 0);
        signal line_size                                                                                : std_logic_vector (11 downto 0);
        signal target_address                                                           : std_logic_vector(ADDR_WIDTH-1 downto 0);
        signal blit_done                                                                                : std_logic;
        signal alphaOp                                                                                  : std_logic;
        signal front_buffer                                                                     : std_logic;
 
         --Application Side Signals for the DualPort Controller
        signal rst_i                                                                                    : std_logic;    --tied reset signal
   signal opBegun0, opBegun1                       : std_logic;  -- read/write operation started indicator
   signal earlyOpBegun0, earlyOpBegun1          : std_logic;  -- read/write operation started indicator
   signal rdPending0, rdPending1                                           : std_logic;  -- read operation pending in SDRAM pipeline indicator
   signal done0, done1                               : std_logic;  -- read/write operation complete indicator
   signal rdDone0, rdDone1                                     : std_logic;  -- read operation complete indicator
   signal hAddr0, hAddr1                                 : std_logic_vector(ADDR_WIDTH-1 downto 0);  -- host-side address bus
   signal hDIn0, hDIn1                                    : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
   signal hDOut0, hDOut1                                                      : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
   signal rd0, rd1                                      : std_logic;  -- host-side read control signal
   signal wr0, wr1                              : std_logic;  -- host-side write control signal
 
        -- SDRAM host side signals
        signal sdram_bufclk                                                                     : std_logic;    -- buffered input (non-DLL) clock
        signal sdram_clk1x                                                                      : std_logic;    -- internal master clock signal
        signal sdram_clk2x                                                                      : std_logic;            -- doubled clock
        signal sdram_lock                                                                       : std_logic;    -- SDRAM clock DLL lock indicator
        signal sdram_rst                                                                        : std_logic;    -- internal reset signal
        signal sdram_rd                                                                         : std_logic;    -- host-side read control signal
        signal sdram_wr                                                                         : std_logic;    -- host-side write control signal
        signal sdram_earlyOpBegun                                                       : std_logic;
        signal sdram_OpBegun                                                                    : std_logic;
        signal sdram_rdPending                                                          : std_logic;
        signal sdram_done                                                                       : std_logic;    -- SDRAM operation complete indicator
        signal sdram_rdDone                                                                     : std_logic;            -- host-side read completed signal
        signal sdram_hAddr                                                                      : std_logic_vector(ADDR_WIDTH -1 downto 0);  -- host address bus
        signal sdram_hDIn                                                                       : std_logic_vector(DATA_WIDTH -1 downto 0);      -- host-side data to SDRAM
        signal sdram_hDOut                                                                      : std_logic_vector(DATA_WIDTH -1 downto 0);      -- host-side data from SDRAM
        signal sdram_status                                                                     : std_logic_vector(3 downto 0);  -- SDRAM controller status
 
 
        -- VGA related signals
        signal eof                                                                              : std_logic;      -- end-of-frame signal from VGA controller
   signal full                                                                                          : std_logic;      -- indicates when the VGA pixel buffer is full
   signal vga_address                                                           : unsigned(ADDR_WIDTH-1 downto 0);  -- SDRAM address counter 
        signal pixels                                                                                   : std_logic_vector(DATA_WIDTH-1 downto 0);
        signal rst_n                                                                                    : std_logic;            --VGA reset (active low)
        signal drawframe                                                                                : std_logic;  -- flag to indicate whether we are drawing current frame  
 
--------------------------------------------------------------------------------------------------------------
-- Beginning of Submodules
-- All instances of submodules and signals associated with them
-- are declared within. Signals not directly associated with
-- submodules are declared elsewhere.
--  
--------------------------------------------------------------------------------------------------------------
 
begin
 ------------------------------------------------------------------------
 -- Instantiate the dualport module
 ------------------------------------------------------------------------
  u1 : dualport
    generic map(
      PIPE_EN         => PIPE_EN,
      PORT_TIME_SLOTS => PORT_TIME_SLOTS,
      DATA_WIDTH      => DATA_WIDTH,
      HADDR_WIDTH     => ADDR_WIDTH
      )
    port map(
      clk             => sdram_clk1x,
 
                -- Memory Port 0 connections
                rst0            => rst_i,
      rd0             => rd0,
      wr0             => wr0,
      rdPending0      => rdPending0,
      opBegun0        => opBegun0,
      earlyOpBegun0   => earlyOpBegun0,
      rdDone0         => rdDone0,
      done0           => done0,
      hAddr0          => hAddr0,
      hDIn0           => hDIn0,
      hDOut0          => hDOut0,
      status0         => open,
 
                -- Memory Port 1 connections
      rst1            => rst_i,
      rd1             => rd1,
      wr1             => wr1,
      rdPending1      => rdPending1,
      opBegun1        => opBegun1,
      earlyOpBegun1   => earlyOpBegun1,
      rdDone1         => rdDone1,
      done1           => done1,
      hAddr1          => hAddr1,
      hDIn1           => hDIn1,
      hDOut1          => hDOut1,
      status1         => open,
 
                -- connections to the SDRAM controller
      rst             => sdram_rst,
      rd              => sdram_rd,
      wr              => sdram_wr,
      rdPending       => sdram_rdPending,
      opBegun         => sdram_opBegun,
      earlyOpBegun    => sdram_earlyOpBegun,
      rdDone          => sdram_rdDone,
      done            => sdram_done,
      hAddr           => sdram_hAddr,
      hDIn            => sdram_hDIn,
      hDOut           => sdram_hDOut,
      status          => sdram_status
      );
 
 
  ------------------------------------------------------------------------
  -- Instantiate the SDRAM controller that connects to the dualport
  -- module and interfaces to the external SDRAM chip.
  ------------------------------------------------------------------------
  u2 : xsaSDRAMCntl
    generic map(
      FREQ                                        => FREQ,
      CLK_DIV                                     => CLK_DIV,
      PIPE_EN                        => PIPE_EN,
      MULTIPLE_ACTIVE_ROWS   => MULTIPLE_ACTIVE_ROWS,
                DATA_WIDTH                        => DATA_WIDTH,
      NROWS                               => NROWS,
      NCOLS                               => NCOLS,
      HADDR_WIDTH                         => ADDR_WIDTH,
      SADDR_WIDTH                         => SADDR_WIDTH
      )
    port map(
                --Dual Port Controller (Host) Side
      clk          => pin_clkin,             -- master clock from external clock source (unbuffered)
      bufclk       => sdram_bufclk,                -- buffered master clock output
      clk1x        => sdram_clk1x,                 -- synchronized master clock (accounts for delays to external SDRAM)
      clk2x        => sdram_clk2x,              -- synchronized doubled master clock
      lock         => sdram_lock,                       -- DLL lock indicator
      rst          => sdram_rst,                        -- reset
      rd           => sdram_rd,                         -- host-side SDRAM read control from dualport
      wr           => sdram_wr,                         -- host-side SDRAM write control from dualport
      earlyOpBegun => sdram_earlyOpBegun,               -- early indicator that memory operation has begun 
                opBegun      => sdram_opBegun,          -- indicates memory read/write has begun
                rdPending    => sdram_rdPending,                -- read operation to SDRAM is in progress
      done         => sdram_done,                       -- indicates SDRAM memory read or write operation is done
      rdDone       => sdram_rdDone,                     -- indicates SDRAM memory read operation is done
      hAddr        => sdram_hAddr,           -- host-side address from dualport to SDRAM
      hDIn         => sdram_hDIn,            -- test data pattern from dualport to SDRAM
      hDOut        => sdram_hDOut,           -- SDRAM data output to dualport
      status       => sdram_status,          -- SDRAM controller state (for diagnostics)
 
           --SDRAM (External) Side
                sclkfb       => pin_sclkfb,           -- clock feedback with added external PCB delays
      sclk         => pin_sclk,             -- synchronized clock to external SDRAM
      cke          => pin_cke,              -- SDRAM clock enable
      cs_n         => pin_cs_n,             -- SDRAM chip-select
      ras_n        => pin_ras_n,            -- SDRAM RAS
      cas_n        => pin_cas_n,            -- SDRAM CAS
      we_n         => pin_we_n,             -- SDRAM write-enable
      ba           => pin_ba,               -- SDRAM bank address
      sAddr        => pin_sAddr,            -- SDRAM address
      sData        => pin_sData,            -- SDRAM databus
      dqmh         => pin_dqmh,             -- SDRAM DQMH
      dqml         => pin_dqml              -- SDRAM DQML
      );
 
------------------------------------------------------------------------------------------------------------
-- Instance of VGA driver, this unit generates the video signals from VRAM
------------------------------------------------------------------------------------------------------------
 
 
        u3 : vga
    generic map (
      FREQ            => FREQ,
      CLK_DIV         => VGA_CLK_DIV,
      PIXEL_WIDTH     => PIXEL_WIDTH,
      PIXELS_PER_LINE => PIXELS_PER_LINE,
      LINES_PER_FRAME => LINES_PER_FRAME,
      NUM_RGB_BITS    => NUM_RGB_BITS,
      FIT_TO_SCREEN   => FIT_TO_SCREEN
      )
    port map (
      rst             => rst_i,
      clk             => sdram_clk1x,   -- use the resync'ed master clock so VGA generator is in sync with SDRAM
      wr              => rdDone0,       -- write to pixel buffer when the data read from SDRAM is available
      pixel_data_in   => pixels,                 -- pixel data from SDRAM
      full            => full,          -- indicates when the pixel buffer is full
      eof             => eof,           -- indicates when the VGA generator has finished a video frame
      r               => pin_red,       -- RGB components (output)
      g               => pin_green,
      b               => pin_blue,
      hsync_n         => pin_hsync_n,   -- horizontal sync
      vsync_n         => pin_vsync_n,   -- vertical sync
      blank           => open
      );
 
------------------------------------------------------------------------------------------------------------
-- instance of main blitter
------------------------------------------------------------------------------------------------------------
 
        u4: Blitter
        generic map(
    FREQ                => FREQ,
    PIPE_EN       => PIPE_EN,
         DATA_WIDTH    => DATA_WIDTH,
    ADDR_WIDTH    => ADDR_WIDTH
    )
  port map (
    clk                          =>sdram_clk1x,
         rst                             =>blit_reset,
         rd             =>rd1,
    wr             =>wr1,
    opBegun        =>opBegun1,
    earlyopBegun   =>earlyOpBegun1,
    done           =>done1,
         rddone                  =>rddone1,
    rdPending            =>rdPending1,
         Addr           =>hAddr1,
    DIn            =>hDIn1,
    DOut           =>hDOut1,
         blit_begin              =>blit_begin,
         source_address =>source_address,
         source_lines    =>source_lines,
         target_address =>target_address,
         line_size               =>line_size,
         alphaOp                         =>alphaOp,
         blit_done               =>blit_done,
         front_buffer    =>front_buffer
         );
 
--------------------------------------------------------------------------------------------------------------
-- End of Submodules
--------------------------------------------------------------------------------------------------------------
-- Begin Top Level Module
 
        -- connect internal signals     
        rst_i <= sysReset;
        pin_ce_n <= '1';                                                  -- disable Flash RAM
 
        rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
        hDIn0 <= "0000000000000000";              -- don't need to write to port 0 (VGA Port)
        wr0 <= '0';
        hAddr0 <= std_logic_vector(vga_address);
 
        blit_reset <= rst_i or reset_blitter;
 
        -- Port0 is reserved for VGA
        pixels <= hDOut0 when drawframe = '1' else "0000000000000000";
 
        source_address  <= source_address_r;
        line_size               <= line_size_r;
        target_address  <= target_address_r;
        source_lines    <= source_lines_r;
        alphaOp                 <= alphaOp_r;
        front_buffer    <= YES;--front_buffer_r;        
 
        comb:process(state_r, delay_r, plane0_dest_r)
        begin
                blit_begin <= NO;                                               --default operations            
                reset_blitter <= NO;
 
                state_x                                 <= state_r;                                     --default register values
                delay_x                         <= delay_r + 1;
           source_address_x     <= source_address_r;
                line_size_x             <= line_size_r;
                target_address_x        <= target_address_r;
                source_lines_x          <= source_lines_r;
                alphaOp_x                       <= alphaOp_r;
                plane0_dest_x           <= plane0_dest_r;
                plane0_ypos_x           <= plane0_ypos_r;
                front_buffer_x  <= front_buffer_r;
 
                case state_r is
                        when INIT =>
                                blit_begin <= NO;
                                reset_blitter <= YES;
                                state_x <= INIT_BKG;
                                plane0_dest_x <= x"000060";
                                plane0_ypos_x <= x"000";
                                front_buffer_x <= YES;
 
                        when INIT_BKG   =>
                                --flip buffers  
                                source_address_x        <= x"012C00";
                                line_size_x       <= x"0A0";
                                target_address_x  <= x"000000";
                                source_lines_x          <= x"00EF";
                                alphaOp_x                       <= NO;
                                blit_begin <= YES;
                                state_x <= DRAW_BKG;
 
                        when DRAW_BKG =>
                           blit_begin <= YES;
 
                                if (blit_done = YES) then
                                        reset_blitter <= YES;
                                        state_x <= BLIT_REST;
                                end if;
 
                        when BLIT_REST =>
                                source_address_x        <= x"01EBE5";
                                line_size_x             <= x"024";
                                target_address_x  <= plane0_dest_r;
                                source_lines_x          <= x"004E";
                                alphaOp_x                       <= YES;
 
                                reset_blitter <= YES;
                                state_x <= INIT_SPRITE;
 
                when INIT_SPRITE =>
                                blit_begin <= YES;
 
                                state_x <= DRAW_SPRITE;
 
                        when DRAW_SPRITE        =>
                                blit_begin <= YES;
 
                                if (blit_done = YES) then
                                        reset_blitter <= YES;
                                        state_x <= UPDATE;
                                end if;
 
                        when UPDATE =>
                                reset_blitter <= YES;
                                if (delay_r = x"FFFFF") then
                                        plane0_dest_x <= plane0_dest_r + x"000140";
                                        plane0_ypos_x <= plane0_ypos_r + x"001";
                                        if (plane0_ypos_r = x"050") then
                                                plane0_dest_x <= x"000060";
                                                plane0_ypos_x <= x"000";
                                        end if;
                                        state_x <= INIT_BKG;
                                end if;
 
                end case;
        end process;
 
   -- update the SDRAM address counter
   process(sdram_clk1x)
   begin
     if rising_edge(sdram_clk1x) then
 
                 --VGA Related Stuff
                 if eof = YES then
         drawframe <= not drawframe;                                     -- draw every other frame
 
                        -- reset the address at the end of a video frame depending on which buffer is the front
                        if (front_buffer = YES) then
                                vga_address <= x"000000";
                        else
                                vga_address <= x"009600";
                        end if;
                 elsif (earlyOpBegun0 = YES) then
                        vga_address <= vga_address + 1;            -- go to the next address once the read of the current address has begun
                 end if;
 
                --reset stuff
                if (sysReset = YES) then
                   state_r <= INIT;
                end if;
 
                state_r                                 <= state_x;
                delay_r                         <= delay_x;
                source_address_r        <= source_address_x;
                line_size_r             <= line_size_x;
                target_address_r        <= target_address_x;
                source_lines_r          <= source_lines_x;
        alphaOp_r                       <= alphaOp_x;
           plane0_dest_r                <= plane0_dest_x;
                plane0_ypos_r           <= plane0_ypos_x;
                front_buffer_r          <= front_buffer_x;
 
          end if;
   end process;
 
        --process reset circuitry
        process(sdram_bufclk)
        begin
                if (rising_edge(sdram_bufclk)) then
                        if sdram_lock='0' then
                                sysReset <= '1';     -- keep in reset until DLLs start up
                        else
                                --sysReset <= '0';
                                sysReset <= not pin_pushbtn;  -- push button will reset
                        end if;
                end if;
        end process;
end arch;

Line No.	Rev	Author	Line
1	6	zuofu	`--ECE395 GPU:`
2			`--Top Level HDL`
3			`--=====================================================`
4			`--Designed by:`
5			`--Zuofu Cheng`
6			`--James Cavanaugh`
7			`--Eric Sands`
8			`--`
9			`--of the University of Illinois at Urbana Champaign`
10			`--under the direction of Dr. Lippold Haken`
11			`--====================================================`
12	7	zuofu	`--`
13			`--Heavily based off of HDL examples provided by XESS Corporation`
14			`--www.xess.com`
15			`--`
16	6	zuofu	`--Based in part on Doug Hodson's work which in turn`
17			`--was based off of the XSOC from Gray Research LLC.`
18			`--`
19	7	zuofu	`--`
20	6	zuofu	`--release under the GNU General Public License`
21			`--and kindly hosted by www.opencores.org`
22
23
24			`library IEEE;`
25			`use IEEE.std_logic_1164.all;`
26			`use IEEE.std_logic_unsigned.all;`
27			`use IEEE.numeric_std.all;`
28			`use WORK.common.all;`
29			`use WORK.xsasdram.all;`
30			`use WORK.sdram.all;`
31	7	zuofu	`use WORK.vga_pckg.all;`
32	25	zuofu	`use WORK.blitter_pckg.all;`
33	6	zuofu
34			`entity gpuChip is`
35
36			`generic(`
37			`FREQ : natural := 50_000; -- frequency of operation in KHz`
38			`PIPE_EN : boolean := true; -- enable fast, pipelined SDRAM operation`
39			`MULTIPLE_ACTIVE_ROWS: boolean := true; -- if true, allow an active row in each bank`
40	7	zuofu	`CLK_DIV : real := 1.0; -- SDRAM Clock div`
41	6	zuofu	`NROWS : natural := 4096; -- number of rows in the SDRAM`
42	7	zuofu	`NCOLS : natural := 256; -- number of columns in each SDRAM row`
43	6	zuofu	`SADDR_WIDTH : natural := 12;`
44	7	zuofu	`DATA_WIDTH : natural := 16; -- SDRAM databus width`
45	25	zuofu	`ADDR_WIDTH : natural := 23; -- host-side address width`
46			`VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV`
47	7	zuofu	`PIXEL_WIDTH : natural := 8; -- width of a pixel in memory`
48			`NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel`
49	25	zuofu	`PIXELS_PER_LINE : natural := 320; -- width of image in pixels`
50			`LINES_PER_FRAME : natural := 240; -- height of image in scanlines`
51	7	zuofu	`FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x`
52	25	zuofu	`PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111111111111"`
53	6	zuofu	`);`
54
55			`port(`
56			`pin_clkin : in std_logic; -- main clock input from external clock source`
57			`pin_ce_n : out std_logic; -- Flash RAM chip-enable`
58			`pin_pushbtn : in std_logic;`
59	25	zuofu
60	6	zuofu	`-- vga port connections`
61			`pin_red : out std_logic_vector(1 downto 0);`
62			`pin_green : out std_logic_vector(1 downto 0);`
63			`pin_blue : out std_logic_vector(1 downto 0);`
64			`pin_hsync_n : out std_logic;`
65			`pin_vsync_n : out std_logic;`
66
67			`-- SDRAM pin connections`
68			`pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays`
69			`pin_sclk : out std_logic; -- clock to SDRAM`
70			`pin_cke : out std_logic; -- SDRAM clock-enable`
71			`pin_cs_n : out std_logic; -- SDRAM chip-select`
72			`pin_ras_n : out std_logic; -- SDRAM RAS`
73			`pin_cas_n : out std_logic; -- SDRAM CAS`
74			`pin_we_n : out std_logic; -- SDRAM write-enable`
75			`pin_ba : out std_logic_vector( 1 downto 0); -- SDRAM bank-address`
76			`pin_sAddr : out std_logic_vector(11 downto 0); -- SDRAM address bus`
77			`pin_sData : inout std_logic_vector (16-1 downto 0); -- data bus to SDRAM`
78			`pin_dqmh : out std_logic; -- SDRAM DQMH`
79			`pin_dqml : out std_logic -- SDRAM DQML`
80			`);`
81			`end gpuChip;`
82
83			`architecture arch of gpuChip is`
84
85			`constant YES: std_logic := '1';`
86			`constant NO: std_logic := '0';`
87			`constant HI: std_logic := '1';`
88			`constant LO: std_logic := '0';`
89
90	25	zuofu	`type gpuState is (`
91			`INIT, -- init`
92			`INIT_BKG,`
93			`DRAW_BKG,`
94			`BLIT_REST,`
95			`INIT_SPRITE,`
96			`DRAW_SPRITE,`
97			`UPDATE`
98			`);`
99
100			`signal state_r, state_x : gpuState; -- state register and next state`
101
102			`--registers`
103			`signal plane0_dest_r, plane0_dest_x : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register`
104			`signal plane0_ypos_r, plane0_ypos_x : std_logic_vector (11 downto 0);`
105			`signal delay_r, delay_x : std_logic_vector (19 downto 0); --20 bit counter for delay`
106			`signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);`
107			`signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);`
108			`signal line_size_x, line_size_r : std_logic_vector (11 downto 0);`
109			`signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0);`
110			`signal alphaOp_x, alphaOp_r : std_logic;`
111			`signal front_buffer_x, front_buffer_r : std_logic;`
112
113	6	zuofu	`--internal signals`
114	7	zuofu	`signal sysReset : std_logic; -- system reset`
115	25	zuofu	`signal blit_reset : std_logic;`
116			`signal reset_blitter : std_logic;`
117	6	zuofu
118	25	zuofu	`-- Blitter signals`
119			`signal blit_begin : std_logic;`
120			`signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0);`
121			`signal source_lines : std_logic_vector (15 downto 0);`
122			`signal line_size : std_logic_vector (11 downto 0);`
123			`signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0);`
124			`signal blit_done : std_logic;`
125			`signal alphaOp : std_logic;`
126			`signal front_buffer : std_logic;`
127
128	6	zuofu	`--Application Side Signals for the DualPort Controller`
129	7	zuofu	`signal rst_i : std_logic; --tied reset signal`
130	6	zuofu	`signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator`
131			`signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator`
132			`signal rdPending0, rdPending1 : std_logic; -- read operation pending in SDRAM pipeline indicator`
133			`signal done0, done1 : std_logic; -- read/write operation complete indicator`
134			`signal rdDone0, rdDone1 : std_logic; -- read operation complete indicator`
135			`signal hAddr0, hAddr1 : std_logic_vector(ADDR_WIDTH-1 downto 0); -- host-side address bus`
136			`signal hDIn0, hDIn1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM`
137			`signal hDOut0, hDOut1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM`
138			`signal rd0, rd1 : std_logic; -- host-side read control signal`
139			`signal wr0, wr1 : std_logic; -- host-side write control signal`
140	7	zuofu
141	6	zuofu	`-- SDRAM host side signals`
142	7	zuofu	`signal sdram_bufclk : std_logic; -- buffered input (non-DLL) clock`
143			`signal sdram_clk1x : std_logic; -- internal master clock signal`
144			`signal sdram_clk2x : std_logic; -- doubled clock`
145			`signal sdram_lock : std_logic; -- SDRAM clock DLL lock indicator`
146			`signal sdram_rst : std_logic; -- internal reset signal`
147			`signal sdram_rd : std_logic; -- host-side read control signal`
148			`signal sdram_wr : std_logic; -- host-side write control signal`
149			`signal sdram_earlyOpBegun : std_logic;`
150			`signal sdram_OpBegun : std_logic;`
151			`signal sdram_rdPending : std_logic;`
152			`signal sdram_done : std_logic; -- SDRAM operation complete indicator`
153			`signal sdram_rdDone : std_logic; -- host-side read completed signal`
154			`signal sdram_hAddr : std_logic_vector(ADDR_WIDTH -1 downto 0); -- host address bus`
155			`signal sdram_hDIn : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data to SDRAM`
156			`signal sdram_hDOut : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data from SDRAM`
157			`signal sdram_status : std_logic_vector(3 downto 0); -- SDRAM controller status`
158	6	zuofu
159	7	zuofu
160			`-- VGA related signals`
161			`signal eof : std_logic; -- end-of-frame signal from VGA controller`
162			`signal full : std_logic; -- indicates when the VGA pixel buffer is full`
163			`signal vga_address : unsigned(ADDR_WIDTH-1 downto 0); -- SDRAM address counter`
164	25	zuofu	`signal pixels : std_logic_vector(DATA_WIDTH-1 downto 0);`
165	7	zuofu	`signal rst_n : std_logic; --VGA reset (active low)`
166	25	zuofu	`signal drawframe : std_logic; -- flag to indicate whether we are drawing current frame`
167
168	6	zuofu	`--------------------------------------------------------------------------------------------------------------`
169			`-- Beginning of Submodules`
170			`-- All instances of submodules and signals associated with them`
171			`-- are declared within. Signals not directly associated with`
172			`-- submodules are declared elsewhere.`
173			`--`
174			`--------------------------------------------------------------------------------------------------------------`
175
176			`begin`
177			`------------------------------------------------------------------------`
178			`-- Instantiate the dualport module`
179			`------------------------------------------------------------------------`
180			`u1 : dualport`
181			`generic map(`
182			`PIPE_EN => PIPE_EN,`
183			`PORT_TIME_SLOTS => PORT_TIME_SLOTS,`
184			`DATA_WIDTH => DATA_WIDTH,`
185			`HADDR_WIDTH => ADDR_WIDTH`
186			`)`
187			`port map(`
188			`clk => sdram_clk1x,`
189
190			`-- Memory Port 0 connections`
191			`rst0 => rst_i,`
192			`rd0 => rd0,`
193			`wr0 => wr0,`
194			`rdPending0 => rdPending0,`
195			`opBegun0 => opBegun0,`
196			`earlyOpBegun0 => earlyOpBegun0,`
197			`rdDone0 => rdDone0,`
198			`done0 => done0,`
199			`hAddr0 => hAddr0,`
200			`hDIn0 => hDIn0,`
201			`hDOut0 => hDOut0,`
202			`status0 => open,`
203
204			`-- Memory Port 1 connections`
205			`rst1 => rst_i,`
206			`rd1 => rd1,`
207			`wr1 => wr1,`
208			`rdPending1 => rdPending1,`
209			`opBegun1 => opBegun1,`
210			`earlyOpBegun1 => earlyOpBegun1,`
211			`rdDone1 => rdDone1,`
212			`done1 => done1,`
213			`hAddr1 => hAddr1,`
214			`hDIn1 => hDIn1,`
215			`hDOut1 => hDOut1,`
216			`status1 => open,`
217	25	zuofu
218			`-- connections to the SDRAM controller`
219	6	zuofu	`rst => sdram_rst,`
220			`rd => sdram_rd,`
221			`wr => sdram_wr,`
222			`rdPending => sdram_rdPending,`
223			`opBegun => sdram_opBegun,`
224			`earlyOpBegun => sdram_earlyOpBegun,`
225			`rdDone => sdram_rdDone,`
226			`done => sdram_done,`
227			`hAddr => sdram_hAddr,`
228			`hDIn => sdram_hDIn,`
229			`hDOut => sdram_hDOut,`
230			`status => sdram_status`
231			`);`
232
233
234			`------------------------------------------------------------------------`
235			`-- Instantiate the SDRAM controller that connects to the dualport`
236			`-- module and interfaces to the external SDRAM chip.`
237			`------------------------------------------------------------------------`
238			`u2 : xsaSDRAMCntl`
239			`generic map(`
240			`FREQ => FREQ,`
241			`CLK_DIV => CLK_DIV,`
242			`PIPE_EN => PIPE_EN,`
243			`MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,`
244			`DATA_WIDTH => DATA_WIDTH,`
245			`NROWS => NROWS,`
246			`NCOLS => NCOLS,`
247			`HADDR_WIDTH => ADDR_WIDTH,`
248			`SADDR_WIDTH => SADDR_WIDTH`
249			`)`
250			`port map(`
251			`--Dual Port Controller (Host) Side`
252			`clk => pin_clkin, -- master clock from external clock source (unbuffered)`
253			`bufclk => sdram_bufclk, -- buffered master clock output`
254			`clk1x => sdram_clk1x, -- synchronized master clock (accounts for delays to external SDRAM)`
255			`clk2x => sdram_clk2x, -- synchronized doubled master clock`
256			`lock => sdram_lock, -- DLL lock indicator`
257			`rst => sdram_rst, -- reset`
258			`rd => sdram_rd, -- host-side SDRAM read control from dualport`
259			`wr => sdram_wr, -- host-side SDRAM write control from dualport`
260			`earlyOpBegun => sdram_earlyOpBegun, -- early indicator that memory operation has begun`
261			`opBegun => sdram_opBegun, -- indicates memory read/write has begun`
262			`rdPending => sdram_rdPending, -- read operation to SDRAM is in progress`
263			`done => sdram_done, -- indicates SDRAM memory read or write operation is done`
264			`rdDone => sdram_rdDone, -- indicates SDRAM memory read operation is done`
265			`hAddr => sdram_hAddr, -- host-side address from dualport to SDRAM`
266			`hDIn => sdram_hDIn, -- test data pattern from dualport to SDRAM`
267			`hDOut => sdram_hDOut, -- SDRAM data output to dualport`
268			`status => sdram_status, -- SDRAM controller state (for diagnostics)`
269
270			`--SDRAM (External) Side`
271			`sclkfb => pin_sclkfb, -- clock feedback with added external PCB delays`
272			`sclk => pin_sclk, -- synchronized clock to external SDRAM`
273			`cke => pin_cke, -- SDRAM clock enable`
274			`cs_n => pin_cs_n, -- SDRAM chip-select`
275			`ras_n => pin_ras_n, -- SDRAM RAS`
276			`cas_n => pin_cas_n, -- SDRAM CAS`
277			`we_n => pin_we_n, -- SDRAM write-enable`
278			`ba => pin_ba, -- SDRAM bank address`
279			`sAddr => pin_sAddr, -- SDRAM address`
280			`sData => pin_sData, -- SDRAM databus`
281			`dqmh => pin_dqmh, -- SDRAM DQMH`
282			`dqml => pin_dqml -- SDRAM DQML`
283			`);`
284
285	25	zuofu	`------------------------------------------------------------------------------------------------------------`
286			`-- Instance of VGA driver, this unit generates the video signals from VRAM`
287			`------------------------------------------------------------------------------------------------------------`
288
289	6	zuofu
290	7	zuofu	`u3 : vga`
291			`generic map (`
292			`FREQ => FREQ,`
293			`CLK_DIV => VGA_CLK_DIV,`
294			`PIXEL_WIDTH => PIXEL_WIDTH,`
295			`PIXELS_PER_LINE => PIXELS_PER_LINE,`
296			`LINES_PER_FRAME => LINES_PER_FRAME,`
297			`NUM_RGB_BITS => NUM_RGB_BITS,`
298			`FIT_TO_SCREEN => FIT_TO_SCREEN`
299			`)`
300			`port map (`
301			`rst => rst_i,`
302			`clk => sdram_clk1x, -- use the resync'ed master clock so VGA generator is in sync with SDRAM`
303			`wr => rdDone0, -- write to pixel buffer when the data read from SDRAM is available`
304	25	zuofu	`pixel_data_in => pixels, -- pixel data from SDRAM`
305	7	zuofu	`full => full, -- indicates when the pixel buffer is full`
306			`eof => eof, -- indicates when the VGA generator has finished a video frame`
307			`r => pin_red, -- RGB components (output)`
308			`g => pin_green,`
309			`b => pin_blue,`
310	9	zuofu	`hsync_n => pin_hsync_n, -- horizontal sync`
311			`vsync_n => pin_vsync_n, -- vertical sync`
312	7	zuofu	`blank => open`
313			`);`
314	25	zuofu
315			`------------------------------------------------------------------------------------------------------------`
316			`-- instance of main blitter`
317			`------------------------------------------------------------------------------------------------------------`
318
319			`u4: Blitter`
320			`generic map(`
321			`FREQ => FREQ,`
322			`PIPE_EN => PIPE_EN,`
323			`DATA_WIDTH => DATA_WIDTH,`
324			`ADDR_WIDTH => ADDR_WIDTH`
325			`)`
326			`port map (`
327			`clk =>sdram_clk1x,`
328			`rst =>blit_reset,`
329			`rd =>rd1,`
330			`wr =>wr1,`
331			`opBegun =>opBegun1,`
332			`earlyopBegun =>earlyOpBegun1,`
333			`done =>done1,`
334			`rddone =>rddone1,`
335			`rdPending =>rdPending1,`
336			`Addr =>hAddr1,`
337			`DIn =>hDIn1,`
338			`DOut =>hDOut1,`
339			`blit_begin =>blit_begin,`
340			`source_address =>source_address,`
341			`source_lines =>source_lines,`
342			`target_address =>target_address,`
343			`line_size =>line_size,`
344			`alphaOp =>alphaOp,`
345			`blit_done =>blit_done,`
346			`front_buffer =>front_buffer`
347			`);`
348
349	6	zuofu	`--------------------------------------------------------------------------------------------------------------`
350			`-- End of Submodules`
351			`--------------------------------------------------------------------------------------------------------------`
352			`-- Begin Top Level Module`
353	9	zuofu
354	25	zuofu	`-- connect internal signals`
355	6	zuofu	`rst_i <= sysReset;`
356	25	zuofu	`pin_ce_n <= '1'; -- disable Flash RAM`
357
358			`rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation`
359			`hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)`
360	7	zuofu	`wr0 <= '0';`
361			`hAddr0 <= std_logic_vector(vga_address);`
362	25	zuofu
363			`blit_reset <= rst_i or reset_blitter;`
364	6	zuofu
365	25	zuofu	`-- Port0 is reserved for VGA`
366			`pixels <= hDOut0 when drawframe = '1' else "0000000000000000";`
367	7	zuofu
368	25	zuofu	`source_address <= source_address_r;`
369			`line_size <= line_size_r;`
370			`target_address <= target_address_r;`
371			`source_lines <= source_lines_r;`
372			`alphaOp <= alphaOp_r;`
373			`front_buffer <= YES;--front_buffer_r;`
374
375			`comb:process(state_r, delay_r, plane0_dest_r)`
376			`begin`
377			`blit_begin <= NO; --default operations`
378			`reset_blitter <= NO;`
379
380			`state_x <= state_r; --default register values`
381			`delay_x <= delay_r + 1;`
382			`source_address_x <= source_address_r;`
383			`line_size_x <= line_size_r;`
384			`target_address_x <= target_address_r;`
385			`source_lines_x <= source_lines_r;`
386			`alphaOp_x <= alphaOp_r;`
387			`plane0_dest_x <= plane0_dest_r;`
388			`plane0_ypos_x <= plane0_ypos_r;`
389			`front_buffer_x <= front_buffer_r;`
390
391			`case state_r is`
392			`when INIT =>`
393			`blit_begin <= NO;`
394			`reset_blitter <= YES;`
395			`state_x <= INIT_BKG;`
396			`plane0_dest_x <= x"000060";`
397			`plane0_ypos_x <= x"000";`
398			`front_buffer_x <= YES;`
399
400			`when INIT_BKG =>`
401			`--flip buffers`
402			`source_address_x <= x"012C00";`
403			`line_size_x <= x"0A0";`
404			`target_address_x <= x"000000";`
405			`source_lines_x <= x"00EF";`
406			`alphaOp_x <= NO;`
407			`blit_begin <= YES;`
408			`state_x <= DRAW_BKG;`
409
410			`when DRAW_BKG =>`
411			`blit_begin <= YES;`
412
413			`if (blit_done = YES) then`
414			`reset_blitter <= YES;`
415			`state_x <= BLIT_REST;`
416			`end if;`
417
418			`when BLIT_REST =>`
419			`source_address_x <= x"01EBE5";`
420			`line_size_x <= x"024";`
421			`target_address_x <= plane0_dest_r;`
422			`source_lines_x <= x"004E";`
423			`alphaOp_x <= YES;`
424
425			`reset_blitter <= YES;`
426			`state_x <= INIT_SPRITE;`
427
428			`when INIT_SPRITE =>`
429			`blit_begin <= YES;`
430
431			`state_x <= DRAW_SPRITE;`
432
433			`when DRAW_SPRITE =>`
434			`blit_begin <= YES;`
435
436			`if (blit_done = YES) then`
437			`reset_blitter <= YES;`
438			`state_x <= UPDATE;`
439			`end if;`
440
441			`when UPDATE =>`
442			`reset_blitter <= YES;`
443			`if (delay_r = x"FFFFF") then`
444			`plane0_dest_x <= plane0_dest_r + x"000140";`
445			`plane0_ypos_x <= plane0_ypos_r + x"001";`
446			`if (plane0_ypos_r = x"050") then`
447			`plane0_dest_x <= x"000060";`
448			`plane0_ypos_x <= x"000";`
449			`end if;`
450			`state_x <= INIT_BKG;`
451			`end if;`
452
453			`end case;`
454			`end process;`
455
456	7	zuofu	`-- update the SDRAM address counter`
457			`process(sdram_clk1x)`
458			`begin`
459			`if rising_edge(sdram_clk1x) then`
460	25	zuofu
461			`--VGA Related Stuff`
462			`if eof = YES then`
463			`drawframe <= not drawframe; -- draw every other frame`
464
465			`-- reset the address at the end of a video frame depending on which buffer is the front`
466			`if (front_buffer = YES) then`
467			`vga_address <= x"000000";`
468			`else`
469			`vga_address <= x"009600";`
470			`end if;`
471			`elsif (earlyOpBegun0 = YES) then`
472			`vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun`
473			`end if;`
474
475			`--reset stuff`
476			`if (sysReset = YES) then`
477			`state_r <= INIT;`
478			`end if;`
479
480			`state_r <= state_x;`
481			`delay_r <= delay_x;`
482			`source_address_r <= source_address_x;`
483			`line_size_r <= line_size_x;`
484			`target_address_r <= target_address_x;`
485			`source_lines_r <= source_lines_x;`
486			`alphaOp_r <= alphaOp_x;`
487			`plane0_dest_r <= plane0_dest_x;`
488			`plane0_ypos_r <= plane0_ypos_x;`
489			`front_buffer_r <= front_buffer_x;`
490
491			`end if;`
492	7	zuofu	`end process;`
493	6	zuofu
494	9	zuofu	`--process reset circuitry`
495	6	zuofu	`process(sdram_bufclk)`
496			`begin`
497			`if (rising_edge(sdram_bufclk)) then`
498			`if sdram_lock='0' then`
499			`sysReset <= '1'; -- keep in reset until DLLs start up`
500			`else`

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