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--ECE395 GPU:
--GPU Core Intermediate Block
--=====================================================
--Designed by:
--Zuofu Cheng
--James Cavanaugh
--Eric Sands
--
--of the University of Illinois at Urbana Champaign
--under the direction of Dr. Lippold Haken
--====================================================
--
--Heavily based off of HDL examples provided by XESS Corporation
--www.xess.com
--
--Based in part on Doug Hodson's work which in turn
--was based off of the XSOC from Gray Research LLC.
--                                                                              
--
--release under the GNU General Public License
--and kindly hosted by www.opencores.org
 
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use UNISIM.VComponents.all;
use WORK.common.all;
use WORK.sdram.all;
 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
package GPU_core_pckg is
        component GPU_core
                generic(
            FREQ                 :     natural := 50_000;  -- operating frequency in KHz
            DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
            HADDR_WIDTH          :     natural := 23  -- host-side address width
            );
          port(
    clk                  : in  std_logic;  -- master clock
         rst                                     :      in  std_logic;  -- reset for this entity
         rd1                  : out  std_logic;  -- initiate read operation
    wr1                  : out  std_logic;  -- initiate write operation
    opBegun1             : in std_logic;  -- read/write/self-refresh op begun (clocked)
    done1                : in std_logic;  -- read or write operation is done
         rdPending1                              : in std_logic;        -- read operation is not done
    hAddr1               : out  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address to SDRAM
    hDIn1                : out  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to dualport to SDRAM
    hDOut1               : in std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from dualport to SDRAM
         start_read                              : in std_logic;
         source_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         target_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         size                                            : in std_logic_vector(9 downto 0)
                 );
        end component GPU_core;
end package GPU_core_pckg;
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.fifo_cc_pckg.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity GPU_core is
        generic(
    FREQ                 :     natural := 50_000;  -- operating frequency in KHz
    DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
    HADDR_WIDTH          :     natural := 23  -- host-side address width
    );
    Port (
    clk                  : in  std_logic;  -- master clock
         rst                                             :      in  std_logic;  -- reset for this entity
         rd1                  : out  std_logic;  -- initiate read operation
    wr1                  : out  std_logic;  -- initiate write operation
    opBegun1             : in std_logic;  -- read/write/self-refresh op begun (clocked)
    done1                : in std_logic;  -- read or write operation is done
         rdPending1                              : in std_logic;        -- read operation is not done
    hAddr1               : out  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address to SDRAM
    hDIn1                : out  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to dualport to SDRAM
    hDOut1               : in std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from dualport to SDRAM
         start_read                              : in std_logic;
         source_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         target_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         end_address                     : in std_logic_vector(HADDR_WIDTH-1 downto 0)
         );
end GPU_core;
 
architecture Behavioral of GPU_core is
 
type my_state is (wait4Go, getLine, writeLine);
signal state : my_state;
 
signal address : std_logic_vector(HADDR_WIDTH-1 downto 0);
signal output : std_logic_vector(15 downto 0);
signal stop_address : std_logic_vector(HADDR_WIDTH-1 downto 0);
 
signal wr_q, rd_q, full_q, empty_q : std_logic;
signal datain_q, dataout_q : std_logic_vector(DATA_WIDTH-1 downto 0);
signal level_q : std_logic_vector(7 downto 0);
 
begin
 
        statemachineread : process()
        begin
 
        case state is
                when halt =>
 
                        rd1 <= '0';
                        address <= source_address;
 
                        if start_read = '1' then
                                state <= readBegin;
                        end if;
 
                when readBegin =>
 
                        -- EXIT CONDITION
                        if      end_address = address then
                                state <= readEnd;
                        elsif opBegun = '1' then
                                state <= read1;
                        end if;
 
                        rd1 <= '1';
                        hAddr1 <= address;
 
                when read1 =>
 
                        -- EXIT CONDITION
                        if end_address = address then
                                state <= readEnd;
                        elsif opBegun = '1' then
                                state <= read2;
                        end if;
 
                        rd1 <= '1';
                        address <= address + 1;
                        hAddr1 <= address;
 
                when read2 =>
 
                        -- EXIT CONDITION
                        if end_address = address then
                                state <= readEnd;
                        elsif opBegun = '1' then
                                state <= read1;
                        end if;
 
                        rd1 <= '1';
                        address <= address + 1;
                        hAddr1 <= address;
 
                when readEnd =>
 
                        if rdPending = '0' and done1 = '0' then
                                state <= writeBegin;
                        end if;
 
                        rd1 <= '0';
                        address <= target_address;
 
                when writeBegin =>
 
                        wr1 <= '1';
                        hAddr1 <= address;
                        rd_q <= '1';
                        hDIn1 <= dataout_q;
 
                when write1 =>
                when write2 =>
 
        end process;
 
        getdata : process ( clk, rdDone1, hDOut1)
        begin
                if rising_edge(clk) then
                        if rdDone1 = '1' then
                                wr_q <= '1';
                                datain_q <= hDOut1;
                        else
                                wr_q <= '0';
                        end if;
 
                        if rdDone1 = '0' and done1 = '1' then
                                rd_q <= '1';
                                hDIn1 <= dataout_q;
                        else
                                rd_q <= '0';
                        end if;
                end if;
        end process;
 
u1 : fifo_cc
port map(
                clk=>clk,
                rst=>rst,
                rd=>rd_q,
                wr=>wr_q,
                data_in=>datain_q,
                data_out=>dataout_q,
                full=>full_q,
                empty=>empty_q,
                level=>level_q
                );
 
end Behavioral;

Line No.	Rev	Author	Line
1	22	zuofu	`--ECE395 GPU:`
2			`--GPU Core Intermediate Block`
3			`--=====================================================`
4			`--Designed by:`
5			`--Zuofu Cheng`
6			`--James Cavanaugh`
7			`--Eric Sands`
8			`--`
9			`--of the University of Illinois at Urbana Champaign`
10			`--under the direction of Dr. Lippold Haken`
11			`--====================================================`
12			`--`
13			`--Heavily based off of HDL examples provided by XESS Corporation`
14			`--www.xess.com`
15			`--`
16			`--Based in part on Doug Hodson's work which in turn`
17			`--was based off of the XSOC from Gray Research LLC.`
18			`--`
19			`--`
20			`--release under the GNU General Public License`
21			`--and kindly hosted by www.opencores.org`
22
23	19	zuofu	`library IEEE, UNISIM;`
24			`use IEEE.std_logic_1164.all;`
25			`use IEEE.numeric_std.all;`
26			`use UNISIM.VComponents.all;`
27			`use WORK.common.all;`
28	21	zuofu	`use WORK.sdram.all;`
29
30	19	zuofu	`use IEEE.STD_LOGIC_ARITH.ALL;`
31			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
32
33	21	zuofu
34			`package GPU_core_pckg is`
35			`component GPU_core`
36	19	zuofu	`generic(`
37			`FREQ : natural := 50_000; -- operating frequency in KHz`
38			`DATA_WIDTH : natural := 16; -- host & SDRAM data width`
39			`HADDR_WIDTH : natural := 23 -- host-side address width`
40			`);`
41			`port(`
42			`clk : in std_logic; -- master clock`
43	21	zuofu	`rst : in std_logic; -- reset for this entity`
44	19	zuofu	`rd1 : out std_logic; -- initiate read operation`
45			`wr1 : out std_logic; -- initiate write operation`
46	21	zuofu	`opBegun1 : in std_logic; -- read/write/self-refresh op begun (clocked)`
47	19	zuofu	`done1 : in std_logic; -- read or write operation is done`
48	21	zuofu	`rdPending1 : in std_logic; -- read operation is not done`
49			`hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM`
50	19	zuofu	`hDIn1 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to dualport to SDRAM`
51			`hDOut1 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from dualport to SDRAM`
52	21	zuofu	`start_read : in std_logic;`
53			`source_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
54			`target_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
55			`size : in std_logic_vector(9 downto 0)`
56	19	zuofu	`);`
57	21	zuofu	`end component GPU_core;`
58			`end package GPU_core_pckg;`
59	19	zuofu
60	21	zuofu	`library IEEE;`
61			`use IEEE.STD_LOGIC_1164.ALL;`
62	19	zuofu	`use IEEE.STD_LOGIC_ARITH.ALL;`
63			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
64	21	zuofu	`use WORK.fifo_cc_pckg.all;`
65	19	zuofu
66	21	zuofu	`---- Uncomment the following library declaration if instantiating`
67			`---- any Xilinx primitives in this code.`
68			`--library UNISIM;`
69			`--use UNISIM.VComponents.all;`
70
71			`entity GPU_core is`
72	19	zuofu	`generic(`
73			`FREQ : natural := 50_000; -- operating frequency in KHz`
74			`DATA_WIDTH : natural := 16; -- host & SDRAM data width`
75			`HADDR_WIDTH : natural := 23 -- host-side address width`
76			`);`
77			`Port (`
78			`clk : in std_logic; -- master clock`
79	21	zuofu	`rst : in std_logic; -- reset for this entity`
80	19	zuofu	`rd1 : out std_logic; -- initiate read operation`
81			`wr1 : out std_logic; -- initiate write operation`
82	21	zuofu	`opBegun1 : in std_logic; -- read/write/self-refresh op begun (clocked)`
83	19	zuofu	`done1 : in std_logic; -- read or write operation is done`
84	21	zuofu	`rdPending1 : in std_logic; -- read operation is not done`
85			`hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM`
86	19	zuofu	`hDIn1 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to dualport to SDRAM`
87			`hDOut1 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from dualport to SDRAM`
88	21	zuofu	`start_read : in std_logic;`
89			`source_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
90			`target_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
91			`end_address : in std_logic_vector(HADDR_WIDTH-1 downto 0)`
92	19	zuofu	`);`
93	21	zuofu	`end GPU_core;`
94	19	zuofu
95	21	zuofu	`architecture Behavioral of GPU_core is`
96	19	zuofu
97	21	zuofu	`type my_state is (wait4Go, getLine, writeLine);`
98			`signal state : my_state;`
99	19	zuofu
100	21	zuofu	`signal address : std_logic_vector(HADDR_WIDTH-1 downto 0);`
101			`signal output : std_logic_vector(15 downto 0);`
102			`signal stop_address : std_logic_vector(HADDR_WIDTH-1 downto 0);`
103	19	zuofu
104	21	zuofu	`signal wr_q, rd_q, full_q, empty_q : std_logic;`
105			`signal datain_q, dataout_q : std_logic_vector(DATA_WIDTH-1 downto 0);`
106			`signal level_q : std_logic_vector(7 downto 0);`
107	19	zuofu
108	21	zuofu	`begin`
109	19	zuofu
110	21	zuofu	`statemachineread : process()`
111			`begin`
112
113			`case state is`
114			`when halt =>`
115
116			`rd1 <= '0';`
117			`address <= source_address;`
118
119			`if start_read = '1' then`
120			`state <= readBegin;`
121			`end if;`
122
123			`when readBegin =>`
124
125			`-- EXIT CONDITION`
126			`if end_address = address then`
127			`state <= readEnd;`
128			`elsif opBegun = '1' then`
129			`state <= read1;`
130			`end if;`
131
132			`rd1 <= '1';`
133			`hAddr1 <= address;`
134
135			`when read1 =>`
136
137			`-- EXIT CONDITION`
138			`if end_address = address then`
139			`state <= readEnd;`
140			`elsif opBegun = '1' then`
141			`state <= read2;`
142			`end if;`
143
144			`rd1 <= '1';`
145			`address <= address + 1;`
146			`hAddr1 <= address;`
147
148			`when read2 =>`
149
150			`-- EXIT CONDITION`
151			`if end_address = address then`
152			`state <= readEnd;`
153			`elsif opBegun = '1' then`
154			`state <= read1;`
155			`end if;`
156
157			`rd1 <= '1';`
158			`address <= address + 1;`
159			`hAddr1 <= address;`
160
161			`when readEnd =>`
162
163			`if rdPending = '0' and done1 = '0' then`
164			`state <= writeBegin;`
165			`end if;`
166
167			`rd1 <= '0';`
168			`address <= target_address;`
169
170			`when writeBegin =>`
171
172			`wr1 <= '1';`
173			`hAddr1 <= address;`
174			`rd_q <= '1';`
175			`hDIn1 <= dataout_q;`
176
177			`when write1 =>`
178			`when write2 =>`
179
180			`end process;`
181
182			`getdata : process ( clk, rdDone1, hDOut1)`
183			`begin`
184			`if rising_edge(clk) then`
185			`if rdDone1 = '1' then`
186			`wr_q <= '1';`
187			`datain_q <= hDOut1;`
188			`else`
189			`wr_q <= '0';`
190			`end if;`
191
192			`if rdDone1 = '0' and done1 = '1' then`
193			`rd_q <= '1';`
194			`hDIn1 <= dataout_q;`
195			`else`
196			`rd_q <= '0';`
197			`end if;`
198			`end if;`
199			`end process;`
200	19	zuofu
201	21	zuofu	`u1 : fifo_cc`
202			`port map(`
203			`clk=>clk,`
204			`rst=>rst,`
205			`rd=>rd_q,`
206			`wr=>wr_q,`
207			`data_in=>datain_q,`
208			`data_out=>dataout_q,`
209			`full=>full_q,`
210			`empty=>empty_q,`
211			`level=>level_q`
212			`);`
213
214	19	zuofu	`end Behavioral;`

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[/] [395_vgs/] [trunk/] [hdl/] [gpu_core.vhd] - Blame information for rev 22