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--ECE395 GPU:
--GPU Core Intermediate Block
--=====================================================
--Designed by:
--Zuofu Cheng
--James Cavanaugh
--Eric Sands
--
--of the University of Illinois at Urbana Champaign
--under the direction of Dr. Lippold Haken
--====================================================
--
--Heavily based off of HDL examples provided by XESS Corporation
--www.xess.com
--
--Based in part on Doug Hodson's work which in turn
--was based off of the XSOC from Gray Research LLC.
--                                                                              
--
--release under the GNU General Public License
--and kindly hosted by www.opencores.org
 
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use UNISIM.VComponents.all;
use WORK.common.all;
use WORK.sdram.all;
 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
package GPU_core_pckg is
        component GPU_core
                generic(
            FREQ                 :     natural := 50_000;  -- operating frequency in KHz
            DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
            HADDR_WIDTH          :     natural := 23  -- host-side address width
            );
          port(
    clk                  : in  std_logic;  -- master clock
         rst                                     :      in  std_logic;  -- reset for this entity
         rd1                  : out  std_logic;  -- initiate read operation
    wr1                  : out  std_logic;  -- initiate write operation
    opBegun1             : in std_logic;  -- read/write/self-refresh op begun (clocked)
    done1                : in std_logic;  -- read or write operation is done
         rddone1                                         : in std_logic;  -- read operation is done
         rdPending1                              : in std_logic;        -- read operation is not done
    hAddr1               : out  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address to SDRAM
    hDIn1                : out  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to dualport to SDRAM
    hDOut1               : in std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from dualport to SDRAM
         start_read                              : in std_logic;
         source_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         target_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         end_address                     : in std_logic_vector(HADDR_WIDTH-1 downto 0)
        );
        end component GPU_core;
end package GPU_core_pckg;
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.fifo_cc_pckg.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity GPU_core is
        generic(
    FREQ                 :     natural := 50_000;  -- operating frequency in KHz
    DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
    HADDR_WIDTH          :     natural := 23  -- host-side address width
    );
    Port (
    clk                  : in  std_logic;  -- master clock
         rst                                             :      in  std_logic;  -- reset for this entity
         rd1                  : out  std_logic;  -- initiate read operation
    wr1                  : out  std_logic;  -- initiate write operation
    opBegun1             : in std_logic;  -- read/write/self-refresh op begun (clocked)
    done1                : in std_logic;  -- read or write operation is done
         rddone1                                         : in std_logic;  -- read operation is done
         rdPending1                              : in std_logic;        -- read operation is not done
    hAddr1               : out  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address to SDRAM
    hDIn1                : out  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to dualport to SDRAM
    hDOut1               : in std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from dualport to SDRAM
         start_read                              : in std_logic;
         source_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         target_address          : in std_logic_vector(HADDR_WIDTH-1 downto 0);
         end_address                     : in std_logic_vector(HADDR_WIDTH-1 downto 0)
         );
end GPU_core;
 
architecture Behavioral of GPU_core is
 
--------------------------------------------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------------------------------------------
 
type state_type is (halt, read0, read1, read2, read3, write0, write1, write2);
signal current_state,next_state : state_type;
 
signal address : std_logic_vector(HADDR_WIDTH-1 downto 0);
signal output : std_logic_vector(15 downto 0);
--signal stop_address : std_logic_vector(HADDR_WIDTH-1 downto 0);
 
signal wr_q, rd_q, full_q, empty_q : std_logic;
signal datain_q, dataout_q : std_logic_vector(DATA_WIDTH-1 downto 0);
signal level_q : std_logic_vector(7 downto 0);
 
begin
--------------------------------------------------------------------------------------------------------------
-- Beginning of Submodules
-- All instances of submodules and signals associated with them
-- are declared within. Signals not directly associated with
-- submodules are declared elsewhere.
--  
--------------------------------------------------------------------------------------------------------------
u1 : fifo_cc
port map(
                clk=>clk,
                rst=>rst,
                rd=>rd_q,
                wr=>wr_q,
                data_in=>datain_q,
                data_out=>dataout_q,
                full=>full_q,
                empty=>empty_q,
                level=>level_q
);
 
--------------------------------------------------------------------------------------------------------------
-- End of Submodules
--------------------------------------------------------------------------------------------------------------
-- Begin GPUCore Module
 
-- Process that puts data into the FIFO whenever on rising edge of clk when rdDone1 is high
        getdata : process ( clk, rdDone1, hDOut1)
        begin
                if rising_edge(clk) then
                        if rdDone1 = '1' then
                                wr_q <= '1';
                                datain_q <= hDOut1;
                        else
                                wr_q <= '0';
                        end if;
 
--                      if rdDone1 = '0' and done1 = '1' then
--                              rd_q <= '1';
--                              hDIn1 <= dataout_q;
--                      else
--                              rd_q <= '0';
--                      end if;
                end if;
        end process;
 
-- Main state machine sequential process
        sync_proc : process(clk, rst)
        begin
                if (rst = '1') then
                        current_state <= halt;
                elsif rising_edge(clk) then
                        current_state <= next_state;
                end if;
        end process;
 
-- Main state machine combinatoric process
        comb_proc : process(current_state)
        begin
        case current_state is
                when halt =>
 
                        rd1 <= '0';
                        address <= source_address;
                        hAddr1 <= "00000000000000000000000";
 
                        if start_read = '1' then
                                next_state <= read0;
                        end if;
 
                when read0 =>
 
                        rd1 <= '1';
                        hAddr1 <= address;
 
                        -- EXIT CONDITION
                        if      end_address = address then
                                next_state <= read3;
                        elsif opBegun1 = '1' then
                                next_state <= read1;
                        end if;
 
                when read1 =>
 
                        rd1 <= '1';
                        address <= address + 1;
                        hAddr1 <= address;
 
                        -- EXIT CONDITION
                        if end_address = address then
                                next_state <= read3;
                        elsif opBegun1 = '1' then
                                next_state <= read2;
                        end if;
 
                when read2 =>
 
                        rd1 <= '1';
                        address <= address + 1;
                        hAddr1 <= address;
 
                        -- EXIT CONDITION
                        if end_address = address then
                                next_state <= read3;
                        elsif opBegun1 = '1' then
                                next_state <= read1;
                        end if;
 
                when read3 =>
 
                        rd1 <= '0';
                        address <= target_address;
 
                        if rdPending1 = '0' and done1 = '0' then
                                next_state <= write0;
                        end if;
 
                when write0 =>
 
                        wr1 <= '1';
                        hAddr1 <= address;
                        rd_q <= '1';
                        hDIn1 <= dataout_q;
 
                        if opBegun1 = '1' then
                                next_state <= write1;
                        end if;
 
                when write1 =>
                        wr1 <= '1';
                        hAddr1 <= address;
                        address <= address + 1;
                        rd_q <= '1';
                        hDin1 <= dataout_q;
 
                        if (empty_q = '0' and opBegun1 = '1') then
                                next_state <= write2;
                        elsif (empty_q = '1') then
                                next_state <= halt;
                        end if;
 
                when write2 =>
                        wr1 <= '1';
                        hAddr1 <= address;
                        address <= address + 1;
                        rd_q <= '1';
                        hDin1 <= dataout_q;
 
                        if (empty_q = '0' and opBegun1 = '1') then
                                next_state <= write1;
                        elsif (empty_q = '1') then
                                next_state <= halt;
                        end if;
 
        end case;
        end process;
 
 
 
 
 
end Behavioral;

Line No.	Rev	Author	Line
1	22	zuofu	`--ECE395 GPU:`
2			`--GPU Core Intermediate Block`
3			`--=====================================================`
4			`--Designed by:`
5			`--Zuofu Cheng`
6			`--James Cavanaugh`
7			`--Eric Sands`
8			`--`
9			`--of the University of Illinois at Urbana Champaign`
10			`--under the direction of Dr. Lippold Haken`
11			`--====================================================`
12			`--`
13			`--Heavily based off of HDL examples provided by XESS Corporation`
14			`--www.xess.com`
15			`--`
16			`--Based in part on Doug Hodson's work which in turn`
17			`--was based off of the XSOC from Gray Research LLC.`
18			`--`
19			`--`
20			`--release under the GNU General Public License`
21			`--and kindly hosted by www.opencores.org`
22
23	19	zuofu	`library IEEE, UNISIM;`
24			`use IEEE.std_logic_1164.all;`
25			`use IEEE.numeric_std.all;`
26			`use UNISIM.VComponents.all;`
27			`use WORK.common.all;`
28	21	zuofu	`use WORK.sdram.all;`
29
30	19	zuofu	`use IEEE.STD_LOGIC_ARITH.ALL;`
31			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
32
33	21	zuofu
34			`package GPU_core_pckg is`
35			`component GPU_core`
36	19	zuofu	`generic(`
37			`FREQ : natural := 50_000; -- operating frequency in KHz`
38			`DATA_WIDTH : natural := 16; -- host & SDRAM data width`
39			`HADDR_WIDTH : natural := 23 -- host-side address width`
40			`);`
41			`port(`
42			`clk : in std_logic; -- master clock`
43	21	zuofu	`rst : in std_logic; -- reset for this entity`
44	19	zuofu	`rd1 : out std_logic; -- initiate read operation`
45			`wr1 : out std_logic; -- initiate write operation`
46	21	zuofu	`opBegun1 : in std_logic; -- read/write/self-refresh op begun (clocked)`
47	19	zuofu	`done1 : in std_logic; -- read or write operation is done`
48	23	zuofu	`rddone1 : in std_logic; -- read operation is done`
49	21	zuofu	`rdPending1 : in std_logic; -- read operation is not done`
50			`hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM`
51	19	zuofu	`hDIn1 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to dualport to SDRAM`
52			`hDOut1 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from dualport to SDRAM`
53	21	zuofu	`start_read : in std_logic;`
54			`source_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
55			`target_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
56	23	zuofu	`end_address : in std_logic_vector(HADDR_WIDTH-1 downto 0)`
57			`);`
58	21	zuofu	`end component GPU_core;`
59			`end package GPU_core_pckg;`
60	19	zuofu
61	21	zuofu	`library IEEE;`
62			`use IEEE.STD_LOGIC_1164.ALL;`
63	19	zuofu	`use IEEE.STD_LOGIC_ARITH.ALL;`
64			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
65	21	zuofu	`use WORK.fifo_cc_pckg.all;`
66	19	zuofu
67	21	zuofu	`---- Uncomment the following library declaration if instantiating`
68			`---- any Xilinx primitives in this code.`
69			`--library UNISIM;`
70			`--use UNISIM.VComponents.all;`
71
72			`entity GPU_core is`
73	19	zuofu	`generic(`
74			`FREQ : natural := 50_000; -- operating frequency in KHz`
75			`DATA_WIDTH : natural := 16; -- host & SDRAM data width`
76			`HADDR_WIDTH : natural := 23 -- host-side address width`
77			`);`
78			`Port (`
79			`clk : in std_logic; -- master clock`
80	21	zuofu	`rst : in std_logic; -- reset for this entity`
81	19	zuofu	`rd1 : out std_logic; -- initiate read operation`
82			`wr1 : out std_logic; -- initiate write operation`
83	21	zuofu	`opBegun1 : in std_logic; -- read/write/self-refresh op begun (clocked)`
84	19	zuofu	`done1 : in std_logic; -- read or write operation is done`
85	23	zuofu	`rddone1 : in std_logic; -- read operation is done`
86	21	zuofu	`rdPending1 : in std_logic; -- read operation is not done`
87			`hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM`
88	19	zuofu	`hDIn1 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to dualport to SDRAM`
89			`hDOut1 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from dualport to SDRAM`
90	21	zuofu	`start_read : in std_logic;`
91			`source_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
92			`target_address : in std_logic_vector(HADDR_WIDTH-1 downto 0);`
93			`end_address : in std_logic_vector(HADDR_WIDTH-1 downto 0)`
94	19	zuofu	`);`
95	21	zuofu	`end GPU_core;`
96	19	zuofu
97	21	zuofu	`architecture Behavioral of GPU_core is`
98	19	zuofu
99	23	zuofu	`--------------------------------------------------------------------------------------------------------------`
100			`-- Signal Declarations`
101			`--------------------------------------------------------------------------------------------------------------`
102	19	zuofu
103	23	zuofu	`type state_type is (halt, read0, read1, read2, read3, write0, write1, write2);`
104			`signal current_state,next_state : state_type;`
105
106	21	zuofu	`signal address : std_logic_vector(HADDR_WIDTH-1 downto 0);`
107			`signal output : std_logic_vector(15 downto 0);`
108	24	zuofu	`--signal stop_address : std_logic_vector(HADDR_WIDTH-1 downto 0);`
109	19	zuofu
110	21	zuofu	`signal wr_q, rd_q, full_q, empty_q : std_logic;`
111			`signal datain_q, dataout_q : std_logic_vector(DATA_WIDTH-1 downto 0);`
112			`signal level_q : std_logic_vector(7 downto 0);`
113	19	zuofu
114	21	zuofu	`begin`
115	23	zuofu	`--------------------------------------------------------------------------------------------------------------`
116			`-- Beginning of Submodules`
117			`-- All instances of submodules and signals associated with them`
118			`-- are declared within. Signals not directly associated with`
119			`-- submodules are declared elsewhere.`
120			`--`
121			`--------------------------------------------------------------------------------------------------------------`
122			`u1 : fifo_cc`
123			`port map(`
124			`clk=>clk,`
125			`rst=>rst,`
126			`rd=>rd_q,`
127			`wr=>wr_q,`
128			`data_in=>datain_q,`
129			`data_out=>dataout_q,`
130			`full=>full_q,`
131			`empty=>empty_q,`
132			`level=>level_q`
133			`);`
134	19	zuofu
135	23	zuofu	`--------------------------------------------------------------------------------------------------------------`
136			`-- End of Submodules`
137			`--------------------------------------------------------------------------------------------------------------`
138			`-- Begin GPUCore Module`
139
140			`-- Process that puts data into the FIFO whenever on rising edge of clk when rdDone1 is high`
141			`getdata : process ( clk, rdDone1, hDOut1)`
142	21	zuofu	`begin`
143	23	zuofu	`if rising_edge(clk) then`
144			`if rdDone1 = '1' then`
145			`wr_q <= '1';`
146			`datain_q <= hDOut1;`
147			`else`
148			`wr_q <= '0';`
149			`end if;`
150	21	zuofu
151	24	zuofu	`-- if rdDone1 = '0' and done1 = '1' then`
152			`-- rd_q <= '1';`
153			`-- hDIn1 <= dataout_q;`
154			`-- else`
155			`-- rd_q <= '0';`
156			`-- end if;`
157	23	zuofu	`end if;`
158			`end process;`
159
160			`-- Main state machine sequential process`
161			`sync_proc : process(clk, rst)`
162			`begin`
163			`if (rst = '1') then`
164			`current_state <= halt;`
165			`elsif rising_edge(clk) then`
166			`current_state <= next_state;`
167			`end if;`
168			`end process;`
169
170			`-- Main state machine combinatoric process`
171			`comb_proc : process(current_state)`
172			`begin`
173			`case current_state is`
174	21	zuofu	`when halt =>`
175
176			`rd1 <= '0';`
177			`address <= source_address;`
178	24	zuofu	`hAddr1 <= "00000000000000000000000";`
179	21	zuofu
180			`if start_read = '1' then`
181	23	zuofu	`next_state <= read0;`
182	21	zuofu	`end if;`
183
184	23	zuofu	`when read0 =>`
185
186			`rd1 <= '1';`
187			`hAddr1 <= address;`
188
189	21	zuofu	`-- EXIT CONDITION`
190			`if end_address = address then`
191	23	zuofu	`next_state <= read3;`
192			`elsif opBegun1 = '1' then`
193			`next_state <= read1;`
194	21	zuofu	`end if;`
195
196			`when read1 =>`
197
198			`rd1 <= '1';`
199			`address <= address + 1;`
200			`hAddr1 <= address;`
201
202			`-- EXIT CONDITION`
203			`if end_address = address then`
204	23	zuofu	`next_state <= read3;`
205			`elsif opBegun1 = '1' then`
206			`next_state <= read2;`
207	21	zuofu	`end if;`
208
209	23	zuofu	`when read2 =>`
210
211	21	zuofu	`rd1 <= '1';`
212			`address <= address + 1;`
213			`hAddr1 <= address;`
214
215	23	zuofu	`-- EXIT CONDITION`
216			`if end_address = address then`
217			`next_state <= read3;`
218			`elsif opBegun1 = '1' then`
219			`next_state <= read1;`
220	21	zuofu	`end if;`
221	23	zuofu
222			`when read3 =>`
223	21	zuofu
224			`rd1 <= '0';`
225			`address <= target_address;`
226
227	23	zuofu	`if rdPending1 = '0' and done1 = '0' then`
228			`next_state <= write0;`
229			`end if;`
230	21	zuofu
231	23	zuofu	`when write0 =>`
232
233	21	zuofu	`wr1 <= '1';`
234			`hAddr1 <= address;`
235			`rd_q <= '1';`
236			`hDIn1 <= dataout_q;`
237
238	24	zuofu	`if opBegun1 = '1' then`
239			`next_state <= write1;`
240			`end if;`
241
242	21	zuofu	`when write1 =>`
243	24	zuofu	`wr1 <= '1';`
244			`hAddr1 <= address;`
245			`address <= address + 1;`
246			`rd_q <= '1';`
247			`hDin1 <= dataout_q;`
248
249			`if (empty_q = '0' and opBegun1 = '1') then`
250			`next_state <= write2;`
251			`elsif (empty_q = '1') then`
252			`next_state <= halt;`
253			`end if;`
254
255	21	zuofu	`when write2 =>`
256	24	zuofu	`wr1 <= '1';`
257			`hAddr1 <= address;`
258			`address <= address + 1;`
259			`rd_q <= '1';`
260			`hDin1 <= dataout_q;`
261	21	zuofu
262	24	zuofu	`if (empty_q = '0' and opBegun1 = '1') then`
263			`next_state <= write1;`
264			`elsif (empty_q = '1') then`
265			`next_state <= halt;`
266			`end if;`
267	23	zuofu
268			`end case;`
269	21	zuofu	`end process;`
270
271
272
273	23	zuofu
274
275	19	zuofu	`end Behavioral;`

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[/] [395_vgs/] [trunk/] [hdl/] [gpu_core.vhd] - Blame information for rev 33