1 |
2 |
zuofu |
--ECE395 GPU:
|
2 |
|
|
--Top Level HDL
|
3 |
|
|
--=====================================================
|
4 |
|
|
--Designed by:
|
5 |
|
|
--Zuofu Cheng
|
6 |
|
|
--James Cavanaugh
|
7 |
|
|
--Eric Sands
|
8 |
|
|
--
|
9 |
|
|
--of the University of Illinois at Urbana Champaign
|
10 |
|
|
--under the direction of Dr. Lippold Haken
|
11 |
|
|
--====================================================
|
12 |
10 |
zuofu |
--
|
13 |
|
|
--Heavily based off of HDL examples provided by XESS Corporation
|
14 |
|
|
--www.xess.com
|
15 |
|
|
--
|
16 |
2 |
zuofu |
--Based in part on Doug Hodson's work which in turn
|
17 |
|
|
--was based off of the XSOC from Gray Research LLC.
|
18 |
|
|
--
|
19 |
10 |
zuofu |
--
|
20 |
2 |
zuofu |
--release under the GNU General Public License
|
21 |
|
|
--and kindly hosted by www.opencores.org
|
22 |
|
|
|
23 |
|
|
|
24 |
|
|
library IEEE;
|
25 |
|
|
use IEEE.std_logic_1164.all;
|
26 |
|
|
use IEEE.std_logic_unsigned.all;
|
27 |
|
|
use IEEE.numeric_std.all;
|
28 |
|
|
use WORK.common.all;
|
29 |
|
|
use WORK.xsasdram.all;
|
30 |
|
|
use WORK.sdram.all;
|
31 |
10 |
zuofu |
use WORK.vga_pckg.all;
|
32 |
17 |
zuofu |
<<<<<<< gpuchip.vhd
|
33 |
|
|
use WORK.gpu_core_pckg.all;
|
34 |
|
|
=======
|
35 |
15 |
cavanaug |
use WORK.fillunit_pckg.all;
|
36 |
17 |
zuofu |
>>>>>>> 1.5
|
37 |
2 |
zuofu |
|
38 |
|
|
entity gpuChip is
|
39 |
|
|
|
40 |
|
|
generic(
|
41 |
|
|
FREQ : natural := 50_000; -- frequency of operation in KHz
|
42 |
|
|
PIPE_EN : boolean := true; -- enable fast, pipelined SDRAM operation
|
43 |
|
|
MULTIPLE_ACTIVE_ROWS: boolean := true; -- if true, allow an active row in each bank
|
44 |
10 |
zuofu |
CLK_DIV : real := 1.0; -- SDRAM Clock div
|
45 |
2 |
zuofu |
NROWS : natural := 4096; -- number of rows in the SDRAM
|
46 |
|
|
NCOLS : natural := 512; -- number of columns in each SDRAM row
|
47 |
|
|
SADDR_WIDTH : natural := 12;
|
48 |
10 |
zuofu |
DATA_WIDTH : natural := 16; -- SDRAM databus width
|
49 |
|
|
ADDR_WIDTH : natural := 23; -- host-side address width
|
50 |
12 |
zuofu |
VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV
|
51 |
10 |
zuofu |
PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
|
52 |
|
|
NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
|
53 |
12 |
zuofu |
PIXELS_PER_LINE : natural := 320; -- width of image in pixels
|
54 |
|
|
LINES_PER_FRAME : natural := 240; -- height of image in scanlines
|
55 |
10 |
zuofu |
FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
|
56 |
15 |
cavanaug |
PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111100001111"
|
57 |
2 |
zuofu |
);
|
58 |
|
|
|
59 |
|
|
port(
|
60 |
|
|
pin_clkin : in std_logic; -- main clock input from external clock source
|
61 |
|
|
pin_ce_n : out std_logic; -- Flash RAM chip-enable
|
62 |
|
|
pin_pushbtn : in std_logic;
|
63 |
|
|
|
64 |
|
|
-- vga port connections
|
65 |
|
|
pin_red : out std_logic_vector(1 downto 0);
|
66 |
|
|
pin_green : out std_logic_vector(1 downto 0);
|
67 |
|
|
pin_blue : out std_logic_vector(1 downto 0);
|
68 |
|
|
pin_hsync_n : out std_logic;
|
69 |
|
|
pin_vsync_n : out std_logic;
|
70 |
|
|
|
71 |
17 |
zuofu |
-- SRAM Cache connections
|
72 |
|
|
pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache
|
73 |
|
|
pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus
|
74 |
|
|
pin_cwrite : out std_logic;
|
75 |
|
|
pin_cread : out std_logic;
|
76 |
|
|
|
77 |
2 |
zuofu |
-- SDRAM pin connections
|
78 |
|
|
pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays
|
79 |
|
|
pin_sclk : out std_logic; -- clock to SDRAM
|
80 |
|
|
pin_cke : out std_logic; -- SDRAM clock-enable
|
81 |
|
|
pin_cs_n : out std_logic; -- SDRAM chip-select
|
82 |
|
|
pin_ras_n : out std_logic; -- SDRAM RAS
|
83 |
|
|
pin_cas_n : out std_logic; -- SDRAM CAS
|
84 |
|
|
pin_we_n : out std_logic; -- SDRAM write-enable
|
85 |
|
|
pin_ba : out std_logic_vector( 1 downto 0); -- SDRAM bank-address
|
86 |
|
|
pin_sAddr : out std_logic_vector(11 downto 0); -- SDRAM address bus
|
87 |
|
|
pin_sData : inout std_logic_vector (16-1 downto 0); -- data bus to SDRAM
|
88 |
|
|
pin_dqmh : out std_logic; -- SDRAM DQMH
|
89 |
|
|
pin_dqml : out std_logic -- SDRAM DQML
|
90 |
|
|
);
|
91 |
|
|
end gpuChip;
|
92 |
|
|
|
93 |
|
|
architecture arch of gpuChip is
|
94 |
|
|
|
95 |
|
|
constant YES: std_logic := '1';
|
96 |
|
|
constant NO: std_logic := '0';
|
97 |
|
|
constant HI: std_logic := '1';
|
98 |
|
|
constant LO: std_logic := '0';
|
99 |
|
|
|
100 |
|
|
--internal signals
|
101 |
10 |
zuofu |
signal sysClk : std_logic; -- system clock
|
102 |
|
|
signal sysReset : std_logic; -- system reset
|
103 |
2 |
zuofu |
|
104 |
|
|
--Application Side Signals for the DualPort Controller
|
105 |
10 |
zuofu |
signal rst_i : std_logic; --tied reset signal
|
106 |
2 |
zuofu |
signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
|
107 |
|
|
signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
|
108 |
|
|
signal rdPending0, rdPending1 : std_logic; -- read operation pending in SDRAM pipeline indicator
|
109 |
|
|
signal done0, done1 : std_logic; -- read/write operation complete indicator
|
110 |
|
|
signal rdDone0, rdDone1 : std_logic; -- read operation complete indicator
|
111 |
|
|
signal hAddr0, hAddr1 : std_logic_vector(ADDR_WIDTH-1 downto 0); -- host-side address bus
|
112 |
|
|
signal hDIn0, hDIn1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM
|
113 |
|
|
signal hDOut0, hDOut1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM
|
114 |
|
|
signal rd0, rd1 : std_logic; -- host-side read control signal
|
115 |
|
|
signal wr0, wr1 : std_logic; -- host-side write control signal
|
116 |
10 |
zuofu |
|
117 |
2 |
zuofu |
-- SDRAM host side signals
|
118 |
10 |
zuofu |
signal sdram_bufclk : std_logic; -- buffered input (non-DLL) clock
|
119 |
|
|
signal sdram_clk1x : std_logic; -- internal master clock signal
|
120 |
|
|
signal sdram_clk2x : std_logic; -- doubled clock
|
121 |
|
|
signal sdram_lock : std_logic; -- SDRAM clock DLL lock indicator
|
122 |
|
|
signal sdram_rst : std_logic; -- internal reset signal
|
123 |
|
|
signal sdram_rd : std_logic; -- host-side read control signal
|
124 |
|
|
signal sdram_wr : std_logic; -- host-side write control signal
|
125 |
|
|
signal sdram_earlyOpBegun : std_logic;
|
126 |
|
|
signal sdram_OpBegun : std_logic;
|
127 |
|
|
signal sdram_rdPending : std_logic;
|
128 |
|
|
signal sdram_done : std_logic; -- SDRAM operation complete indicator
|
129 |
|
|
signal sdram_rdDone : std_logic; -- host-side read completed signal
|
130 |
|
|
signal sdram_hAddr : std_logic_vector(ADDR_WIDTH -1 downto 0); -- host address bus
|
131 |
|
|
signal sdram_hDIn : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data to SDRAM
|
132 |
|
|
signal sdram_hDOut : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data from SDRAM
|
133 |
|
|
signal sdram_status : std_logic_vector(3 downto 0); -- SDRAM controller status
|
134 |
2 |
zuofu |
|
135 |
10 |
zuofu |
|
136 |
|
|
-- VGA related signals
|
137 |
|
|
signal eof : std_logic; -- end-of-frame signal from VGA controller
|
138 |
|
|
signal full : std_logic; -- indicates when the VGA pixel buffer is full
|
139 |
|
|
signal vga_address : unsigned(ADDR_WIDTH-1 downto 0); -- SDRAM address counter
|
140 |
13 |
zuofu |
signal pixels : std_logic_vector(DATA_WIDTH-1 downto 0);
|
141 |
10 |
zuofu |
signal rst_n : std_logic; --VGA reset (active low)
|
142 |
13 |
zuofu |
signal drawframe : std_logic; -- flag to indicate whether we are drawing current frame
|
143 |
|
|
|
144 |
2 |
zuofu |
--------------------------------------------------------------------------------------------------------------
|
145 |
|
|
-- Beginning of Submodules
|
146 |
|
|
-- All instances of submodules and signals associated with them
|
147 |
|
|
-- are declared within. Signals not directly associated with
|
148 |
|
|
-- submodules are declared elsewhere.
|
149 |
|
|
--
|
150 |
|
|
--------------------------------------------------------------------------------------------------------------
|
151 |
|
|
|
152 |
|
|
begin
|
153 |
|
|
------------------------------------------------------------------------
|
154 |
|
|
-- Instantiate the dualport module
|
155 |
|
|
------------------------------------------------------------------------
|
156 |
|
|
u1 : dualport
|
157 |
|
|
generic map(
|
158 |
|
|
PIPE_EN => PIPE_EN,
|
159 |
|
|
PORT_TIME_SLOTS => PORT_TIME_SLOTS,
|
160 |
|
|
DATA_WIDTH => DATA_WIDTH,
|
161 |
|
|
HADDR_WIDTH => ADDR_WIDTH
|
162 |
|
|
)
|
163 |
|
|
port map(
|
164 |
|
|
clk => sdram_clk1x,
|
165 |
|
|
|
166 |
|
|
-- Memory Port 0 connections
|
167 |
|
|
rst0 => rst_i,
|
168 |
|
|
rd0 => rd0,
|
169 |
|
|
wr0 => wr0,
|
170 |
|
|
rdPending0 => rdPending0,
|
171 |
|
|
opBegun0 => opBegun0,
|
172 |
|
|
earlyOpBegun0 => earlyOpBegun0,
|
173 |
|
|
rdDone0 => rdDone0,
|
174 |
|
|
done0 => done0,
|
175 |
|
|
hAddr0 => hAddr0,
|
176 |
|
|
hDIn0 => hDIn0,
|
177 |
|
|
hDOut0 => hDOut0,
|
178 |
|
|
status0 => open,
|
179 |
|
|
|
180 |
|
|
-- Memory Port 1 connections
|
181 |
|
|
rst1 => rst_i,
|
182 |
|
|
rd1 => rd1,
|
183 |
|
|
wr1 => wr1,
|
184 |
|
|
rdPending1 => rdPending1,
|
185 |
|
|
opBegun1 => opBegun1,
|
186 |
|
|
earlyOpBegun1 => earlyOpBegun1,
|
187 |
|
|
rdDone1 => rdDone1,
|
188 |
|
|
done1 => done1,
|
189 |
|
|
hAddr1 => hAddr1,
|
190 |
|
|
hDIn1 => hDIn1,
|
191 |
|
|
hDOut1 => hDOut1,
|
192 |
|
|
status1 => open,
|
193 |
|
|
-- connections to the SDRAM controller
|
194 |
|
|
rst => sdram_rst,
|
195 |
|
|
rd => sdram_rd,
|
196 |
|
|
wr => sdram_wr,
|
197 |
|
|
rdPending => sdram_rdPending,
|
198 |
|
|
opBegun => sdram_opBegun,
|
199 |
|
|
earlyOpBegun => sdram_earlyOpBegun,
|
200 |
|
|
rdDone => sdram_rdDone,
|
201 |
|
|
done => sdram_done,
|
202 |
|
|
hAddr => sdram_hAddr,
|
203 |
|
|
hDIn => sdram_hDIn,
|
204 |
|
|
hDOut => sdram_hDOut,
|
205 |
|
|
status => sdram_status
|
206 |
|
|
);
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
------------------------------------------------------------------------
|
210 |
|
|
-- Instantiate the SDRAM controller that connects to the dualport
|
211 |
|
|
-- module and interfaces to the external SDRAM chip.
|
212 |
|
|
------------------------------------------------------------------------
|
213 |
|
|
u2 : xsaSDRAMCntl
|
214 |
|
|
generic map(
|
215 |
|
|
FREQ => FREQ,
|
216 |
|
|
CLK_DIV => CLK_DIV,
|
217 |
|
|
PIPE_EN => PIPE_EN,
|
218 |
|
|
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
|
219 |
|
|
DATA_WIDTH => DATA_WIDTH,
|
220 |
|
|
NROWS => NROWS,
|
221 |
|
|
NCOLS => NCOLS,
|
222 |
|
|
HADDR_WIDTH => ADDR_WIDTH,
|
223 |
|
|
SADDR_WIDTH => SADDR_WIDTH
|
224 |
|
|
)
|
225 |
|
|
port map(
|
226 |
|
|
--Dual Port Controller (Host) Side
|
227 |
|
|
clk => pin_clkin, -- master clock from external clock source (unbuffered)
|
228 |
|
|
bufclk => sdram_bufclk, -- buffered master clock output
|
229 |
|
|
clk1x => sdram_clk1x, -- synchronized master clock (accounts for delays to external SDRAM)
|
230 |
|
|
clk2x => sdram_clk2x, -- synchronized doubled master clock
|
231 |
|
|
lock => sdram_lock, -- DLL lock indicator
|
232 |
|
|
rst => sdram_rst, -- reset
|
233 |
|
|
rd => sdram_rd, -- host-side SDRAM read control from dualport
|
234 |
|
|
wr => sdram_wr, -- host-side SDRAM write control from dualport
|
235 |
|
|
earlyOpBegun => sdram_earlyOpBegun, -- early indicator that memory operation has begun
|
236 |
|
|
opBegun => sdram_opBegun, -- indicates memory read/write has begun
|
237 |
|
|
rdPending => sdram_rdPending, -- read operation to SDRAM is in progress
|
238 |
|
|
done => sdram_done, -- indicates SDRAM memory read or write operation is done
|
239 |
|
|
rdDone => sdram_rdDone, -- indicates SDRAM memory read operation is done
|
240 |
|
|
hAddr => sdram_hAddr, -- host-side address from dualport to SDRAM
|
241 |
|
|
hDIn => sdram_hDIn, -- test data pattern from dualport to SDRAM
|
242 |
|
|
hDOut => sdram_hDOut, -- SDRAM data output to dualport
|
243 |
|
|
status => sdram_status, -- SDRAM controller state (for diagnostics)
|
244 |
|
|
|
245 |
|
|
--SDRAM (External) Side
|
246 |
|
|
sclkfb => pin_sclkfb, -- clock feedback with added external PCB delays
|
247 |
|
|
sclk => pin_sclk, -- synchronized clock to external SDRAM
|
248 |
|
|
cke => pin_cke, -- SDRAM clock enable
|
249 |
|
|
cs_n => pin_cs_n, -- SDRAM chip-select
|
250 |
|
|
ras_n => pin_ras_n, -- SDRAM RAS
|
251 |
|
|
cas_n => pin_cas_n, -- SDRAM CAS
|
252 |
|
|
we_n => pin_we_n, -- SDRAM write-enable
|
253 |
|
|
ba => pin_ba, -- SDRAM bank address
|
254 |
|
|
sAddr => pin_sAddr, -- SDRAM address
|
255 |
|
|
sData => pin_sData, -- SDRAM databus
|
256 |
|
|
dqmh => pin_dqmh, -- SDRAM DQMH
|
257 |
|
|
dqml => pin_dqml -- SDRAM DQML
|
258 |
|
|
);
|
259 |
|
|
|
260 |
15 |
cavanaug |
------------------------------------------------------------------------------------------------------------
|
261 |
|
|
-- instance of vga
|
262 |
|
|
------------------------------------------------------------------------------------------------------------
|
263 |
|
|
|
264 |
2 |
zuofu |
|
265 |
10 |
zuofu |
u3 : vga
|
266 |
|
|
generic map (
|
267 |
|
|
FREQ => FREQ,
|
268 |
|
|
CLK_DIV => VGA_CLK_DIV,
|
269 |
|
|
PIXEL_WIDTH => PIXEL_WIDTH,
|
270 |
|
|
PIXELS_PER_LINE => PIXELS_PER_LINE,
|
271 |
|
|
LINES_PER_FRAME => LINES_PER_FRAME,
|
272 |
|
|
NUM_RGB_BITS => NUM_RGB_BITS,
|
273 |
|
|
FIT_TO_SCREEN => FIT_TO_SCREEN
|
274 |
|
|
)
|
275 |
|
|
port map (
|
276 |
|
|
rst => rst_i,
|
277 |
|
|
clk => sdram_clk1x, -- use the resync'ed master clock so VGA generator is in sync with SDRAM
|
278 |
|
|
wr => rdDone0, -- write to pixel buffer when the data read from SDRAM is available
|
279 |
13 |
zuofu |
pixel_data_in => pixels, -- pixel data from SDRAM
|
280 |
10 |
zuofu |
full => full, -- indicates when the pixel buffer is full
|
281 |
|
|
eof => eof, -- indicates when the VGA generator has finished a video frame
|
282 |
|
|
r => pin_red, -- RGB components (output)
|
283 |
|
|
g => pin_green,
|
284 |
|
|
b => pin_blue,
|
285 |
|
|
hsync_n => pin_hsync_n, -- horizontal sync
|
286 |
|
|
vsync_n => pin_vsync_n, -- vertical sync
|
287 |
|
|
blank => open
|
288 |
|
|
);
|
289 |
15 |
cavanaug |
|
290 |
17 |
zuofu |
|
291 |
15 |
cavanaug |
------------------------------------------------------------------------------------------------------------
|
292 |
|
|
-- instance of fill-unit
|
293 |
|
|
------------------------------------------------------------------------------------------------------------
|
294 |
|
|
|
295 |
17 |
zuofu |
-- u4: fillunit
|
296 |
|
|
-- generic map(
|
297 |
|
|
-- FREQ => FREQ,
|
298 |
|
|
-- DATA_WIDTH => DATA_WIDTH,
|
299 |
|
|
-- HADDR_WIDTH => ADDR_WIDTH
|
300 |
|
|
-- )
|
301 |
|
|
-- port map(
|
302 |
|
|
-- clk => sdram_clk1x, -- master clock
|
303 |
|
|
-- reset => sysReset, -- reset for this entity
|
304 |
|
|
-- rd1 => rd1, -- initiate read operation
|
305 |
|
|
-- wr1 => wr1, -- initiate write operation
|
306 |
|
|
-- opBegun => opBegun1, --operation recieved
|
307 |
|
|
-- done1 => done1, -- read or write operation is done
|
308 |
|
|
-- hAddr1 => hAddr1, -- address to SDRAM
|
309 |
|
|
-- hDIn1 => hDIn1, -- data to dualport to SDRAM
|
310 |
|
|
-- hDOut1 => hDOut1 -- data from dualport to SDRAM
|
311 |
|
|
-- );
|
312 |
|
|
--
|
313 |
|
|
|
314 |
|
|
u5: gpu_core
|
315 |
|
|
generic map(
|
316 |
15 |
cavanaug |
FREQ => FREQ,
|
317 |
|
|
DATA_WIDTH => DATA_WIDTH,
|
318 |
|
|
HADDR_WIDTH => ADDR_WIDTH
|
319 |
|
|
)
|
320 |
17 |
zuofu |
port map (
|
321 |
|
|
clk =>sdram_clk1x,
|
322 |
|
|
rst =>sysReset,
|
323 |
|
|
rd1 =>rd1,
|
324 |
|
|
wr1 =>wr1,
|
325 |
|
|
opBegun =>opBegun1,
|
326 |
|
|
done1 =>done1,
|
327 |
|
|
rddone1 =>rddone1,
|
328 |
|
|
hAddr1 =>hAddr1,
|
329 |
|
|
hDIn1 =>hDIn1,
|
330 |
|
|
hDOut1 =>hDOut1,
|
331 |
|
|
CacheDIn =>pin_cData,
|
332 |
|
|
CacheAddr =>pin_cAddr,
|
333 |
|
|
cread =>pin_cread,
|
334 |
|
|
cwrite =>pin_cwrite
|
335 |
|
|
);
|
336 |
15 |
cavanaug |
|
337 |
2 |
zuofu |
--------------------------------------------------------------------------------------------------------------
|
338 |
|
|
-- End of Submodules
|
339 |
|
|
--------------------------------------------------------------------------------------------------------------
|
340 |
|
|
-- Begin Top Level Module
|
341 |
10 |
zuofu |
|
342 |
|
|
-- connect internal signals
|
343 |
2 |
zuofu |
rst_i <= sysReset;
|
344 |
13 |
zuofu |
pin_ce_n <= '1'; -- disable Flash RAM
|
345 |
|
|
rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
|
346 |
17 |
zuofu |
hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)
|
347 |
10 |
zuofu |
wr0 <= '0';
|
348 |
|
|
hAddr0 <= std_logic_vector(vga_address);
|
349 |
2 |
zuofu |
|
350 |
13 |
zuofu |
-- Port0 is reserved for VGA
|
351 |
2 |
zuofu |
|
352 |
13 |
zuofu |
pixels <= hDOut0 when drawframe = '1' else "00000000";
|
353 |
|
|
|
354 |
10 |
zuofu |
-- update the SDRAM address counter
|
355 |
|
|
process(sdram_clk1x)
|
356 |
|
|
begin
|
357 |
|
|
if rising_edge(sdram_clk1x) then
|
358 |
|
|
if eof = YES then
|
359 |
13 |
zuofu |
drawframe <= not drawframe; -- draw every other frame
|
360 |
|
|
vga_address <= "00000000000000000000000"; -- reset the address at the end of a video frame
|
361 |
10 |
zuofu |
elsif earlyOpBegun0 = YES then
|
362 |
|
|
vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
|
363 |
13 |
zuofu |
elsif drawframe = '0' then
|
364 |
|
|
vga_address <= vga_address + 1; --if we're not drawing a frame, keep incrementing the address
|
365 |
|
|
end if;
|
366 |
10 |
zuofu |
end if;
|
367 |
|
|
end process;
|
368 |
2 |
zuofu |
|
369 |
10 |
zuofu |
--process reset circuitry
|
370 |
2 |
zuofu |
process(sdram_bufclk)
|
371 |
|
|
begin
|
372 |
|
|
if (rising_edge(sdram_bufclk)) then
|
373 |
|
|
if sdram_lock='0' then
|
374 |
|
|
sysReset <= '1'; -- keep in reset until DLLs start up
|
375 |
|
|
else
|
376 |
|
|
--sysReset <= '0';
|
377 |
|
|
sysReset <= not pin_pushbtn; -- push button will reset
|
378 |
|
|
end if;
|
379 |
|
|
end if;
|
380 |
|
|
end process;
|
381 |
10 |
zuofu |
|
382 |
2 |
zuofu |
|
383 |
|
|
end arch;
|