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zuofu |
--ECE395 GPU:
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--Top Level HDL
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--=====================================================
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--Designed by:
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--Zuofu Cheng
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--James Cavanaugh
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--Eric Sands
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--
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--of the University of Illinois at Urbana Champaign
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--under the direction of Dr. Lippold Haken
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--====================================================
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zuofu |
--
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--Heavily based off of HDL examples provided by XESS Corporation
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--www.xess.com
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--
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2 |
zuofu |
--Based in part on Doug Hodson's work which in turn
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--was based off of the XSOC from Gray Research LLC.
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--
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zuofu |
--
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zuofu |
--release under the GNU General Public License
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--and kindly hosted by www.opencores.org
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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use WORK.common.all;
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use WORK.xsasdram.all;
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use WORK.sdram.all;
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10 |
zuofu |
use WORK.vga_pckg.all;
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17 |
zuofu |
use WORK.gpu_core_pckg.all;
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2 |
zuofu |
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entity gpuChip is
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generic(
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FREQ : natural := 50_000; -- frequency of operation in KHz
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PIPE_EN : boolean := true; -- enable fast, pipelined SDRAM operation
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MULTIPLE_ACTIVE_ROWS: boolean := true; -- if true, allow an active row in each bank
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10 |
zuofu |
CLK_DIV : real := 1.0; -- SDRAM Clock div
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2 |
zuofu |
NROWS : natural := 4096; -- number of rows in the SDRAM
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NCOLS : natural := 512; -- number of columns in each SDRAM row
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SADDR_WIDTH : natural := 12;
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10 |
zuofu |
DATA_WIDTH : natural := 16; -- SDRAM databus width
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ADDR_WIDTH : natural := 23; -- host-side address width
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12 |
zuofu |
VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV
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10 |
zuofu |
PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
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NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
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12 |
zuofu |
PIXELS_PER_LINE : natural := 320; -- width of image in pixels
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LINES_PER_FRAME : natural := 240; -- height of image in scanlines
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10 |
zuofu |
FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
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15 |
cavanaug |
PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111100001111"
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2 |
zuofu |
);
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port(
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pin_clkin : in std_logic; -- main clock input from external clock source
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pin_ce_n : out std_logic; -- Flash RAM chip-enable
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pin_pushbtn : in std_logic;
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-- vga port connections
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pin_red : out std_logic_vector(1 downto 0);
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pin_green : out std_logic_vector(1 downto 0);
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pin_blue : out std_logic_vector(1 downto 0);
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pin_hsync_n : out std_logic;
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pin_vsync_n : out std_logic;
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zuofu |
-- SRAM Cache connections
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pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache
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pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus
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pin_cwrite : out std_logic;
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pin_cread : out std_logic;
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zuofu |
-- SDRAM pin connections
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pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays
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pin_sclk : out std_logic; -- clock to SDRAM
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pin_cke : out std_logic; -- SDRAM clock-enable
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pin_cs_n : out std_logic; -- SDRAM chip-select
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pin_ras_n : out std_logic; -- SDRAM RAS
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pin_cas_n : out std_logic; -- SDRAM CAS
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pin_we_n : out std_logic; -- SDRAM write-enable
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pin_ba : out std_logic_vector( 1 downto 0); -- SDRAM bank-address
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pin_sAddr : out std_logic_vector(11 downto 0); -- SDRAM address bus
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pin_sData : inout std_logic_vector (16-1 downto 0); -- data bus to SDRAM
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pin_dqmh : out std_logic; -- SDRAM DQMH
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pin_dqml : out std_logic -- SDRAM DQML
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);
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end gpuChip;
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architecture arch of gpuChip is
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constant YES: std_logic := '1';
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constant NO: std_logic := '0';
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constant HI: std_logic := '1';
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constant LO: std_logic := '0';
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--internal signals
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10 |
zuofu |
signal sysClk : std_logic; -- system clock
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signal sysReset : std_logic; -- system reset
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2 |
zuofu |
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--Application Side Signals for the DualPort Controller
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10 |
zuofu |
signal rst_i : std_logic; --tied reset signal
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2 |
zuofu |
signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
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signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
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signal rdPending0, rdPending1 : std_logic; -- read operation pending in SDRAM pipeline indicator
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signal done0, done1 : std_logic; -- read/write operation complete indicator
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signal rdDone0, rdDone1 : std_logic; -- read operation complete indicator
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signal hAddr0, hAddr1 : std_logic_vector(ADDR_WIDTH-1 downto 0); -- host-side address bus
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signal hDIn0, hDIn1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM
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signal hDOut0, hDOut1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM
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signal rd0, rd1 : std_logic; -- host-side read control signal
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signal wr0, wr1 : std_logic; -- host-side write control signal
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10 |
zuofu |
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2 |
zuofu |
-- SDRAM host side signals
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10 |
zuofu |
signal sdram_bufclk : std_logic; -- buffered input (non-DLL) clock
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signal sdram_clk1x : std_logic; -- internal master clock signal
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signal sdram_clk2x : std_logic; -- doubled clock
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signal sdram_lock : std_logic; -- SDRAM clock DLL lock indicator
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signal sdram_rst : std_logic; -- internal reset signal
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signal sdram_rd : std_logic; -- host-side read control signal
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signal sdram_wr : std_logic; -- host-side write control signal
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signal sdram_earlyOpBegun : std_logic;
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signal sdram_OpBegun : std_logic;
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signal sdram_rdPending : std_logic;
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signal sdram_done : std_logic; -- SDRAM operation complete indicator
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signal sdram_rdDone : std_logic; -- host-side read completed signal
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signal sdram_hAddr : std_logic_vector(ADDR_WIDTH -1 downto 0); -- host address bus
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signal sdram_hDIn : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data to SDRAM
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signal sdram_hDOut : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data from SDRAM
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signal sdram_status : std_logic_vector(3 downto 0); -- SDRAM controller status
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2 |
zuofu |
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10 |
zuofu |
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-- VGA related signals
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signal eof : std_logic; -- end-of-frame signal from VGA controller
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signal full : std_logic; -- indicates when the VGA pixel buffer is full
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signal vga_address : unsigned(ADDR_WIDTH-1 downto 0); -- SDRAM address counter
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13 |
zuofu |
signal pixels : std_logic_vector(DATA_WIDTH-1 downto 0);
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10 |
zuofu |
signal rst_n : std_logic; --VGA reset (active low)
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zuofu |
signal drawframe : std_logic; -- flag to indicate whether we are drawing current frame
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2 |
zuofu |
--------------------------------------------------------------------------------------------------------------
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-- Beginning of Submodules
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-- All instances of submodules and signals associated with them
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-- are declared within. Signals not directly associated with
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-- submodules are declared elsewhere.
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--
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--------------------------------------------------------------------------------------------------------------
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begin
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------------------------------------------------------------------------
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-- Instantiate the dualport module
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------------------------------------------------------------------------
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u1 : dualport
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generic map(
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PIPE_EN => PIPE_EN,
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PORT_TIME_SLOTS => PORT_TIME_SLOTS,
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DATA_WIDTH => DATA_WIDTH,
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HADDR_WIDTH => ADDR_WIDTH
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)
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port map(
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clk => sdram_clk1x,
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-- Memory Port 0 connections
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rst0 => rst_i,
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rd0 => rd0,
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wr0 => wr0,
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rdPending0 => rdPending0,
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opBegun0 => opBegun0,
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earlyOpBegun0 => earlyOpBegun0,
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rdDone0 => rdDone0,
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done0 => done0,
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hAddr0 => hAddr0,
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hDIn0 => hDIn0,
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hDOut0 => hDOut0,
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status0 => open,
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-- Memory Port 1 connections
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rst1 => rst_i,
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rd1 => rd1,
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wr1 => wr1,
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rdPending1 => rdPending1,
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opBegun1 => opBegun1,
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earlyOpBegun1 => earlyOpBegun1,
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rdDone1 => rdDone1,
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done1 => done1,
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hAddr1 => hAddr1,
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hDIn1 => hDIn1,
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hDOut1 => hDOut1,
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status1 => open,
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-- connections to the SDRAM controller
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rst => sdram_rst,
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rd => sdram_rd,
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wr => sdram_wr,
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rdPending => sdram_rdPending,
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opBegun => sdram_opBegun,
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earlyOpBegun => sdram_earlyOpBegun,
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rdDone => sdram_rdDone,
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done => sdram_done,
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hAddr => sdram_hAddr,
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hDIn => sdram_hDIn,
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hDOut => sdram_hDOut,
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status => sdram_status
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);
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------------------------------------------------------------------------
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-- Instantiate the SDRAM controller that connects to the dualport
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-- module and interfaces to the external SDRAM chip.
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------------------------------------------------------------------------
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u2 : xsaSDRAMCntl
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generic map(
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FREQ => FREQ,
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CLK_DIV => CLK_DIV,
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PIPE_EN => PIPE_EN,
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MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
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DATA_WIDTH => DATA_WIDTH,
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NROWS => NROWS,
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NCOLS => NCOLS,
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HADDR_WIDTH => ADDR_WIDTH,
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SADDR_WIDTH => SADDR_WIDTH
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)
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port map(
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--Dual Port Controller (Host) Side
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clk => pin_clkin, -- master clock from external clock source (unbuffered)
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bufclk => sdram_bufclk, -- buffered master clock output
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clk1x => sdram_clk1x, -- synchronized master clock (accounts for delays to external SDRAM)
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clk2x => sdram_clk2x, -- synchronized doubled master clock
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lock => sdram_lock, -- DLL lock indicator
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rst => sdram_rst, -- reset
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rd => sdram_rd, -- host-side SDRAM read control from dualport
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wr => sdram_wr, -- host-side SDRAM write control from dualport
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earlyOpBegun => sdram_earlyOpBegun, -- early indicator that memory operation has begun
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opBegun => sdram_opBegun, -- indicates memory read/write has begun
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rdPending => sdram_rdPending, -- read operation to SDRAM is in progress
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done => sdram_done, -- indicates SDRAM memory read or write operation is done
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rdDone => sdram_rdDone, -- indicates SDRAM memory read operation is done
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hAddr => sdram_hAddr, -- host-side address from dualport to SDRAM
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hDIn => sdram_hDIn, -- test data pattern from dualport to SDRAM
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hDOut => sdram_hDOut, -- SDRAM data output to dualport
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status => sdram_status, -- SDRAM controller state (for diagnostics)
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--SDRAM (External) Side
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sclkfb => pin_sclkfb, -- clock feedback with added external PCB delays
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sclk => pin_sclk, -- synchronized clock to external SDRAM
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cke => pin_cke, -- SDRAM clock enable
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cs_n => pin_cs_n, -- SDRAM chip-select
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ras_n => pin_ras_n, -- SDRAM RAS
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cas_n => pin_cas_n, -- SDRAM CAS
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248 |
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we_n => pin_we_n, -- SDRAM write-enable
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249 |
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ba => pin_ba, -- SDRAM bank address
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250 |
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sAddr => pin_sAddr, -- SDRAM address
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251 |
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sData => pin_sData, -- SDRAM databus
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252 |
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dqmh => pin_dqmh, -- SDRAM DQMH
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253 |
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dqml => pin_dqml -- SDRAM DQML
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254 |
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);
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255 |
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256 |
15 |
cavanaug |
------------------------------------------------------------------------------------------------------------
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257 |
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-- instance of vga
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258 |
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------------------------------------------------------------------------------------------------------------
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260 |
2 |
zuofu |
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261 |
10 |
zuofu |
u3 : vga
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262 |
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generic map (
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263 |
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FREQ => FREQ,
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CLK_DIV => VGA_CLK_DIV,
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PIXEL_WIDTH => PIXEL_WIDTH,
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PIXELS_PER_LINE => PIXELS_PER_LINE,
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267 |
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LINES_PER_FRAME => LINES_PER_FRAME,
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268 |
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NUM_RGB_BITS => NUM_RGB_BITS,
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FIT_TO_SCREEN => FIT_TO_SCREEN
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)
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271 |
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port map (
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272 |
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rst => rst_i,
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273 |
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clk => sdram_clk1x, -- use the resync'ed master clock so VGA generator is in sync with SDRAM
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274 |
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wr => rdDone0, -- write to pixel buffer when the data read from SDRAM is available
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275 |
13 |
zuofu |
pixel_data_in => pixels, -- pixel data from SDRAM
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276 |
10 |
zuofu |
full => full, -- indicates when the pixel buffer is full
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277 |
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eof => eof, -- indicates when the VGA generator has finished a video frame
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278 |
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r => pin_red, -- RGB components (output)
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279 |
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g => pin_green,
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280 |
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b => pin_blue,
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281 |
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hsync_n => pin_hsync_n, -- horizontal sync
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282 |
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vsync_n => pin_vsync_n, -- vertical sync
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283 |
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blank => open
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284 |
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);
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285 |
15 |
cavanaug |
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286 |
17 |
zuofu |
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287 |
15 |
cavanaug |
------------------------------------------------------------------------------------------------------------
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288 |
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-- instance of fill-unit
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289 |
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------------------------------------------------------------------------------------------------------------
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290 |
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291 |
17 |
zuofu |
-- u4: fillunit
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292 |
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-- generic map(
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293 |
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-- FREQ => FREQ,
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294 |
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-- DATA_WIDTH => DATA_WIDTH,
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295 |
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-- HADDR_WIDTH => ADDR_WIDTH
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296 |
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-- )
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297 |
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-- port map(
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298 |
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-- clk => sdram_clk1x, -- master clock
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299 |
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-- reset => sysReset, -- reset for this entity
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300 |
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-- rd1 => rd1, -- initiate read operation
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301 |
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-- wr1 => wr1, -- initiate write operation
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302 |
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-- opBegun => opBegun1, --operation recieved
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303 |
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-- done1 => done1, -- read or write operation is done
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304 |
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-- hAddr1 => hAddr1, -- address to SDRAM
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305 |
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-- hDIn1 => hDIn1, -- data to dualport to SDRAM
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306 |
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-- hDOut1 => hDOut1 -- data from dualport to SDRAM
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307 |
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-- );
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308 |
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--
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309 |
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310 |
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u5: gpu_core
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311 |
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generic map(
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312 |
15 |
cavanaug |
FREQ => FREQ,
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313 |
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DATA_WIDTH => DATA_WIDTH,
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314 |
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HADDR_WIDTH => ADDR_WIDTH
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315 |
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)
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316 |
17 |
zuofu |
port map (
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317 |
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clk =>sdram_clk1x,
|
318 |
|
|
rst =>sysReset,
|
319 |
|
|
rd1 =>rd1,
|
320 |
|
|
wr1 =>wr1,
|
321 |
|
|
opBegun =>opBegun1,
|
322 |
|
|
done1 =>done1,
|
323 |
|
|
rddone1 =>rddone1,
|
324 |
|
|
hAddr1 =>hAddr1,
|
325 |
|
|
hDIn1 =>hDIn1,
|
326 |
|
|
hDOut1 =>hDOut1,
|
327 |
|
|
CacheDIn =>pin_cData,
|
328 |
|
|
CacheAddr =>pin_cAddr,
|
329 |
|
|
cread =>pin_cread,
|
330 |
|
|
cwrite =>pin_cwrite
|
331 |
|
|
);
|
332 |
15 |
cavanaug |
|
333 |
2 |
zuofu |
--------------------------------------------------------------------------------------------------------------
|
334 |
|
|
-- End of Submodules
|
335 |
|
|
--------------------------------------------------------------------------------------------------------------
|
336 |
|
|
-- Begin Top Level Module
|
337 |
10 |
zuofu |
|
338 |
|
|
-- connect internal signals
|
339 |
2 |
zuofu |
rst_i <= sysReset;
|
340 |
13 |
zuofu |
pin_ce_n <= '1'; -- disable Flash RAM
|
341 |
|
|
rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
|
342 |
17 |
zuofu |
hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)
|
343 |
10 |
zuofu |
wr0 <= '0';
|
344 |
|
|
hAddr0 <= std_logic_vector(vga_address);
|
345 |
2 |
zuofu |
|
346 |
13 |
zuofu |
-- Port0 is reserved for VGA
|
347 |
2 |
zuofu |
|
348 |
13 |
zuofu |
pixels <= hDOut0 when drawframe = '1' else "00000000";
|
349 |
|
|
|
350 |
10 |
zuofu |
-- update the SDRAM address counter
|
351 |
|
|
process(sdram_clk1x)
|
352 |
|
|
begin
|
353 |
|
|
if rising_edge(sdram_clk1x) then
|
354 |
|
|
if eof = YES then
|
355 |
13 |
zuofu |
drawframe <= not drawframe; -- draw every other frame
|
356 |
|
|
vga_address <= "00000000000000000000000"; -- reset the address at the end of a video frame
|
357 |
10 |
zuofu |
elsif earlyOpBegun0 = YES then
|
358 |
|
|
vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
|
359 |
13 |
zuofu |
elsif drawframe = '0' then
|
360 |
|
|
vga_address <= vga_address + 1; --if we're not drawing a frame, keep incrementing the address
|
361 |
|
|
end if;
|
362 |
10 |
zuofu |
end if;
|
363 |
|
|
end process;
|
364 |
2 |
zuofu |
|
365 |
10 |
zuofu |
--process reset circuitry
|
366 |
2 |
zuofu |
process(sdram_bufclk)
|
367 |
|
|
begin
|
368 |
|
|
if (rising_edge(sdram_bufclk)) then
|
369 |
|
|
if sdram_lock='0' then
|
370 |
|
|
sysReset <= '1'; -- keep in reset until DLLs start up
|
371 |
|
|
else
|
372 |
|
|
--sysReset <= '0';
|
373 |
|
|
sysReset <= not pin_pushbtn; -- push button will reset
|
374 |
|
|
end if;
|
375 |
|
|
end if;
|
376 |
|
|
end process;
|
377 |
10 |
zuofu |
|
378 |
2 |
zuofu |
|
379 |
|
|
end arch;
|