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--ECE395 GPU:
--Top Level HDL
--=====================================================
--Designed by:
--Zuofu Cheng
--James Cavanaugh
--Eric Sands
--
--of the University of Illinois at Urbana Champaign
--under the direction of Dr. Lippold Haken
--====================================================
--
--Heavily based off of HDL examples provided by XESS Corporation
--www.xess.com
--
--Based in part on Doug Hodson's work which in turn
--was based off of the XSOC from Gray Research LLC.
--                                                                              
--
--release under the GNU General Public License
--and kindly hosted by www.opencores.org
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.xsasdram.all;
use WORK.sdram.all;
use WORK.vga_pckg.all;
use WORK.blitter_pckg.all;
 
entity gpuChip is
 
        generic(
      FREQ            :       natural                       := 50_000;  -- frequency of operation in KHz
      PIPE_EN         :       boolean                       := true;  -- enable fast, pipelined SDRAM operation
      MULTIPLE_ACTIVE_ROWS:   boolean                                                           := false;  -- if true, allow an active row in each bank
                CLK_DIV         :       real                                                               := 1.0;  -- SDRAM Clock div
                NROWS           :       natural                       := 4096;  -- number of rows in the SDRAM
      NCOLS           :       natural                       := 512;  -- number of columns in each SDRAM row
        SADDR_WIDTH      :              natural                                                         := 12;
                DATA_WIDTH      :       natural                                                                 := 16;  -- SDRAM databus width
                ADDR_WIDTH      :       natural                                                                 := 24;  -- host-side address width
                VGA_CLK_DIV     :       natural                                                                 := 4;  -- pixel clock = FREQ / CLK_DIV
        PIXEL_WIDTH     :       natural                                                                 := 8;  -- width of a pixel in memory
        NUM_RGB_BITS    :       natural                                                                 := 2;  -- #bits in each R,G,B component of a pixel
        PIXELS_PER_LINE :       natural                                                                 := 320; -- width of image in pixels
        LINES_PER_FRAME :       natural                                                                 := 240;  -- height of image in scanlines
        FIT_TO_SCREEN   :       boolean                                                                 := true;  -- adapt video timing to fit image width x             
           PORT_TIME_SLOTS :       std_logic_vector(15 downto 0) := "0000111111111111"
   );
 
        port(
                pin_clkin   : in std_logic;       -- main clock input from external clock source
                pin_ce_n    : out std_logic;      -- Flash RAM chip-enable
                pin_pushbtn : in std_logic;
 
 
                -- blitter port connections
                pin_port_in       : in std_logic_vector (7 downto 0);
                pin_port_addr : in std_logic_vector     (3 downto 0);
                pin_load                  : in std_logic;
                pin_start         : in std_logic;
                pin_done                  : out std_logic;
                pin_flip_buffer: in std_logic;
 
                -- vga port connections
                pin_red     : out std_logic_vector(1 downto 0);
                pin_green   : out std_logic_vector(1 downto 0);
                pin_blue    : out std_logic_vector(1 downto 0);
                pin_hsync_n : out std_logic;
                pin_vsync_n : out std_logic;
 
                -- SDRAM pin connections
                pin_sclkfb : in std_logic;                   -- feedback SDRAM clock with PCB delays
                pin_sclk   : out std_logic;                  -- clock to SDRAM
                pin_cke    : out std_logic;                  -- SDRAM clock-enable
                pin_cs_n   : out std_logic;                  -- SDRAM chip-select
                pin_ras_n  : out std_logic;                  -- SDRAM RAS
                pin_cas_n  : out std_logic;                  -- SDRAM CAS
                pin_we_n   : out std_logic;                  -- SDRAM write-enable
                pin_ba     : out std_logic_vector( 1 downto 0);      -- SDRAM bank-address
                pin_sAddr  : out std_logic_vector(11 downto 0);      -- SDRAM address bus
                pin_sData  : inout std_logic_vector (16-1 downto 0);  -- data bus to SDRAM
                pin_dqmh   : out std_logic;                  -- SDRAM DQMH
                pin_dqml   : out std_logic                   -- SDRAM DQML                      
        );
end gpuChip;
 
architecture arch of gpuChip is
 
        constant YES:   std_logic := '1';
        constant NO:    std_logic := '0';
        constant HI:    std_logic := '1';
        constant LO:    std_logic := '0';
 
        type gpuState is (
         INIT,                           -- init
    LOAD,
         DRAW,
         REST
    );
 
        signal state_r, state_x : gpuState;  -- state register and next state
 
        --registers
        signal source_address_x, source_address_r       : std_logic_vector (ADDR_WIDTH - 1 downto 0);  -- sprite dest register
        signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
        signal source_lines_x, source_lines_r           : std_logic_vector (15 downto 0);
        signal line_size_x, line_size_r                                 : std_logic_vector (11 downto 0);
        signal alphaOp_x, alphaOp_r                                     : std_logic;
        signal front_buffer_x, front_buffer_r           : std_logic;
        signal idle_x, idle_r                                                   : std_logic;
        --signal flip_buf_pend_x, flip_buf_pend_r       : std_logic;
 
        --internal signals
   signal sysReset                                                                              : std_logic;  -- system reset
        signal blit_reset                                                                               : std_logic;
        signal reset_blitter                                                                    : std_logic;
 
        -- Blitter signals
        signal blit_begin                                                                               : std_logic;
        signal source_address                                       : std_logic_vector(ADDR_WIDTH-1 downto 0);
        signal source_lines                                                                     : std_logic_vector (15 downto 0);
        signal line_size                                                                                : std_logic_vector (11 downto 0);
        signal target_address                                                           : std_logic_vector(ADDR_WIDTH-1 downto 0);
        signal blit_done                                                                                : std_logic;
        signal alphaOp                                                                                  : std_logic;
        signal front_buffer                                                                     : std_logic;
 
        signal port_in                                                                                  : std_logic_vector (7 downto 0);
        signal port_addr                                                                                : std_logic_vector (3 downto 0);
 
         --Application Side Signals for the DualPort Controller
        signal rst_i                                                                                    : std_logic;    --tied reset signal
   signal opBegun0, opBegun1                       : std_logic;  -- read/write operation started indicator
   signal earlyOpBegun0, earlyOpBegun1          : std_logic;  -- read/write operation started indicator
   signal rdPending0, rdPending1                                           : std_logic;  -- read operation pending in SDRAM pipeline indicator
   signal done0, done1                               : std_logic;  -- read/write operation complete indicator
   signal rdDone0, rdDone1                                     : std_logic;  -- read operation complete indicator
   signal hAddr0, hAddr1                                 : std_logic_vector(ADDR_WIDTH-1 downto 0);  -- host-side address bus
   signal hDIn0, hDIn1                                    : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
   signal hDOut0, hDOut1                                                      : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
   signal rd0, rd1                                      : std_logic;  -- host-side read control signal
   signal wr0, wr1                              : std_logic;  -- host-side write control signal
 
        -- SDRAM host side signals
        signal sdram_bufclk                                                                     : std_logic;    -- buffered input (non-DLL) clock
        signal sdram_clk1x                                                                      : std_logic;    -- internal master clock signal
        signal sdram_clk2x                                                                      : std_logic;            -- doubled clock
        signal sdram_lock                                                                       : std_logic;    -- SDRAM clock DLL lock indicator
        signal sdram_rst                                                                        : std_logic;    -- internal reset signal
        signal sdram_rd                                                                         : std_logic;    -- host-side read control signal
        signal sdram_wr                                                                         : std_logic;    -- host-side write control signal
        signal sdram_earlyOpBegun                                                       : std_logic;
        signal sdram_OpBegun                                                                    : std_logic;
        signal sdram_rdPending                                                          : std_logic;
        signal sdram_done                                                                       : std_logic;    -- SDRAM operation complete indicator
        signal sdram_rdDone                                                                     : std_logic;            -- host-side read completed signal
        signal sdram_hAddr                                                                      : std_logic_vector(ADDR_WIDTH -1 downto 0);  -- host address bus
        signal sdram_hDIn                                                                       : std_logic_vector(DATA_WIDTH -1 downto 0);      -- host-side data to SDRAM
        signal sdram_hDOut                                                                      : std_logic_vector(DATA_WIDTH -1 downto 0);      -- host-side data from SDRAM
        signal sdram_status                                                                     : std_logic_vector(3 downto 0);  -- SDRAM controller status
 
 
        -- VGA related signals
        signal eof                                                                              : std_logic;      -- end-of-frame signal from VGA controller
   signal full                                                                                          : std_logic;      -- indicates when the VGA pixel buffer is full
   signal vga_address                                                           : unsigned(ADDR_WIDTH-1 downto 0);  -- SDRAM address counter 
        signal pixels                                                                                   : std_logic_vector(DATA_WIDTH-1 downto 0);
        signal rst_n                                                                                    : std_logic;            --VGA reset (active low)
        signal drawframe                                                                                : std_logic;  -- flag to indicate whether we are drawing current frame  
 
--------------------------------------------------------------------------------------------------------------
-- Beginning of Submodules
-- All instances of submodules and signals associated with them
-- are declared within. Signals not directly associated with
-- submodules are declared elsewhere.
--  
--------------------------------------------------------------------------------------------------------------
 
begin
 ------------------------------------------------------------------------
 -- Instantiate the dualport module
 ------------------------------------------------------------------------
  u1 : dualport
    generic map(
      PIPE_EN         => PIPE_EN,
      PORT_TIME_SLOTS => PORT_TIME_SLOTS,
      DATA_WIDTH      => DATA_WIDTH,
      HADDR_WIDTH     => ADDR_WIDTH
      )
    port map(
      clk             => sdram_clk1x,
 
                -- Memory Port 0 connections
                rst0            => rst_i,
      rd0             => rd0,
      wr0             => wr0,
      rdPending0      => rdPending0,
      opBegun0        => opBegun0,
      earlyOpBegun0   => earlyOpBegun0,
      rdDone0         => rdDone0,
      done0           => done0,
      hAddr0          => hAddr0,
      hDIn0           => hDIn0,
      hDOut0          => hDOut0,
      status0         => open,
 
                -- Memory Port 1 connections
      rst1            => rst_i,
      rd1             => rd1,
      wr1             => wr1,
      rdPending1      => rdPending1,
      opBegun1        => opBegun1,
      earlyOpBegun1   => earlyOpBegun1,
      rdDone1         => rdDone1,
      done1           => done1,
      hAddr1          => hAddr1,
      hDIn1           => hDIn1,
      hDOut1          => hDOut1,
      status1         => open,
 
                -- connections to the SDRAM controller
      rst             => sdram_rst,
      rd              => sdram_rd,
      wr              => sdram_wr,
      rdPending       => sdram_rdPending,
      opBegun         => sdram_opBegun,
      earlyOpBegun    => sdram_earlyOpBegun,
      rdDone          => sdram_rdDone,
      done            => sdram_done,
      hAddr           => sdram_hAddr,
      hDIn            => sdram_hDIn,
      hDOut           => sdram_hDOut,
      status          => sdram_status
      );
 
 
  ------------------------------------------------------------------------
  -- Instantiate the SDRAM controller that connects to the dualport
  -- module and interfaces to the external SDRAM chip.
  ------------------------------------------------------------------------
  u2 : xsaSDRAMCntl
    generic map(
      FREQ                                        => FREQ,
      CLK_DIV                                     => CLK_DIV,
      PIPE_EN                        => PIPE_EN,
      MULTIPLE_ACTIVE_ROWS   => MULTIPLE_ACTIVE_ROWS,
                DATA_WIDTH                        => DATA_WIDTH,
      NROWS                               => NROWS,
      NCOLS                               => NCOLS,
      HADDR_WIDTH                         => ADDR_WIDTH,
      SADDR_WIDTH                         => SADDR_WIDTH
      )
    port map(
                --Dual Port Controller (Host) Side
      clk          => pin_clkin,             -- master clock from external clock source (unbuffered)
      bufclk       => sdram_bufclk,                -- buffered master clock output
      clk1x        => sdram_clk1x,                 -- synchronized master clock (accounts for delays to external SDRAM)
      clk2x        => sdram_clk2x,              -- synchronized doubled master clock
      lock         => sdram_lock,                       -- DLL lock indicator
      rst          => sdram_rst,                        -- reset
      rd           => sdram_rd,                         -- host-side SDRAM read control from dualport
      wr           => sdram_wr,                         -- host-side SDRAM write control from dualport
      earlyOpBegun => sdram_earlyOpBegun,               -- early indicator that memory operation has begun 
                opBegun      => sdram_opBegun,          -- indicates memory read/write has begun
                rdPending    => sdram_rdPending,                -- read operation to SDRAM is in progress
      done         => sdram_done,                       -- indicates SDRAM memory read or write operation is done
      rdDone       => sdram_rdDone,                     -- indicates SDRAM memory read operation is done
      hAddr        => sdram_hAddr,           -- host-side address from dualport to SDRAM
      hDIn         => sdram_hDIn,            -- test data pattern from dualport to SDRAM
      hDOut        => sdram_hDOut,           -- SDRAM data output to dualport
      status       => sdram_status,          -- SDRAM controller state (for diagnostics)
 
           --SDRAM (External) Side
                sclkfb       => pin_sclkfb,           -- clock feedback with added external PCB delays
      sclk         => pin_sclk,             -- synchronized clock to external SDRAM
      cke          => pin_cke,              -- SDRAM clock enable
      cs_n         => pin_cs_n,             -- SDRAM chip-select
      ras_n        => pin_ras_n,            -- SDRAM RAS
      cas_n        => pin_cas_n,            -- SDRAM CAS
      we_n         => pin_we_n,             -- SDRAM write-enable
      ba           => pin_ba,               -- SDRAM bank address
      sAddr        => pin_sAddr,            -- SDRAM address
      sData        => pin_sData,            -- SDRAM databus
      dqmh         => pin_dqmh,             -- SDRAM DQMH
      dqml         => pin_dqml              -- SDRAM DQML
      );
 
------------------------------------------------------------------------------------------------------------
-- Instance of VGA driver, this unit generates the video signals from VRAM
------------------------------------------------------------------------------------------------------------
 
 
        u3 : vga
    generic map (
      FREQ            => FREQ,
      CLK_DIV         => VGA_CLK_DIV,
      PIXEL_WIDTH     => PIXEL_WIDTH,
      PIXELS_PER_LINE => PIXELS_PER_LINE,
      LINES_PER_FRAME => LINES_PER_FRAME,
      NUM_RGB_BITS    => NUM_RGB_BITS,
      FIT_TO_SCREEN   => FIT_TO_SCREEN
      )
    port map (
      rst             => rst_i,
      clk             => sdram_clk1x,   -- use the resync'ed master clock so VGA generator is in sync with SDRAM
      wr              => rdDone0,       -- write to pixel buffer when the data read from SDRAM is available
      pixel_data_in   => pixels,                 -- pixel data from SDRAM
      full            => full,          -- indicates when the pixel buffer is full
      eof             => eof,           -- indicates when the VGA generator has finished a video frame
      r               => pin_red,       -- RGB components (output)
      g               => pin_green,
      b               => pin_blue,
      hsync_n         => pin_hsync_n,   -- horizontal sync
      vsync_n         => pin_vsync_n,   -- vertical sync
      blank           => open
      );
 
------------------------------------------------------------------------------------------------------------
-- instance of main blitter
------------------------------------------------------------------------------------------------------------
 
        u4: Blitter
        generic map(
    FREQ                => FREQ,
    PIPE_EN       => PIPE_EN,
         DATA_WIDTH    => DATA_WIDTH,
    ADDR_WIDTH    => ADDR_WIDTH
    )
  port map (
    clk                          =>sdram_clk1x,
         rst                             =>blit_reset,
         rd             =>rd1,
    wr             =>wr1,
    opBegun        =>opBegun1,
    earlyopBegun   =>earlyOpBegun1,
    done           =>done1,
         rddone                  =>rddone1,
    rdPending            =>rdPending1,
         Addr           =>hAddr1,
    DIn            =>hDIn1,
    DOut           =>hDOut1,
         blit_begin              =>blit_begin,
         source_address =>source_address,
         source_lines    =>source_lines,
         target_address =>target_address,
         line_size               =>line_size,
         alphaOp                         =>alphaOp,
         blit_done               =>blit_done,
         front_buffer    =>front_buffer
         );
 
--------------------------------------------------------------------------------------------------------------
-- End of Submodules
--------------------------------------------------------------------------------------------------------------
-- Begin Top Level Module
 
        -- connect internal signals     
        rst_i <= sysReset;
        pin_ce_n <= '1';                                                  -- disable Flash RAM
 
        rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
        hDIn0 <= "0000000000000000";              -- don't need to write to port 0 (VGA Port)
        wr0 <= '0';
        hAddr0 <= std_logic_vector(vga_address);
 
        blit_reset <= rst_i or reset_blitter;
 
        -- Port0 is reserved for VGA
        pixels <= hDOut0 when drawframe = '1' else "0000000000000000";
 
        port_in                 <= pin_port_in;
        port_addr               <= pin_port_addr;
        pin_done                        <= idle_r;
 
        source_address  <= source_address_r;
        line_size               <= line_size_r;
        target_address  <= target_address_r;
        source_lines    <= source_lines_r;
        alphaOp                 <= alphaOp_r;
 
        front_buffer    <= YES;--front_buffer_r;        
 
        comb:process(state_r, port_in, port_addr, pin_start)
        begin
                blit_begin <= NO;                                               --default operations            
                reset_blitter <= NO;
 
                state_x                                 <= state_r;                                     --default register values
           source_address_x     <= source_address_r;
                target_address_x        <= target_address_r;
                source_lines_x          <= source_lines_r;
                line_size_x             <= line_size_r;
                alphaOp_x                       <= alphaOp_r;
                front_buffer_x  <= front_buffer_r;
                idle_x                          <= idle_r;
 
                case state_r is
                        when INIT =>
                                idle_x <= YES;
                                reset_blitter <= YES;
                                state_x <= LOAD;
 
                        when LOAD =>
                                if (pin_load = YES) then
                                        case port_addr is
                                                when "0000" => source_address_x(23 downto 16) <= port_in;
                                                when "0001" => source_address_x(15 downto 8)  <= port_in;
                                                when "0010" => source_address_x(7 downto  0)  <= port_in;
                                                when "0011" => target_address_x(23 downto 16) <= port_in;
                                                when "0100" => target_address_x(15 downto 8)  <= port_in;
                                                when "0101" => target_address_x(7 downto  0)  <= port_in;
                                                when "0110" => source_lines_x  (15 downto 8)  <= port_in;
                                                when "0111" => source_lines_x  (7 downto 0)       <= port_in;
                                                when "1000" => line_size_x     (11 downto 8)  <= port_in(3 downto 0);
                                                when "1001" => line_size_x     (7 downto 0)       <= port_in;
                                                when "1010" => alphaOp_x                                                         <= port_in(0);
                                                when others =>
                                        end case;
                                end if;
 
                                if (pin_start = YES) then
                                        idle_x <= NO;
                                        state_x <= DRAW;
                                end if;
 
                        when DRAW =>
                           blit_begin <= YES;
                                if (blit_done = YES) then
                                        reset_blitter <= YES;
                                        idle_x <= YES;
                                        state_x <= REST;
                                end if;
 
                        when REST =>
                                reset_blitter <= YES;
                                state_x <= LOAD;
 
                end case;
        end process;
 
   -- update the SDRAM address counter
   process(sdram_clk1x)
   begin
     if rising_edge(sdram_clk1x) then
 
                 --VGA Related Stuff
                 if eof = YES then
         drawframe <= not drawframe;                                     -- draw every other frame
 
                 -- reset the address at the end of a video frame depending on which buffer is the front
                 if (front_buffer = YES) then
                        vga_address <= x"000000";
                 else
                        vga_address <= x"000000";                                               --temporary
                 end if;
 
                 elsif (earlyOpBegun0 = YES) then
                        vga_address <= vga_address + 1;           -- go to the next address once the read of the current address has begun
                 end if;
 
                --reset stuff
                if (sysReset = YES) then
                   state_r <= INIT;
                end if;
 
                state_r                                 <= state_x;
                source_address_r        <= source_address_x;
                target_address_r        <= target_address_x;
                source_lines_r          <= source_lines_x;
                line_size_r             <= line_size_x;
        alphaOp_r                       <= alphaOp_x;
           front_buffer_r               <= front_buffer_x;
                idle_r                          <= idle_x;
 
          end if;
   end process;
 
        --process reset circuitry
        process(sdram_bufclk)
        begin
                if (rising_edge(sdram_bufclk)) then
                        if sdram_lock='0' then
                                sysReset <= '1';     -- keep in reset until DLLs start up
                        else
                                --sysReset <= '0';
                                sysReset <= not pin_pushbtn;  -- push button will reset
                        end if;
                end if;
        end process;
end arch;

Line No.	Rev	Author	Line
1	2	zuofu	`--ECE395 GPU:`
2			`--Top Level HDL`
3			`--=====================================================`
4			`--Designed by:`
5			`--Zuofu Cheng`
6			`--James Cavanaugh`
7			`--Eric Sands`
8			`--`
9			`--of the University of Illinois at Urbana Champaign`
10			`--under the direction of Dr. Lippold Haken`
11			`--====================================================`
12	10	zuofu	`--`
13			`--Heavily based off of HDL examples provided by XESS Corporation`
14			`--www.xess.com`
15			`--`
16	2	zuofu	`--Based in part on Doug Hodson's work which in turn`
17			`--was based off of the XSOC from Gray Research LLC.`
18			`--`
19	10	zuofu	`--`
20	2	zuofu	`--release under the GNU General Public License`
21			`--and kindly hosted by www.opencores.org`
22
23
24			`library IEEE;`
25			`use IEEE.std_logic_1164.all;`
26			`use IEEE.std_logic_unsigned.all;`
27			`use IEEE.numeric_std.all;`
28			`use WORK.common.all;`
29			`use WORK.xsasdram.all;`
30			`use WORK.sdram.all;`
31	10	zuofu	`use WORK.vga_pckg.all;`
32	25	zuofu	`use WORK.blitter_pckg.all;`
33	2	zuofu
34			`entity gpuChip is`
35
36			`generic(`
37			`FREQ : natural := 50_000; -- frequency of operation in KHz`
38			`PIPE_EN : boolean := true; -- enable fast, pipelined SDRAM operation`
39	26	zuofu	`MULTIPLE_ACTIVE_ROWS: boolean := false; -- if true, allow an active row in each bank`
40	10	zuofu	`CLK_DIV : real := 1.0; -- SDRAM Clock div`
41	2	zuofu	`NROWS : natural := 4096; -- number of rows in the SDRAM`
42			`NCOLS : natural := 512; -- number of columns in each SDRAM row`
43			`SADDR_WIDTH : natural := 12;`
44	10	zuofu	`DATA_WIDTH : natural := 16; -- SDRAM databus width`
45	26	zuofu	`ADDR_WIDTH : natural := 24; -- host-side address width`
46	12	zuofu	`VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV`
47	10	zuofu	`PIXEL_WIDTH : natural := 8; -- width of a pixel in memory`
48			`NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel`
49	12	zuofu	`PIXELS_PER_LINE : natural := 320; -- width of image in pixels`
50			`LINES_PER_FRAME : natural := 240; -- height of image in scanlines`
51	10	zuofu	`FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x`
52	25	zuofu	`PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111111111111"`
53	2	zuofu	`);`
54
55			`port(`
56			`pin_clkin : in std_logic; -- main clock input from external clock source`
57			`pin_ce_n : out std_logic; -- Flash RAM chip-enable`
58			`pin_pushbtn : in std_logic;`
59	25	zuofu
60	26	zuofu
61			`-- blitter port connections`
62			`pin_port_in : in std_logic_vector (7 downto 0);`
63			`pin_port_addr : in std_logic_vector (3 downto 0);`
64			`pin_load : in std_logic;`
65			`pin_start : in std_logic;`
66			`pin_done : out std_logic;`
67			`pin_flip_buffer: in std_logic;`
68
69	2	zuofu	`-- vga port connections`
70			`pin_red : out std_logic_vector(1 downto 0);`
71			`pin_green : out std_logic_vector(1 downto 0);`
72			`pin_blue : out std_logic_vector(1 downto 0);`
73			`pin_hsync_n : out std_logic;`
74			`pin_vsync_n : out std_logic;`
75
76			`-- SDRAM pin connections`
77			`pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays`
78			`pin_sclk : out std_logic; -- clock to SDRAM`
79			`pin_cke : out std_logic; -- SDRAM clock-enable`
80			`pin_cs_n : out std_logic; -- SDRAM chip-select`
81			`pin_ras_n : out std_logic; -- SDRAM RAS`
82			`pin_cas_n : out std_logic; -- SDRAM CAS`
83			`pin_we_n : out std_logic; -- SDRAM write-enable`
84			`pin_ba : out std_logic_vector( 1 downto 0); -- SDRAM bank-address`
85			`pin_sAddr : out std_logic_vector(11 downto 0); -- SDRAM address bus`
86			`pin_sData : inout std_logic_vector (16-1 downto 0); -- data bus to SDRAM`
87			`pin_dqmh : out std_logic; -- SDRAM DQMH`
88			`pin_dqml : out std_logic -- SDRAM DQML`
89			`);`
90			`end gpuChip;`
91
92			`architecture arch of gpuChip is`
93
94			`constant YES: std_logic := '1';`
95			`constant NO: std_logic := '0';`
96			`constant HI: std_logic := '1';`
97			`constant LO: std_logic := '0';`
98
99	25	zuofu	`type gpuState is (`
100			`INIT, -- init`
101	26	zuofu	`LOAD,`
102			`DRAW,`
103			`REST`
104			`);`
105	25	zuofu
106			`signal state_r, state_x : gpuState; -- state register and next state`
107
108			`--registers`
109	26	zuofu	`signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register`
110	25	zuofu	`signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);`
111	26	zuofu	`signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0);`
112	25	zuofu	`signal line_size_x, line_size_r : std_logic_vector (11 downto 0);`
113			`signal alphaOp_x, alphaOp_r : std_logic;`
114			`signal front_buffer_x, front_buffer_r : std_logic;`
115	26	zuofu	`signal idle_x, idle_r : std_logic;`
116			`--signal flip_buf_pend_x, flip_buf_pend_r : std_logic;`
117	25	zuofu
118	2	zuofu	`--internal signals`
119	10	zuofu	`signal sysReset : std_logic; -- system reset`
120	25	zuofu	`signal blit_reset : std_logic;`
121			`signal reset_blitter : std_logic;`
122	2	zuofu
123	25	zuofu	`-- Blitter signals`
124			`signal blit_begin : std_logic;`
125			`signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0);`
126			`signal source_lines : std_logic_vector (15 downto 0);`
127			`signal line_size : std_logic_vector (11 downto 0);`
128	23	zuofu	`signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0);`
129	25	zuofu	`signal blit_done : std_logic;`
130			`signal alphaOp : std_logic;`
131			`signal front_buffer : std_logic;`
132
133	26	zuofu	`signal port_in : std_logic_vector (7 downto 0);`
134			`signal port_addr : std_logic_vector (3 downto 0);`
135
136	2	zuofu	`--Application Side Signals for the DualPort Controller`
137	10	zuofu	`signal rst_i : std_logic; --tied reset signal`
138	2	zuofu	`signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator`
139			`signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator`
140			`signal rdPending0, rdPending1 : std_logic; -- read operation pending in SDRAM pipeline indicator`
141			`signal done0, done1 : std_logic; -- read/write operation complete indicator`
142			`signal rdDone0, rdDone1 : std_logic; -- read operation complete indicator`
143			`signal hAddr0, hAddr1 : std_logic_vector(ADDR_WIDTH-1 downto 0); -- host-side address bus`
144			`signal hDIn0, hDIn1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM`
145			`signal hDOut0, hDOut1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM`
146			`signal rd0, rd1 : std_logic; -- host-side read control signal`
147			`signal wr0, wr1 : std_logic; -- host-side write control signal`
148	10	zuofu
149	2	zuofu	`-- SDRAM host side signals`
150	10	zuofu	`signal sdram_bufclk : std_logic; -- buffered input (non-DLL) clock`
151			`signal sdram_clk1x : std_logic; -- internal master clock signal`
152			`signal sdram_clk2x : std_logic; -- doubled clock`
153			`signal sdram_lock : std_logic; -- SDRAM clock DLL lock indicator`
154			`signal sdram_rst : std_logic; -- internal reset signal`
155			`signal sdram_rd : std_logic; -- host-side read control signal`
156			`signal sdram_wr : std_logic; -- host-side write control signal`
157			`signal sdram_earlyOpBegun : std_logic;`
158			`signal sdram_OpBegun : std_logic;`
159			`signal sdram_rdPending : std_logic;`
160			`signal sdram_done : std_logic; -- SDRAM operation complete indicator`
161			`signal sdram_rdDone : std_logic; -- host-side read completed signal`
162			`signal sdram_hAddr : std_logic_vector(ADDR_WIDTH -1 downto 0); -- host address bus`
163			`signal sdram_hDIn : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data to SDRAM`
164			`signal sdram_hDOut : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data from SDRAM`
165			`signal sdram_status : std_logic_vector(3 downto 0); -- SDRAM controller status`
166	2	zuofu
167	10	zuofu
168			`-- VGA related signals`
169			`signal eof : std_logic; -- end-of-frame signal from VGA controller`
170			`signal full : std_logic; -- indicates when the VGA pixel buffer is full`
171			`signal vga_address : unsigned(ADDR_WIDTH-1 downto 0); -- SDRAM address counter`
172	13	zuofu	`signal pixels : std_logic_vector(DATA_WIDTH-1 downto 0);`
173	10	zuofu	`signal rst_n : std_logic; --VGA reset (active low)`
174	13	zuofu	`signal drawframe : std_logic; -- flag to indicate whether we are drawing current frame`
175
176	2	zuofu	`--------------------------------------------------------------------------------------------------------------`
177			`-- Beginning of Submodules`
178			`-- All instances of submodules and signals associated with them`
179			`-- are declared within. Signals not directly associated with`
180			`-- submodules are declared elsewhere.`
181			`--`
182			`--------------------------------------------------------------------------------------------------------------`
183
184			`begin`
185			`------------------------------------------------------------------------`
186			`-- Instantiate the dualport module`
187			`------------------------------------------------------------------------`
188			`u1 : dualport`
189			`generic map(`
190			`PIPE_EN => PIPE_EN,`
191			`PORT_TIME_SLOTS => PORT_TIME_SLOTS,`
192			`DATA_WIDTH => DATA_WIDTH,`
193			`HADDR_WIDTH => ADDR_WIDTH`
194			`)`
195			`port map(`
196			`clk => sdram_clk1x,`
197
198			`-- Memory Port 0 connections`
199			`rst0 => rst_i,`
200			`rd0 => rd0,`
201			`wr0 => wr0,`
202			`rdPending0 => rdPending0,`
203			`opBegun0 => opBegun0,`
204			`earlyOpBegun0 => earlyOpBegun0,`
205			`rdDone0 => rdDone0,`
206			`done0 => done0,`
207			`hAddr0 => hAddr0,`
208			`hDIn0 => hDIn0,`
209			`hDOut0 => hDOut0,`
210			`status0 => open,`
211
212			`-- Memory Port 1 connections`
213			`rst1 => rst_i,`
214			`rd1 => rd1,`
215			`wr1 => wr1,`
216			`rdPending1 => rdPending1,`
217			`opBegun1 => opBegun1,`
218			`earlyOpBegun1 => earlyOpBegun1,`
219			`rdDone1 => rdDone1,`
220			`done1 => done1,`
221			`hAddr1 => hAddr1,`
222			`hDIn1 => hDIn1,`
223			`hDOut1 => hDOut1,`
224			`status1 => open,`
225	25	zuofu
226			`-- connections to the SDRAM controller`
227	2	zuofu	`rst => sdram_rst,`
228			`rd => sdram_rd,`
229			`wr => sdram_wr,`
230			`rdPending => sdram_rdPending,`
231			`opBegun => sdram_opBegun,`
232			`earlyOpBegun => sdram_earlyOpBegun,`
233			`rdDone => sdram_rdDone,`
234			`done => sdram_done,`
235			`hAddr => sdram_hAddr,`
236			`hDIn => sdram_hDIn,`
237			`hDOut => sdram_hDOut,`
238			`status => sdram_status`
239			`);`
240
241
242			`------------------------------------------------------------------------`
243			`-- Instantiate the SDRAM controller that connects to the dualport`
244			`-- module and interfaces to the external SDRAM chip.`
245			`------------------------------------------------------------------------`
246			`u2 : xsaSDRAMCntl`
247			`generic map(`
248			`FREQ => FREQ,`
249			`CLK_DIV => CLK_DIV,`
250			`PIPE_EN => PIPE_EN,`
251			`MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,`
252			`DATA_WIDTH => DATA_WIDTH,`
253			`NROWS => NROWS,`
254			`NCOLS => NCOLS,`
255			`HADDR_WIDTH => ADDR_WIDTH,`
256			`SADDR_WIDTH => SADDR_WIDTH`
257			`)`
258			`port map(`
259			`--Dual Port Controller (Host) Side`
260			`clk => pin_clkin, -- master clock from external clock source (unbuffered)`
261			`bufclk => sdram_bufclk, -- buffered master clock output`
262			`clk1x => sdram_clk1x, -- synchronized master clock (accounts for delays to external SDRAM)`
263			`clk2x => sdram_clk2x, -- synchronized doubled master clock`
264			`lock => sdram_lock, -- DLL lock indicator`
265			`rst => sdram_rst, -- reset`
266			`rd => sdram_rd, -- host-side SDRAM read control from dualport`
267			`wr => sdram_wr, -- host-side SDRAM write control from dualport`
268			`earlyOpBegun => sdram_earlyOpBegun, -- early indicator that memory operation has begun`
269			`opBegun => sdram_opBegun, -- indicates memory read/write has begun`
270			`rdPending => sdram_rdPending, -- read operation to SDRAM is in progress`
271			`done => sdram_done, -- indicates SDRAM memory read or write operation is done`
272			`rdDone => sdram_rdDone, -- indicates SDRAM memory read operation is done`
273			`hAddr => sdram_hAddr, -- host-side address from dualport to SDRAM`
274			`hDIn => sdram_hDIn, -- test data pattern from dualport to SDRAM`
275			`hDOut => sdram_hDOut, -- SDRAM data output to dualport`
276			`status => sdram_status, -- SDRAM controller state (for diagnostics)`
277
278			`--SDRAM (External) Side`
279			`sclkfb => pin_sclkfb, -- clock feedback with added external PCB delays`
280			`sclk => pin_sclk, -- synchronized clock to external SDRAM`
281			`cke => pin_cke, -- SDRAM clock enable`
282			`cs_n => pin_cs_n, -- SDRAM chip-select`
283			`ras_n => pin_ras_n, -- SDRAM RAS`
284			`cas_n => pin_cas_n, -- SDRAM CAS`
285			`we_n => pin_we_n, -- SDRAM write-enable`
286			`ba => pin_ba, -- SDRAM bank address`
287			`sAddr => pin_sAddr, -- SDRAM address`
288			`sData => pin_sData, -- SDRAM databus`
289			`dqmh => pin_dqmh, -- SDRAM DQMH`
290			`dqml => pin_dqml -- SDRAM DQML`
291			`);`
292
293	15	cavanaug	`------------------------------------------------------------------------------------------------------------`
294	25	zuofu	`-- Instance of VGA driver, this unit generates the video signals from VRAM`
295	15	cavanaug	`------------------------------------------------------------------------------------------------------------`
296
297	2	zuofu
298	10	zuofu	`u3 : vga`
299			`generic map (`
300			`FREQ => FREQ,`
301			`CLK_DIV => VGA_CLK_DIV,`
302			`PIXEL_WIDTH => PIXEL_WIDTH,`
303			`PIXELS_PER_LINE => PIXELS_PER_LINE,`
304			`LINES_PER_FRAME => LINES_PER_FRAME,`
305			`NUM_RGB_BITS => NUM_RGB_BITS,`
306			`FIT_TO_SCREEN => FIT_TO_SCREEN`
307			`)`
308			`port map (`
309			`rst => rst_i,`
310			`clk => sdram_clk1x, -- use the resync'ed master clock so VGA generator is in sync with SDRAM`
311			`wr => rdDone0, -- write to pixel buffer when the data read from SDRAM is available`
312	13	zuofu	`pixel_data_in => pixels, -- pixel data from SDRAM`
313	10	zuofu	`full => full, -- indicates when the pixel buffer is full`
314			`eof => eof, -- indicates when the VGA generator has finished a video frame`
315			`r => pin_red, -- RGB components (output)`
316			`g => pin_green,`
317			`b => pin_blue,`
318			`hsync_n => pin_hsync_n, -- horizontal sync`
319			`vsync_n => pin_vsync_n, -- vertical sync`
320			`blank => open`
321			`);`
322	15	cavanaug
323			`------------------------------------------------------------------------------------------------------------`
324	25	zuofu	`-- instance of main blitter`
325	15	cavanaug	`------------------------------------------------------------------------------------------------------------`
326
327	25	zuofu	`u4: Blitter`
328	17	zuofu	`generic map(`
329	15	cavanaug	`FREQ => FREQ,`
330	25	zuofu	`PIPE_EN => PIPE_EN,`
331			`DATA_WIDTH => DATA_WIDTH,`
332			`ADDR_WIDTH => ADDR_WIDTH`
333	15	cavanaug	`)`
334	17	zuofu	`port map (`
335	25	zuofu	`clk =>sdram_clk1x,`
336			`rst =>blit_reset,`
337			`rd =>rd1,`
338			`wr =>wr1,`
339			`opBegun =>opBegun1,`
340			`earlyopBegun =>earlyOpBegun1,`
341			`done =>done1,`
342			`rddone =>rddone1,`
343			`rdPending =>rdPending1,`
344			`Addr =>hAddr1,`
345			`DIn =>hDIn1,`
346			`DOut =>hDOut1,`
347			`blit_begin =>blit_begin,`
348	23	zuofu	`source_address =>source_address,`
349	25	zuofu	`source_lines =>source_lines,`
350	23	zuofu	`target_address =>target_address,`
351	25	zuofu	`line_size =>line_size,`
352			`alphaOp =>alphaOp,`
353			`blit_done =>blit_done,`
354			`front_buffer =>front_buffer`
355	17	zuofu	`);`
356	15	cavanaug
357	2	zuofu	`--------------------------------------------------------------------------------------------------------------`
358			`-- End of Submodules`
359			`--------------------------------------------------------------------------------------------------------------`
360			`-- Begin Top Level Module`
361	10	zuofu
362	25	zuofu	`-- connect internal signals`
363	2	zuofu	`rst_i <= sysReset;`
364	13	zuofu	`pin_ce_n <= '1'; -- disable Flash RAM`
365	25	zuofu
366			`rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation`
367			`hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)`
368	10	zuofu	`wr0 <= '0';`
369			`hAddr0 <= std_logic_vector(vga_address);`
370	25	zuofu
371			`blit_reset <= rst_i or reset_blitter;`
372	2	zuofu
373	13	zuofu	`-- Port0 is reserved for VGA`
374	22	zuofu	`pixels <= hDOut0 when drawframe = '1' else "0000000000000000";`
375	13	zuofu
376	26	zuofu	`port_in <= pin_port_in;`
377			`port_addr <= pin_port_addr;`
378			`pin_done <= idle_r;`
379
380	25	zuofu	`source_address <= source_address_r;`
381			`line_size <= line_size_r;`
382			`target_address <= target_address_r;`
383			`source_lines <= source_lines_r;`
384			`alphaOp <= alphaOp_r;`
385	26	zuofu
386	25	zuofu	`front_buffer <= YES;--front_buffer_r;`
387
388	26	zuofu	`comb:process(state_r, port_in, port_addr, pin_start)`
389	25	zuofu	`begin`
390			`blit_begin <= NO; --default operations`
391			`reset_blitter <= NO;`
392
393			`state_x <= state_r; --default register values`
394			`source_address_x <= source_address_r;`
395			`target_address_x <= target_address_r;`
396			`source_lines_x <= source_lines_r;`
397	26	zuofu	`line_size_x <= line_size_r;`
398	25	zuofu	`alphaOp_x <= alphaOp_r;`
399			`front_buffer_x <= front_buffer_r;`
400	26	zuofu	`idle_x <= idle_r;`
401	25	zuofu
402			`case state_r is`
403			`when INIT =>`
404	26	zuofu	`idle_x <= YES;`
405	25	zuofu	`reset_blitter <= YES;`
406	26	zuofu	`state_x <= LOAD;`
407
408			`when LOAD =>`
409			`if (pin_load = YES) then`
410			`case port_addr is`
411			`when "0000" => source_address_x(23 downto 16) <= port_in;`
412			`when "0001" => source_address_x(15 downto 8) <= port_in;`
413			`when "0010" => source_address_x(7 downto 0) <= port_in;`
414			`when "0011" => target_address_x(23 downto 16) <= port_in;`
415			`when "0100" => target_address_x(15 downto 8) <= port_in;`
416			`when "0101" => target_address_x(7 downto 0) <= port_in;`
417			`when "0110" => source_lines_x (15 downto 8) <= port_in;`
418			`when "0111" => source_lines_x (7 downto 0) <= port_in;`
419			`when "1000" => line_size_x (11 downto 8) <= port_in(3 downto 0);`
420			`when "1001" => line_size_x (7 downto 0) <= port_in;`
421			`when "1010" => alphaOp_x <= port_in(0);`
422			`when others =>`
423			`end case;`
424			`end if;`
425
426			`if (pin_start = YES) then`
427			`idle_x <= NO;`
428			`state_x <= DRAW;`
429			`end if;`
430	25	zuofu
431	26	zuofu	`when DRAW =>`
432	25	zuofu	`blit_begin <= YES;`
433			`if (blit_done = YES) then`
434			`reset_blitter <= YES;`
435	26	zuofu	`idle_x <= YES;`
436			`state_x <= REST;`
437	25	zuofu	`end if;`
438
439	26	zuofu	`when REST =>`
440	25	zuofu	`reset_blitter <= YES;`
441	26	zuofu	`state_x <= LOAD;`
442	25	zuofu
443			`end case;`
444			`end process;`
445
446	10	zuofu	`-- update the SDRAM address counter`
447			`process(sdram_clk1x)`
448			`begin`
449			`if rising_edge(sdram_clk1x) then`
450	25	zuofu
451			`--VGA Related Stuff`
452			`if eof = YES then`
453	13	zuofu	`drawframe <= not drawframe; -- draw every other frame`
454	25	zuofu
455	26	zuofu	`-- reset the address at the end of a video frame depending on which buffer is the front`
456			`if (front_buffer = YES) then`
457			`vga_address <= x"000000";`
458			`else`
459			`vga_address <= x"000000"; --temporary`
460			`end if;`
461
462	25	zuofu	`elsif (earlyOpBegun0 = YES) then`
463	26	zuofu	`vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun`
464	13	zuofu	`end if;`
465	25	zuofu
466			`--reset stuff`
467			`if (sysReset = YES) then`
468			`state_r <= INIT;`
469			`end if;`
470
471			`state_r <= state_x;`
472			`source_address_r <= source_address_x;`
473			`target_address_r <= target_address_x;`
474			`source_lines_r <= source_lines_x;`
475	26	zuofu	`line_size_r <= line_size_x;`
476	25	zuofu	`alphaOp_r <= alphaOp_x;`
477	26	zuofu	`front_buffer_r <= front_buffer_x;`
478			`idle_r <= idle_x;`
479
480	25	zuofu	`end if;`
481	10	zuofu	`end process;`
482	2	zuofu
483	10	zuofu	`--process reset circuitry`
484	2	zuofu	`process(sdram_bufclk)`
485			`begin`
486			`if (rising_edge(sdram_bufclk)) then`
487			`if sdram_lock='0' then`
488			`sysReset <= '1'; -- keep in reset until DLLs start up`
489			`else`
490			`--sysReset <= '0';`
491			`sysReset <= not pin_pushbtn; -- push button will reset`
492			`end if;`
493			`end if;`
494			`end process;`
495			`end arch;`

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