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dsocek |
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-- (c) Copyright 2006, CoreTex Systems, LLC --
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-- www.coretexsys.com --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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---------------------------------------------------------------------
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----------------------------------------------------------------------
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-- Poject structure:
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-- |- tdes_top.vhd
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-- |
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-- |- des_cipher_top.vhd
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-- |- des_top.vhd
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-- |- block_top.vhd
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-- |- add_key.vhd
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-- |
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-- |- add_left.vhd
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-- |
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-- |- e_expansion_function.vhd
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-- |
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-- |- p_box.vhd
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-- |
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-- |- s_box.vhd
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-- |- s1_box.vhd
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-- |- s2_box.vhd
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-- |- s3_box.vhd
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-- |- s4_box.vhd
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-- |- s5_box.vhd
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-- |- s6_box.vhd
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-- |- s7_box.vhd
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-- |- s8_box.vhd
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-- |- key_schedule.vhd
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----------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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-- Title : s1_box
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-- Company : CoreTex Systems, LLC
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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ENTITY s1_box IS
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port (
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A: IN std_logic_VECTOR(5 downto 0);
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SPO: OUT std_logic_VECTOR(3 downto 0));
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END s1_box;
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architecture Behavioral of s1_box is
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begin
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SPO <= "1110" when A = x"0" else
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"0000" when A = x"1" else
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"0100" when A = x"2" else
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"1111" when A = x"3" else
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"1101" when A = x"4" else
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"0111" when A = x"5" else
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"0001" when A = x"6" else
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"0100" when A = x"7" else
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"0010" when A = x"8" else
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"1110" when A = x"9" else
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"1111" when A = x"A" else
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"0010" when A = x"B" else
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"1011" when A = x"C" else
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"1101" when A = x"D" else
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"1000" when A = x"E" else
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"0001" when A = x"F" else
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"0011" when A = x"10" else
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"1010" when A = x"11" else
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"1010" when A = x"12" else
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"0110" when A = x"13" else
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"0110" when A = x"14" else
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"1100" when A = x"15" else
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"1100" when A = x"16" else
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"1011" when A = x"17" else
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"0101" when A = x"18" else
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"1001" when A = x"19" else
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"1001" when A = x"1A" else
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"0101" when A = x"1B" else
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"0000" when A = x"1C" else
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"0011" when A = x"1D" else
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"0111" when A = x"1E" else
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"1000" when A = x"1F" else
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"0100" when A = x"20" else
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"1111" when A = x"21" else
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"0001" when A = x"22" else
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"1100" when A = x"23" else
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"1110" when A = x"24" else
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"1000" when A = x"25" else
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"1000" when A = x"26" else
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"0010" when A = x"27" else
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"1101" when A = x"28" else
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"0100" when A = x"29" else
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"0110" when A = x"2A" else
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"1001" when A = x"2B" else
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"0010" when A = x"2C" else
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"0001" when A = x"2D" else
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"1011" when A = x"2E" else
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"0111" when A = x"2F" else
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"1111" when A = x"30" else
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"0101" when A = x"31" else
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"1100" when A = x"32" else
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"1011" when A = x"33" else
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"1001" when A = x"34" else
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"0011" when A = x"35" else
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"0111" when A = x"36" else
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"1110" when A = x"37" else
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"0011" when A = x"38" else
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"1010" when A = x"39" else
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"1010" when A = x"3A" else
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"0000" when A = x"3B" else
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"0101" when A = x"3C" else
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"0110" when A = x"3D" else
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"0000" when A = x"3E" else
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"1101" when A = x"3F" else
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"1101";
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END Behavioral;
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