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[/] [3des_vhdl/] [trunk/] [VHDL/] [s_box.vhd] - Blame information for rev 4

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1 2 dsocek 
---------------------------------------------------------------------
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--                              (c) Copyright 2006, CoreTex Systems, LLC                                         --
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--                                 www.coretexsys.com                        --
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--                                                                       --
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--              This source file may be used and distributed without         --
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--              restriction provided that this copyright statement is not    --
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--              removed from the file and that any derivative work contains  --
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--              the original copyright notice and the associated disclaimer. --
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--                                                                       --
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--                  THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY      --
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--              EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED    --
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--              TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS    --
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--              FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR       --
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--              OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,          --
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--              INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES     --
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--              (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE    --
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--              GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR         --
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--              BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF   --
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--              LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT   --
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--              (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT   --
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--              OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE          --
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--              POSSIBILITY OF SUCH DAMAGE.                                  --
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--                                                                                                                                                                               --
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---------------------------------------------------------------------
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----------------------------------------------------------------------
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-- Poject structure:
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--  |- tdes_top.vhd
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--  |
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--    |- des_cipher_top.vhd
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--    |- des_top.vhd
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--      |- block_top.vhd
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--        |- add_key.vhd
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--        |
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--        |- add_left.vhd
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--        |
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--                              |- e_expansion_function.vhd
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--                              |
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--                              |- p_box.vhd
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--                              |
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--                              |- s_box.vhd
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--            |- s1_box.vhd
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--            |- s2_box.vhd
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--            |- s3_box.vhd
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--            |- s4_box.vhd
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--            |- s5_box.vhd
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--            |- s6_box.vhd
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--            |- s7_box.vhd
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--            |- s8_box.vhd
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--    |- key_schedule.vhd
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----------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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-- Title       : s_box
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-- Company     : CoreTex Systems, LLC
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity s_box is
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port(
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                block0_in: in std_logic_vector(5 downto 0);
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                        block1_in: in std_logic_vector(5 downto 0);
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                        block2_in: in std_logic_vector(5 downto 0);
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                        block3_in: in std_logic_vector(5 downto 0);
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                        block4_in: in std_logic_vector(5 downto 0);
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                        block5_in: in std_logic_vector(5 downto 0);
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                        block6_in: in std_logic_vector(5 downto 0);
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                        block7_in: in std_logic_vector(5 downto 0);
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                        x0_out: out std_logic_vector(3 downto 0);
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                        x1_out: out std_logic_vector(3 downto 0);
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                        x2_out: out std_logic_vector(3 downto 0);
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                        x3_out: out std_logic_vector(3 downto 0);
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                        x4_out: out std_logic_vector(3 downto 0);
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                        x5_out: out std_logic_vector(3 downto 0);
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                        x6_out: out std_logic_vector(3 downto 0);
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                        x7_out: out std_logic_vector(3 downto 0)
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        );
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end s_box;
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architecture Behavioral of s_box is
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component s1_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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component s2_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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component s3_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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component s4_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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component s5_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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component s6_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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component s7_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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component s8_box
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        port(
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        a: in  std_logic_VECTOR(5 downto 0);
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        spo: out std_logic_VECTOR(3 downto 0)
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        );
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end component;
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begin
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S1 : s1_box
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        port map (
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                a => block0_in,
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                spo => x0_out
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);
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S2 : s2_box
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        port map (
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                a => block1_in,
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                spo => x1_out
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);
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S3 : s3_box
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        port map (
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                a => block2_in,
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                spo => x2_out
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);
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S4 : s4_box
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        port map (
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                a => block3_in,
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                spo => x3_out
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);
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S5 : s5_box
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        port map (
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                a => block4_in,
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                spo => x4_out
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);
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S6 : s6_box
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        port map (
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                a => block5_in,
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                spo => x5_out
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);
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S7 : s7_box
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        port map (
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                a => block6_in,
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                spo => x6_out
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);
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S8 : s8_box
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        port map (
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                a => block7_in,
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                spo => x7_out
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);
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end Behavioral;

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