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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 10

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Changelong
----------
22.06.14
--------
 
- decoders.v : fixed wrong left/right/dest paths for several extended, page 2, 3 opcodes.
- MC6809_cpu.v : fixed jsr extended, indexed
 
06.02.14
--------
 
- regblock.v : dropped double write of PC
- MC6809_cpu.v : fixed loading of new PC from reset vector, rel8 displacement calculation.
 
06.01.14
--------
 
- decoders.v : added registered outputs for the source/destination address registers
 
05.01.14
--------
 
- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC
- decoders.v : fixed destination for BIT
- defs.v : reduced the number of ALU opcodes
- alu16.v : reduced the number of ALU opcodes, fused BIT with AND, CMP with SUB
 
01.01.14
--------
 
- alu16.v : the alu has been bronken in two units
- MC6809_cpu.v : added CWAI states and decoding
- decodres.v : added CWAI decoding
 
31.12.13
--------
 
- Implemented TFR/EXG
- MC6809_cpu.v: Added one more state to execute TFR or EXG
- decoders.v: added source/dest for TFR and EXG
- regblock.v : added second write path to the registers for TFR&EXG
- defs.v defined new SEQ_TFREXG for tfr&exg execution
 
30.12.13
--------
 
- Fixed increment/decrement of the stack pointer
 
- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states
                Added eamem source to the left alu data path to check for zero in the ea (leax/leay)
 
29.12.13
--------
 
- Fixed wrong byte in SEQ_MEM_WRITE_H
- Fixed unaffected Z flag for LEAX/LEAY
- Moved increment of pc from FETCH_2 to FETCH_1
- Fixed CMPA/CMPB/CMPX, they don't write a register back
- Fixed late write of pc
 
- decoders.v: Merged separated write_dest_x into one wire
              Added a source_size wire to indicate the width of the source argument
              Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY
 
- MC6809_cpu.v: Dropped checks for source size from the individual states and moved
                into SEQ_MEM_READ_H
                Merged write flags into k_dest_write
 
- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected
 
- defs.v : added a LEA define to the ALU section

Line No.	Rev	Author	Line
1	4	ale500	`Changelong`
2			`----------`
3	10	ale500	`22.06.14`
4			`--------`
5	4	ale500
6	10	ale500	`- decoders.v : fixed wrong left/right/dest paths for several extended, page 2, 3 opcodes.`
7			`- MC6809_cpu.v : fixed jsr extended, indexed`
8
9			`06.02.14`
10			`--------`
11
12			`- regblock.v : dropped double write of PC`
13			`- MC6809_cpu.v : fixed loading of new PC from reset vector, rel8 displacement calculation.`
14
15	9	ale500	`06.01.14`
16			`--------`
17
18			`- decoders.v : added registered outputs for the source/destination address registers`
19
20	7	ale500	`05.01.14`
21			`--------`
22
23			`- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC`
24	9	ale500	`- decoders.v : fixed destination for BIT`
25			`- defs.v : reduced the number of ALU opcodes`
26			`- alu16.v : reduced the number of ALU opcodes, fused BIT with AND, CMP with SUB`
27	7	ale500
28	6	ale500	`01.01.14`
29			`--------`
30
31			`- alu16.v : the alu has been bronken in two units`
32			`- MC6809_cpu.v : added CWAI states and decoding`
33			`- decodres.v : added CWAI decoding`
34
35	5	ale500	`31.12.13`
36			`--------`
37
38			`- Implemented TFR/EXG`
39			`- MC6809_cpu.v: Added one more state to execute TFR or EXG`
40			`- decoders.v: added source/dest for TFR and EXG`
41			`- regblock.v : added second write path to the registers for TFR&EXG`
42			`- defs.v defined new SEQ_TFREXG for tfr&exg execution`
43
44	4	ale500	`30.12.13`
45			`--------`
46
47			`- Fixed increment/decrement of the stack pointer`
48
49			`- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states`
50			`Added eamem source to the left alu data path to check for zero in the ea (leax/leay)`
51
52			`29.12.13`
53			`--------`
54
55			`- Fixed wrong byte in SEQ_MEM_WRITE_H`
56			`- Fixed unaffected Z flag for LEAX/LEAY`
57			`- Moved increment of pc from FETCH_2 to FETCH_1`
58			`- Fixed CMPA/CMPB/CMPX, they don't write a register back`
59			`- Fixed late write of pc`
60
61			`- decoders.v: Merged separated write_dest_x into one wire`
62			`Added a source_size wire to indicate the width of the source argument`
63			`Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY`
64
65			`- MC6809_cpu.v: Dropped checks for source size from the individual states and moved`
66			`into SEQ_MEM_READ_H`
67			`Merged write flags into k_dest_write`
68
69			`- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected`
70
71			`- defs.v : added a LEA define to the ALU section`

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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 10