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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 11

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Changelong
----------
 
02.07.14
--------
- decoders.v : fixed dec, fixed inc (didn't read before write), fixed clr for ea direct, extended, indexed
               added a path with the decoded sources/destination for the decode stage
- MC6809_cpu.v : implemented two paths for source/dest from the decoder
- rumsim.bat : added batch file for simulation
 
22.06.14
--------
 
- decoders.v : fixed wrong left/right/dest paths for several extended, page 2, 3 opcodes.
- MC6809_cpu.v : fixed jsr extended, indexed
 
06.02.14
--------
 
- regblock.v : dropped double write of PC
- MC6809_cpu.v : fixed loading of new PC from reset vector, rel8 displacement calculation.
 
06.01.14
--------
 
- decoders.v : added registered outputs for the source/destination address registers
 
05.01.14
--------
 
- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC
- decoders.v : fixed destination for BIT
- defs.v : reduced the number of ALU opcodes
- alu16.v : reduced the number of ALU opcodes, fused BIT with AND, CMP with SUB
 
01.01.14
--------
 
- alu16.v : the alu has been bronken in two units
- MC6809_cpu.v : added CWAI states and decoding
- decodres.v : added CWAI decoding
 
31.12.13
--------
 
- Implemented TFR/EXG
- MC6809_cpu.v: Added one more state to execute TFR or EXG
- decoders.v: added source/dest for TFR and EXG
- regblock.v : added second write path to the registers for TFR&EXG
- defs.v defined new SEQ_TFREXG for tfr&exg execution
 
30.12.13
--------
 
- Fixed increment/decrement of the stack pointer
 
- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states
                Added eamem source to the left alu data path to check for zero in the ea (leax/leay)
 
29.12.13
--------
 
- Fixed wrong byte in SEQ_MEM_WRITE_H
- Fixed unaffected Z flag for LEAX/LEAY
- Moved increment of pc from FETCH_2 to FETCH_1
- Fixed CMPA/CMPB/CMPX, they don't write a register back
- Fixed late write of pc
 
- decoders.v: Merged separated write_dest_x into one wire
              Added a source_size wire to indicate the width of the source argument
              Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY
 
- MC6809_cpu.v: Dropped checks for source size from the individual states and moved
                into SEQ_MEM_READ_H
                Merged write flags into k_dest_write
 
- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected
 
- defs.v : added a LEA define to the ALU section

Line No.	Rev	Author	Line
1	4	ale500	`Changelong`
2			`----------`
3	11	ale500
4			`02.07.14`
5			`--------`
6			`- decoders.v : fixed dec, fixed inc (didn't read before write), fixed clr for ea direct, extended, indexed`
7			`added a path with the decoded sources/destination for the decode stage`
8			`- MC6809_cpu.v : implemented two paths for source/dest from the decoder`
9			`- rumsim.bat : added batch file for simulation`
10
11	10	ale500	`22.06.14`
12			`--------`
13	4	ale500
14	10	ale500	`- decoders.v : fixed wrong left/right/dest paths for several extended, page 2, 3 opcodes.`
15			`- MC6809_cpu.v : fixed jsr extended, indexed`
16
17			`06.02.14`
18			`--------`
19
20			`- regblock.v : dropped double write of PC`
21			`- MC6809_cpu.v : fixed loading of new PC from reset vector, rel8 displacement calculation.`
22
23	9	ale500	`06.01.14`
24			`--------`
25
26			`- decoders.v : added registered outputs for the source/destination address registers`
27
28	7	ale500	`05.01.14`
29			`--------`
30
31			`- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC`
32	9	ale500	`- decoders.v : fixed destination for BIT`
33			`- defs.v : reduced the number of ALU opcodes`
34			`- alu16.v : reduced the number of ALU opcodes, fused BIT with AND, CMP with SUB`
35	7	ale500
36	6	ale500	`01.01.14`
37			`--------`
38
39			`- alu16.v : the alu has been bronken in two units`
40			`- MC6809_cpu.v : added CWAI states and decoding`
41			`- decodres.v : added CWAI decoding`
42
43	5	ale500	`31.12.13`
44			`--------`
45
46			`- Implemented TFR/EXG`
47			`- MC6809_cpu.v: Added one more state to execute TFR or EXG`
48			`- decoders.v: added source/dest for TFR and EXG`
49			`- regblock.v : added second write path to the registers for TFR&EXG`
50			`- defs.v defined new SEQ_TFREXG for tfr&exg execution`
51
52	4	ale500	`30.12.13`
53			`--------`
54
55			`- Fixed increment/decrement of the stack pointer`
56
57			`- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states`
58			`Added eamem source to the left alu data path to check for zero in the ea (leax/leay)`
59
60			`29.12.13`
61			`--------`
62
63			`- Fixed wrong byte in SEQ_MEM_WRITE_H`
64			`- Fixed unaffected Z flag for LEAX/LEAY`
65			`- Moved increment of pc from FETCH_2 to FETCH_1`
66			`- Fixed CMPA/CMPB/CMPX, they don't write a register back`
67			`- Fixed late write of pc`
68
69			`- decoders.v: Merged separated write_dest_x into one wire`
70			`Added a source_size wire to indicate the width of the source argument`
71			`Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY`
72
73			`- MC6809_cpu.v: Dropped checks for source size from the individual states and moved`
74			`into SEQ_MEM_READ_H`
75			`Merged write flags into k_dest_write`
76
77			`- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected`
78
79			`- defs.v : added a LEA define to the ALU section`

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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 11