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ale500 |
/*
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*
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* MC6809/HD6309 Compatible code
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* (c) 2013 R.A. Paz Schmidt
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* distributed under the terms of the Lesser GPL, see LICENSE.TXT
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*
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*/
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`include "defs.v"
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module MC6809_cpu(
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input wire cpu_clk,
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input wire cpu_reset,
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input wire cpu_nmi_n,
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input wire cpu_irq_n,
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input wire cpu_firq_n,
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output wire [5:0] cpu_state_o,
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output wire cpu_we_o,
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output wire cpu_oe_o,
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output wire [15:0] cpu_addr_o,
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input wire [7:0] cpu_data_i,
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10 |
ale500 |
output wire [7:0] cpu_data_o,
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input wire debug_clk,
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output wire debug_data_o // serial debug info, 64 bit shift register
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2 |
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);
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wire k_reset;
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5 |
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reg [7:0] k_opcode, k_postbyte, k_ind_ea; /* all bytes of an instruction */
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6 |
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reg [7:0] k_pp_regs; // push/pull registers to process
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reg [3:0] k_pp_active_reg; // push/pull active register
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2 |
ale500 |
reg [7:0] k_memhi, k_memlo, k_cpu_data_o; /* operand read from memory */
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reg [7:0] k_ofslo, k_ofshi, k_eahi, k_ealo;
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reg [5:0] state, // state of the main state machine
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next_state, // next state to exit to from the read from [PC] state machine
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next_mem_state, // next state to exit to from the read from memory state machine
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5 |
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next_push_state; // next state to exit to from push multiple state machine
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reg k_write_tfr, k_write_exg;
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4 |
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reg k_cpu_oe, k_cpu_we, k_inc_pc;
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12 |
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reg k_indirect_loaded; // set when in indirect indexed and the address has been loaded
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2 |
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reg [15:0] k_cpu_addr, k_new_pc;
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16 |
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reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
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reg k_mul_cnt; // multiplier couner
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reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
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reg k_write_post_incdec; // asserted when in the last write cycle or in write back for loads
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reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
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/****
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* Decoder outputs
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*/
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wire [2:0] dec_o_p1_mode; // addressing mode
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wire dec_o_use_s; // signals when S should be used instead of U
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7 |
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wire dec_o_alu_size; /* size of the result of an alu opcode (destination to be written) */
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14 |
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wire op_SYNC, op_EXG, op_TFR, op_RTS, op_RTI, op_CWAI;
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wire op_MUL, op_SWI, op_PUSH, op_PULL, op_LEA, op_JMP, op_JSR;
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2 |
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/* ea decoder */
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16 |
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wire dec_o_ea_ofs8, dec_o_ea_ofs16, dec_o_ea_wpost, dec_o_ea_ofs5, dec_o_ea_indirect;
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wire [3:0] dec_o_eabase, dec_o_eaidx;
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/* alu k_opcode decoder */
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wire [4:0] dec_o_alu_opcode;
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wire [1:0] dec_o_right_path_mod; /* Modifier for alu's right path input */
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/* register decoder */
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wire dec_o_wdest, dec_o_source_size, dec_o_write_flags;
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wire [3:0] dec_o_left_path_addr, dec_o_right_path_addr, dec_o_dest_reg_addr;
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// latched versions, used for muxes, regs and alu
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wire [3:0] dec_lo_left_path_addr, dec_lo_right_path_addr, dec_lo_dest_reg_addr;
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wire [1:0] dec_o_left_path_memtype, dec_o_right_path_memtype, dec_o_dest_memtype;
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wire [1:0] dec_lo_left_path_memtype, dec_lo_right_path_memtype, dec_lo_dest_memtype;
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wire dec_o_operand_read, dec_o_operand_write;
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/* test condition */
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wire dec_o_cond_taken;
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/* ALU outputs */
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wire [15:0] alu_o_result;
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wire [7:0] alu_o_CCR;
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/* Register Module outputs */
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wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
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wire [7:0] regs_o_dp;
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wire [15:0] regs_o_pc;
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wire [7:0] regs_o_CCR;
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/* Data Muxes */
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reg [3:0] datamux_o_dest_reg_addr, datamux_o_alu_in_left_path_addr;
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reg [15:0] datamux_o_alu_in_left_path_data, datamux_o_alu_in_right_path_data, datamux_o_dest;
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5 |
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reg k_p2_valid, k_p3_valid; /* 1 when k_postbyte has been loaded for page 2 or page 3 */
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2 |
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reg [2:0] k_mem_state; /* Memory mini-state machine */
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/*
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* Interrupt sync registers
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*/
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2 |
ale500 |
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reg [2:0] k_reg_nmi, k_reg_irq, k_reg_firq;
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wire k_nmi_req, k_firq_req, k_irq_req;
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assign k_nmi_req = k_reg_nmi[2] & k_reg_nmi[1];
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assign k_firq_req = k_reg_firq[2] & k_reg_firq[1];
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assign k_irq_req = k_reg_irq[2] & k_reg_irq[1];
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10 |
ale500 |
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/* Debug */
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`ifdef SERIAL_DEBUG
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reg [63:0] debug_r;
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always @(posedge debug_clk)
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begin
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if (cpu_clk)
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begin
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debug_r[15:0] <= regs_o_pc;
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debug_r[23:16] <= k_opcode;
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debug_r[27:24] <= datamux_o_alu_in_left_path_addr;
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debug_r[31:28] <= dec_o_right_path_addr;
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debug_r[35:32] <= datamux_o_dest_reg_addr;
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16 |
ale500 |
debug_r[39:36] <= { 3'b0, k_write_pc }; //regs_o_CCR[3:0];
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10 |
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debug_r[55:40] <= { k_memhi,k_memlo };//k_new_pc;
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debug_r[63:56] <= cpu_data_i;
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end
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else
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debug_r <= debug_r << 1; // shift out
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end
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assign debug_data_o = debug_r[63];
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`else
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assign debug_data_o = 1'b0;
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`endif
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6 |
ale500 |
alu alu(
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.clk_in(cpu_clk),
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2 |
ale500 |
.a_in(datamux_o_alu_in_left_path_data),
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.b_in(datamux_o_alu_in_right_path_data),
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.CCR(regs_o_CCR), /* flags */
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6 |
ale500 |
.opcode_in(dec_o_alu_opcode), /* ALU k_opcode */
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.sz_in(dec_o_alu_size),
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2 |
ale500 |
.q_out(alu_o_result), /* ALU result */
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.CCRo(alu_o_CCR)
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6 |
ale500 |
);
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2 |
ale500 |
regblock regs(
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ale500 |
.clk_in(cpu_clk),
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2 |
ale500 |
.path_left_addr(datamux_o_alu_in_left_path_addr),
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11 |
ale500 |
.path_right_addr(dec_lo_right_path_addr),
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5 |
ale500 |
.write_reg_addr(datamux_o_dest_reg_addr),
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7 |
ale500 |
.exg_dest_r(k_postbyte[7:4]),
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2 |
ale500 |
.eapostbyte( k_ind_ea ),
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.offset16({ k_ofshi, k_ofslo }),
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4 |
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.write_reg(k_write_dest),
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5 |
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.write_tfr(k_write_tfr),
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.write_exg(k_write_exg),
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2 |
ale500 |
.write_post(k_write_post_incdec),
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.write_pc(k_write_pc),
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.inc_pc(k_inc_pc),
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.inc_su(k_inc_su),
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.dec_su(k_dec_su),
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.use_s(dec_o_use_s),
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.data_w(datamux_o_dest),
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.new_pc(k_new_pc),
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.CCR_in(alu_o_CCR),
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.write_flags(dec_o_write_flags & (state == `SEQ_GRAL_WBACK)),
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.set_e(k_set_e),
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.clear_e(k_clear_e),
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.CCR_o(regs_o_CCR),
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.path_left_data(regs_o_left_path_data),
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.path_right_data(regs_o_right_path_data),
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9 |
ale500 |
.eamem_addr_o(regs_o_eamem_addr),
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2 |
ale500 |
.reg_pc(regs_o_pc),
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.reg_dp(regs_o_dp),
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.reg_su(regs_o_su)
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);
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16 |
ale500 |
decoders decs(
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.clk_in(cpu_clk),
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.opcode(k_opcode),
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5 |
ale500 |
.postbyte0(k_postbyte),
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2 |
ale500 |
.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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16 |
ale500 |
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.path_left_addr_o(dec_o_left_path_addr),
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9 |
ale500 |
.path_right_addr_o(dec_o_right_path_addr),
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.dest_reg_o(dec_o_dest_reg_addr),
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11 |
ale500 |
.path_left_addr_lo(dec_lo_left_path_addr),
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.path_right_addr_lo(dec_lo_right_path_addr),
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.dest_reg_lo(dec_lo_dest_reg_addr),
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4 |
ale500 |
.write_dest(dec_o_wdest),
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.source_size(dec_o_source_size),
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16 |
ale500 |
.result_size(dec_o_alu_size),
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.path_left_memtype_o(dec_o_left_path_memtype),
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.path_right_memtype_o(dec_o_right_path_memtype),
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.dest_memtype_o(dec_o_dest_memtype),
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.path_left_memtype_lo(dec_lo_left_path_memtype),
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.path_right_memtype_lo(dec_lo_right_path_memtype),
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.dest_memtype_lo(dec_lo_dest_memtype),
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.operand_read_o(dec_o_operand_read),
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.operand_write_o(dec_o_operand_write),
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2 |
ale500 |
.mode(dec_o_p1_mode),
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| 192 |
14 |
ale500 |
.op_SYNC(op_SYNC),
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.op_EXG (op_EXG ),
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.op_TFR (op_TFR ),
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.op_RTS (op_RTS ),
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.op_RTI (op_RTI ),
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.op_CWAI(op_CWAI),
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.op_MUL (op_MUL ),
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.op_SWI (op_SWI ),
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.op_PUSH(op_PUSH),
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.op_PULL(op_PULL),
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.op_LEA (op_LEA ),
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.op_JSR (op_JSR ),
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.op_JMP (op_JMP ),
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16 |
ale500 |
.use_s(dec_o_use_s),
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.alu_opcode(dec_o_alu_opcode),
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.dest_flags_o(dec_o_write_flags)
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);
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2 |
ale500 |
decode_ea dec_ea(
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| 211 |
16 |
ale500 |
.eapostbyte( k_ind_ea ),
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| 212 |
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.eabase_o(dec_o_eabase), // base register
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| 213 |
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.eaindex_o(dec_o_eaidx), // index register
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| 214 |
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.ea_ofs5_o(dec_o_ea_ofs5),
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.ea_ofs8_o(dec_o_ea_ofs8),
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.ea_ofs16_o(dec_o_ea_ofs16),
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.ea_is_indirect_o(dec_o_ea_indirect),
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.ea_write_back_o(dec_o_ea_wpost)
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| 219 |
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);
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| 220 |
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| 221 |
2 |
ale500 |
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| 222 |
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/* Condition decoder */
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| 223 |
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test_condition test_cond(
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| 224 |
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.opcode(k_opcode),
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| 225 |
5 |
ale500 |
.postbyte0(k_postbyte),
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| 226 |
2 |
ale500 |
.page2_valid(k_p2_valid),
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| 227 |
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.CCR(regs_o_CCR),
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| 228 |
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.cond_taken(dec_o_cond_taken)
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| 229 |
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);
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| 230 |
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| 231 |
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/* Module IO */
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| 232 |
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| 233 |
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assign cpu_oe_o = k_cpu_oe; // we latch on the rising edge
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| 234 |
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assign cpu_we_o = k_cpu_we;
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| 235 |
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assign cpu_addr_o = k_cpu_addr;
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| 236 |
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assign cpu_data_o = k_cpu_data_o;
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| 237 |
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assign k_reset = cpu_reset;
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| 238 |
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assign cpu_state_o = state;
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| 239 |
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| 240 |
16 |
ale500 |
wire cpu_dtack_i = 1;
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| 241 |
2 |
ale500 |
/* Left Register read mux
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| 242 |
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*/
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| 243 |
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always @(*)
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| 244 |
6 |
ale500 |
begin
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| 245 |
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if (k_pp_active_reg != `RN_INV)
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| 246 |
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datamux_o_alu_in_left_path_addr = k_pp_active_reg;
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| 247 |
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else
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| 248 |
11 |
ale500 |
datamux_o_alu_in_left_path_addr = dec_lo_left_path_addr;
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| 249 |
2 |
ale500 |
end
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| 250 |
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| 251 |
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/* Destination register address MUX
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| 252 |
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*/
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| 253 |
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always @(*)
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| 254 |
6 |
ale500 |
begin
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| 255 |
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if (k_pp_active_reg != `RN_INV)
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| 256 |
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datamux_o_dest_reg_addr = k_pp_active_reg;
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| 257 |
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else
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| 258 |
11 |
ale500 |
datamux_o_dest_reg_addr = dec_lo_dest_reg_addr;
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| 259 |
2 |
ale500 |
end
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| 260 |
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| 261 |
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/* Destination register data mux
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| 262 |
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* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
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| 263 |
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*
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| 264 |
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*/
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| 265 |
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always @(*)
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| 266 |
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begin
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| 267 |
14 |
ale500 |
if (op_PULL | op_RTS | op_RTI) // destination register
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| 268 |
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datamux_o_dest = { k_memhi, k_memlo };
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| 269 |
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else
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| 270 |
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if (op_LEA)
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| 271 |
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begin
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| 272 |
4 |
ale500 |
if (dec_o_ea_indirect)// & dec_o_alu_size)
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| 273 |
2 |
ale500 |
datamux_o_dest = { k_memhi, k_memlo };
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| 274 |
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else
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| 275 |
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datamux_o_dest = regs_o_eamem_addr;
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| 276 |
14 |
ale500 |
end
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| 277 |
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else
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| 278 |
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datamux_o_dest = alu_o_result;
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| 279 |
2 |
ale500 |
end
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| 280 |
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| 281 |
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/* ALU left input mux */
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| 282 |
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| 283 |
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always @(*)
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| 284 |
|
|
begin
|
| 285 |
16 |
ale500 |
if (dec_lo_left_path_memtype == `MT_BYTE)
|
| 286 |
2 |
ale500 |
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
| 287 |
|
|
else
|
| 288 |
14 |
ale500 |
if (op_LEA)
|
| 289 |
|
|
begin
|
| 290 |
|
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
| 291 |
|
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
| 292 |
|
|
else
|
| 293 |
|
|
datamux_o_alu_in_left_path_data = regs_o_eamem_addr;
|
| 294 |
|
|
end
|
| 295 |
|
|
else
|
| 296 |
2 |
ale500 |
datamux_o_alu_in_left_path_data = regs_o_left_path_data;
|
| 297 |
4 |
ale500 |
end
|
| 298 |
|
|
/* PC as destination from jmp/bsr mux */
|
| 299 |
|
|
always @(*)
|
| 300 |
|
|
begin
|
| 301 |
|
|
k_new_pc = { k_memhi,k_memlo }; // used to fetch reset vector
|
| 302 |
16 |
ale500 |
case (dec_o_p1_mode)
|
| 303 |
|
|
`REL16: k_new_pc = regs_o_pc + { k_memhi,k_memlo };
|
| 304 |
|
|
`REL8: k_new_pc = regs_o_pc + { {8{k_memlo[7]}}, k_memlo };
|
| 305 |
|
|
`EXTENDED: k_new_pc = { k_eahi,k_ealo };
|
| 306 |
|
|
`DIRECT: k_new_pc = { regs_o_dp, k_ealo };
|
| 307 |
|
|
`INDEXED:
|
| 308 |
|
|
if (dec_o_ea_indirect)
|
| 309 |
|
|
k_new_pc = { k_memhi,k_memlo };
|
| 310 |
|
|
else
|
| 311 |
|
|
k_new_pc = regs_o_eamem_addr;
|
| 312 |
|
|
default:
|
| 313 |
|
|
k_new_pc = { k_memhi,k_memlo }; // used to fetch reset vector
|
| 314 |
|
|
endcase
|
| 315 |
2 |
ale500 |
end
|
| 316 |
|
|
/* ALU right input mux */
|
| 317 |
|
|
always @(*)
|
| 318 |
|
|
begin
|
| 319 |
16 |
ale500 |
datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
| 320 |
|
|
if ((dec_lo_right_path_memtype == `MT_NONE) &&
|
| 321 |
|
|
(dec_o_p1_mode != `IMMEDIATE))
|
| 322 |
|
|
// datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
| 323 |
|
|
//else
|
| 324 |
|
|
datamux_o_alu_in_right_path_data = regs_o_right_path_data;
|
| 325 |
|
|
// `MT_BYTE, `MT_WORD:
|
| 326 |
|
|
// datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
| 327 |
|
|
// endcase
|
| 328 |
2 |
ale500 |
end
|
| 329 |
|
|
|
| 330 |
6 |
ale500 |
always @(posedge cpu_clk or posedge k_reset)
|
| 331 |
2 |
ale500 |
begin
|
| 332 |
|
|
if (k_reset == 1'b1)
|
| 333 |
|
|
begin
|
| 334 |
|
|
state <= `SEQ_COLDRESET;
|
| 335 |
|
|
k_reg_nmi <= 0;
|
| 336 |
|
|
k_reg_firq <= 0;
|
| 337 |
|
|
k_reg_irq <= 0;
|
| 338 |
|
|
end
|
| 339 |
|
|
else
|
| 340 |
|
|
begin
|
| 341 |
14 |
ale500 |
/* Interrupt recognition and acknowledge */
|
| 342 |
2 |
ale500 |
if (!k_reg_nmi[2])
|
| 343 |
|
|
k_reg_nmi <= { k_reg_nmi[1:0], cpu_nmi_n };
|
| 344 |
|
|
if (!k_reg_irq[2])
|
| 345 |
|
|
k_reg_irq <= { k_reg_irq[1:0], cpu_irq_n };
|
| 346 |
|
|
if (!k_reg_firq[2])
|
| 347 |
|
|
k_reg_firq <= { k_reg_firq[1:0], cpu_firq_n };
|
| 348 |
|
|
/* modifier registers */
|
| 349 |
|
|
if (k_inc_pc)
|
| 350 |
|
|
k_inc_pc <= 0;
|
| 351 |
|
|
if (k_write_pc)
|
| 352 |
|
|
k_write_pc <= 0;
|
| 353 |
|
|
if (k_cpu_we)
|
| 354 |
|
|
k_cpu_we <= 0;
|
| 355 |
|
|
if (k_cpu_oe)
|
| 356 |
|
|
k_cpu_oe <= 0;
|
| 357 |
|
|
if (k_write_post_incdec)
|
| 358 |
|
|
k_write_post_incdec <= 0;
|
| 359 |
|
|
if (k_dec_su)
|
| 360 |
|
|
k_dec_su <= 0;
|
| 361 |
|
|
if (k_inc_su)
|
| 362 |
|
|
k_inc_su <= 0;
|
| 363 |
|
|
if (k_set_e)
|
| 364 |
|
|
k_set_e <= 0;
|
| 365 |
|
|
if (k_clear_e)
|
| 366 |
4 |
ale500 |
k_clear_e <= 0;
|
| 367 |
|
|
if (k_write_dest)
|
| 368 |
5 |
ale500 |
k_write_dest <= 0;
|
| 369 |
|
|
if (k_write_exg)
|
| 370 |
|
|
k_write_exg <= 0;
|
| 371 |
|
|
if (k_write_tfr)
|
| 372 |
|
|
k_write_tfr <= 0;
|
| 373 |
2 |
ale500 |
case (state)
|
| 374 |
|
|
`SEQ_COLDRESET:
|
| 375 |
4 |
ale500 |
begin
|
| 376 |
|
|
k_forced_mem_size <= 1;
|
| 377 |
2 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 378 |
|
|
k_eahi <= 8'hff;
|
| 379 |
|
|
k_ealo <= 8'hfe;
|
| 380 |
16 |
ale500 |
next_mem_state <= `SEQ_LOADPC;
|
| 381 |
|
|
k_opcode <= 8'h15; // force the decoder for NONE, used in memory access
|
| 382 |
2 |
ale500 |
end
|
| 383 |
|
|
`SEQ_NMI:
|
| 384 |
|
|
begin
|
| 385 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 386 |
7 |
ale500 |
k_reg_nmi <= 3'h0;
|
| 387 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfffc;
|
| 388 |
|
|
k_pp_regs <= 8'hff;
|
| 389 |
|
|
k_set_e <= 1;
|
| 390 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 391 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 392 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 393 |
|
|
end
|
| 394 |
|
|
`SEQ_SWI:
|
| 395 |
|
|
begin
|
| 396 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 397 |
2 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 398 |
|
|
{ k_eahi, k_ealo } <= 16'hfffa;
|
| 399 |
|
|
k_pp_regs <= 8'hff;
|
| 400 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 401 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 402 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 403 |
|
|
k_set_e <= 1;
|
| 404 |
|
|
end
|
| 405 |
|
|
`SEQ_IRQ:
|
| 406 |
|
|
begin
|
| 407 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 408 |
7 |
ale500 |
k_reg_irq <= 3'h0;
|
| 409 |
2 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 410 |
|
|
{ k_eahi, k_ealo } <= 16'hfff8;
|
| 411 |
|
|
k_pp_regs <= 8'hff;
|
| 412 |
|
|
next_mem_state <= `SEQ_PREPUSH;
|
| 413 |
|
|
k_set_e <= 1;
|
| 414 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 415 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 416 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 417 |
|
|
end
|
| 418 |
|
|
`SEQ_FIRQ:
|
| 419 |
|
|
begin
|
| 420 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 421 |
7 |
ale500 |
k_reg_firq <= 3'h0;
|
| 422 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfff6;
|
| 423 |
|
|
k_pp_regs <= 8'h81; // PC & CC
|
| 424 |
|
|
k_clear_e <= 1;
|
| 425 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 426 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 427 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 428 |
|
|
end
|
| 429 |
|
|
`SEQ_SWI2:
|
| 430 |
|
|
begin
|
| 431 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 432 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfff4;
|
| 433 |
|
|
k_pp_regs <= 8'hff;
|
| 434 |
|
|
k_set_e <= 1;
|
| 435 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 436 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 437 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 438 |
|
|
end
|
| 439 |
|
|
`SEQ_SWI3:
|
| 440 |
|
|
begin
|
| 441 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 442 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfff2;
|
| 443 |
|
|
k_pp_regs <= 8'hff;
|
| 444 |
|
|
k_set_e <= 1;
|
| 445 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 446 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 447 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 448 |
|
|
end
|
| 449 |
|
|
`SEQ_UNDEF:
|
| 450 |
|
|
begin
|
| 451 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 452 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfff0;
|
| 453 |
|
|
k_pp_regs <= 8'hff;
|
| 454 |
|
|
k_set_e <= 1;
|
| 455 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 456 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 457 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 458 |
|
|
end
|
| 459 |
|
|
`SEQ_LOADPC: /* loads the PC with the address taken from the reset vector */
|
| 460 |
|
|
begin
|
| 461 |
|
|
$display("cpu_data_i %02x %t", cpu_data_i, $time);
|
| 462 |
16 |
ale500 |
state <= `SEQ_FETCH;
|
| 463 |
2 |
ale500 |
end
|
| 464 |
|
|
`SEQ_FETCH: /* execution starts here */
|
| 465 |
|
|
begin
|
| 466 |
16 |
ale500 |
case (k_mem_state)
|
| 467 |
|
|
3'h0: // start, output address
|
| 468 |
|
|
begin
|
| 469 |
|
|
k_p2_valid <= 0; // set when an k_opcode is page 2
|
| 470 |
|
|
k_p3_valid <= 0; // set when an k_opcode is page 3
|
| 471 |
|
|
k_pp_active_reg <= `RN_INV; // ensures that only push/pull control the left/dest muxes
|
| 472 |
|
|
if (k_nmi_req)
|
| 473 |
|
|
state <= `SEQ_NMI;
|
| 474 |
|
|
else
|
| 475 |
|
|
if (k_firq_req & `FLAGF)
|
| 476 |
|
|
state <= `SEQ_FIRQ;
|
| 477 |
|
|
else
|
| 478 |
|
|
if (k_irq_req & `FLAGI)
|
| 479 |
|
|
state <= `SEQ_IRQ;
|
| 480 |
|
|
else
|
| 481 |
|
|
begin
|
| 482 |
|
|
k_mem_state <= k_mem_state + 3'h1;
|
| 483 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 484 |
|
|
k_inc_pc <= 1;
|
| 485 |
|
|
end
|
| 486 |
|
|
end
|
| 487 |
|
|
3'h1:
|
| 488 |
|
|
begin
|
| 489 |
|
|
k_cpu_oe <= 1;
|
| 490 |
|
|
k_mem_state <= k_mem_state + 3'h1;
|
| 491 |
|
|
end
|
| 492 |
|
|
3'h2:
|
| 493 |
|
|
if (cpu_dtack_i)
|
| 494 |
|
|
begin
|
| 495 |
|
|
k_opcode <= cpu_data_i;
|
| 496 |
|
|
k_cpu_oe <= 0;
|
| 497 |
|
|
case (cpu_data_i[7:0]) /* page 2 & 3 opcodes are recognized here */
|
| 498 |
|
|
8'h10:
|
| 499 |
|
|
begin
|
| 500 |
|
|
k_p2_valid <= 1;
|
| 501 |
|
|
k_mem_state <= k_mem_state + 3'h1;
|
| 502 |
|
|
end
|
| 503 |
|
|
8'h11:
|
| 504 |
|
|
begin
|
| 505 |
|
|
k_p3_valid <= 1;
|
| 506 |
|
|
k_mem_state <= k_mem_state + 3'h1;
|
| 507 |
|
|
end
|
| 508 |
|
|
8'h1e, 8'h1f:
|
| 509 |
|
|
k_mem_state <= k_mem_state + 3'h1; // tfr, exg, treated separately
|
| 510 |
|
|
default:
|
| 511 |
|
|
begin
|
| 512 |
|
|
state <= `SEQ_DECODE;
|
| 513 |
|
|
k_mem_state <= 3'h0;
|
| 514 |
|
|
end
|
| 515 |
|
|
endcase
|
| 516 |
|
|
end
|
| 517 |
|
|
3'h3:
|
| 518 |
|
|
begin
|
| 519 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 520 |
|
|
k_inc_pc <= 1;
|
| 521 |
|
|
k_mem_state <= k_mem_state + 3'h1;
|
| 522 |
|
|
end
|
| 523 |
|
|
3'h4:
|
| 524 |
|
|
begin
|
| 525 |
|
|
k_cpu_oe <= 1;
|
| 526 |
|
|
k_mem_state <= k_mem_state + 3'h1;
|
| 527 |
|
|
end
|
| 528 |
|
|
3'h5:
|
| 529 |
|
|
if (cpu_dtack_i)
|
| 530 |
|
|
begin
|
| 531 |
|
|
k_mem_state <= 3'h0;
|
| 532 |
|
|
k_postbyte <= cpu_data_i;
|
| 533 |
|
|
k_cpu_oe <= 0;
|
| 534 |
|
|
state <= `SEQ_DECODE;
|
| 535 |
|
|
end
|
| 536 |
|
|
endcase
|
| 537 |
|
|
end
|
| 538 |
2 |
ale500 |
`SEQ_DECODE:
|
| 539 |
|
|
begin
|
| 540 |
10 |
ale500 |
/* here we have the first byte of the opcode and should be decided to which state we jump
|
| 541 |
2 |
ale500 |
* inherent means that no extra info is needed
|
| 542 |
|
|
* ALU opcodes need routing of registers to/from the ALU to the registers
|
| 543 |
|
|
*/
|
| 544 |
|
|
case (dec_o_p1_mode)
|
| 545 |
10 |
ale500 |
`NONE: // unknown opcode or push/pull... refetch ?
|
| 546 |
2 |
ale500 |
begin
|
| 547 |
14 |
ale500 |
if (op_SYNC) state <= `SEQ_SYNC;
|
| 548 |
|
|
else if (op_PUSH) // PUSH S&U
|
| 549 |
2 |
ale500 |
begin
|
| 550 |
|
|
state <= `SEQ_PC_READ_L;
|
| 551 |
|
|
next_state <= `SEQ_PREPUSH;
|
| 552 |
|
|
next_push_state <= `SEQ_FETCH;
|
| 553 |
|
|
end
|
| 554 |
14 |
ale500 |
else if (op_PULL) // PULL S&U
|
| 555 |
2 |
ale500 |
begin
|
| 556 |
|
|
next_state <= `SEQ_PREPULL;
|
| 557 |
|
|
state <= `SEQ_PC_READ_L;
|
| 558 |
|
|
end
|
| 559 |
16 |
ale500 |
else if (op_EXG) begin k_write_exg <= 1; state <= `SEQ_TFREXG; end
|
| 560 |
|
|
else if (op_TFR) begin k_write_tfr <= 1; state <= `SEQ_TFREXG; end
|
| 561 |
14 |
ale500 |
else /* we ignore unknown opcodes */
|
| 562 |
|
|
state <= `SEQ_FETCH;
|
| 563 |
2 |
ale500 |
end
|
| 564 |
|
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
| 565 |
|
|
begin
|
| 566 |
|
|
if (dec_o_alu_size)
|
| 567 |
|
|
state <= `SEQ_PC_READ_H;
|
| 568 |
|
|
else
|
| 569 |
|
|
state <= `SEQ_PC_READ_L;
|
| 570 |
|
|
next_state <= `SEQ_GRAL_ALU;
|
| 571 |
|
|
end
|
| 572 |
|
|
`INHERENT:
|
| 573 |
|
|
begin
|
| 574 |
14 |
ale500 |
if (op_RTI) // RTI
|
| 575 |
|
|
begin
|
| 576 |
|
|
state <= `SEQ_PREPULL;
|
| 577 |
|
|
k_pp_regs <= 8'hff; // all regs
|
| 578 |
|
|
end
|
| 579 |
|
|
else if (op_RTS)
|
| 580 |
|
|
begin
|
| 581 |
|
|
state <= `SEQ_PREPULL;
|
| 582 |
|
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
| 583 |
|
|
end
|
| 584 |
|
|
else if (op_MUL)
|
| 585 |
|
|
begin k_mul_cnt <= 1'h1; state <= `SEQ_GRAL_ALU; end // counter for mul
|
| 586 |
|
|
else if (op_SWI)
|
| 587 |
16 |
ale500 |
begin
|
| 588 |
|
|
if (k_p2_valid) state <= `SEQ_SWI2;
|
| 589 |
|
|
else if (k_p3_valid) state <= `SEQ_SWI3;
|
| 590 |
|
|
else
|
| 591 |
|
|
state <= `SEQ_SWI;
|
| 592 |
|
|
end
|
| 593 |
14 |
ale500 |
else
|
| 594 |
|
|
state <= `SEQ_GRAL_ALU;
|
| 595 |
2 |
ale500 |
end
|
| 596 |
|
|
`DIRECT:
|
| 597 |
|
|
begin
|
| 598 |
10 |
ale500 |
state <= `SEQ_PC_READ_L; // loads address
|
| 599 |
14 |
ale500 |
if (op_JSR) next_state <= `SEQ_JSR_PUSH;
|
| 600 |
|
|
else if (op_JMP) next_state <= `SEQ_JMP_LOAD_PC;
|
| 601 |
|
|
else
|
| 602 |
16 |
ale500 |
begin
|
| 603 |
|
|
if (dec_o_operand_read)
|
| 604 |
14 |
ale500 |
begin
|
| 605 |
|
|
next_state <= `SEQ_MEM_READ_H;
|
| 606 |
|
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
| 607 |
|
|
end
|
| 608 |
|
|
else
|
| 609 |
|
|
next_state <= `SEQ_GRAL_ALU; // no read
|
| 610 |
|
|
k_eahi <= regs_o_dp;
|
| 611 |
|
|
end
|
| 612 |
2 |
ale500 |
end
|
| 613 |
|
|
`INDEXED:
|
| 614 |
|
|
state <= `SEQ_IND_READ_EA;
|
| 615 |
|
|
`EXTENDED:
|
| 616 |
10 |
ale500 |
begin
|
| 617 |
2 |
ale500 |
state <= `SEQ_PC_READ_H; // loads address
|
| 618 |
14 |
ale500 |
if (op_JSR) next_state <= `SEQ_JSR_PUSH;
|
| 619 |
|
|
else if (op_JMP) next_state <= `SEQ_JMP_LOAD_PC;
|
| 620 |
|
|
else
|
| 621 |
16 |
ale500 |
begin
|
| 622 |
|
|
if (dec_o_operand_read)
|
| 623 |
14 |
ale500 |
begin
|
| 624 |
|
|
next_state <= `SEQ_MEM_READ_H;
|
| 625 |
|
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
| 626 |
|
|
end
|
| 627 |
|
|
else
|
| 628 |
|
|
next_state <= `SEQ_GRAL_ALU; // no read
|
| 629 |
|
|
end
|
| 630 |
2 |
ale500 |
end
|
| 631 |
|
|
`REL8:
|
| 632 |
|
|
begin
|
| 633 |
|
|
state <= `SEQ_PC_READ_L; // loads address
|
| 634 |
14 |
ale500 |
if (op_JSR) // bsr
|
| 635 |
2 |
ale500 |
next_state <= `SEQ_JSR_PUSH;
|
| 636 |
|
|
else
|
| 637 |
|
|
next_state <= `SEQ_JMP_LOAD_PC; // offset loaded in this cycle, jump if needed
|
| 638 |
|
|
end
|
| 639 |
|
|
`REL16:
|
| 640 |
|
|
begin
|
| 641 |
|
|
state <= `SEQ_PC_READ_H; // loads address
|
| 642 |
14 |
ale500 |
if (op_JSR) // lbsr
|
| 643 |
2 |
ale500 |
next_state <= `SEQ_JSR_PUSH;
|
| 644 |
|
|
else
|
| 645 |
|
|
next_state <= `SEQ_JMP_LOAD_PC;
|
| 646 |
|
|
end
|
| 647 |
|
|
endcase
|
| 648 |
|
|
end
|
| 649 |
4 |
ale500 |
`SEQ_GRAL_ALU:
|
| 650 |
6 |
ale500 |
begin
|
| 651 |
|
|
if (!k_mul_cnt)
|
| 652 |
|
|
begin
|
| 653 |
|
|
state <= `SEQ_GRAL_WBACK;
|
| 654 |
|
|
k_write_dest <= 1; /* write destination on wback */
|
| 655 |
|
|
end
|
| 656 |
7 |
ale500 |
k_mul_cnt <= 1'h0;
|
| 657 |
4 |
ale500 |
end
|
| 658 |
2 |
ale500 |
`SEQ_GRAL_WBACK:
|
| 659 |
|
|
begin
|
| 660 |
4 |
ale500 |
next_mem_state <= `SEQ_FETCH;
|
| 661 |
14 |
ale500 |
if (op_CWAI) state <= `SEQ_CWAI_STACK; // CWAI
|
| 662 |
16 |
ale500 |
else if (dec_o_dest_memtype == `MT_BYTE) state <= `SEQ_MEM_WRITE_L;
|
| 663 |
|
|
else if (dec_o_dest_memtype == `MT_WORD) state <= `SEQ_MEM_WRITE_H;
|
| 664 |
|
|
else
|
| 665 |
|
|
begin
|
| 666 |
|
|
state <= `SEQ_FETCH;
|
| 667 |
|
|
k_write_post_incdec <= dec_o_ea_wpost & (dec_o_p1_mode == `INDEXED);
|
| 668 |
|
|
end
|
| 669 |
2 |
ale500 |
end
|
| 670 |
6 |
ale500 |
`SEQ_CWAI_STACK:
|
| 671 |
|
|
begin
|
| 672 |
|
|
k_pp_regs <= 8'hff;
|
| 673 |
|
|
k_set_e <= 1;
|
| 674 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 675 |
|
|
next_push_state <= `SEQ_CWAI_WAIT; // wait for interrupts
|
| 676 |
|
|
end
|
| 677 |
|
|
`SEQ_CWAI_WAIT: /* waits for an interrupt and process it */
|
| 678 |
|
|
begin
|
| 679 |
|
|
k_forced_mem_size <= 1;
|
| 680 |
|
|
next_mem_state <= `SEQ_FETCH; // then continue fetching instructions
|
| 681 |
|
|
k_eahi <= 8'hff;
|
| 682 |
|
|
k_ealo[7:4] <= 4'hf;
|
| 683 |
|
|
if (k_nmi_req)
|
| 684 |
|
|
begin
|
| 685 |
7 |
ale500 |
k_reg_nmi <= 3'h0;
|
| 686 |
6 |
ale500 |
k_ealo[3:0] <= 4'hc;
|
| 687 |
|
|
state <= `SEQ_MEM_READ_H; // load new PC
|
| 688 |
|
|
end
|
| 689 |
|
|
else
|
| 690 |
7 |
ale500 |
if (k_firq_req & `FLAGF)
|
| 691 |
6 |
ale500 |
begin
|
| 692 |
7 |
ale500 |
k_reg_firq <= 3'h0;
|
| 693 |
6 |
ale500 |
k_ealo[3:0] <= 4'h6;
|
| 694 |
|
|
state <= `SEQ_MEM_READ_H; // load new PC
|
| 695 |
|
|
end
|
| 696 |
|
|
else
|
| 697 |
7 |
ale500 |
if (k_irq_req & `FLAGI)
|
| 698 |
6 |
ale500 |
begin
|
| 699 |
7 |
ale500 |
k_reg_irq <= 3'h0;
|
| 700 |
10 |
ale500 |
k_ealo[3:0] <= 4'h8;
|
| 701 |
6 |
ale500 |
state <= `SEQ_MEM_READ_H; // load new PC
|
| 702 |
|
|
end
|
| 703 |
7 |
ale500 |
end
|
| 704 |
|
|
`SEQ_SYNC: /* sync works like this:
|
| 705 |
|
|
* waits for an interrupt request
|
| 706 |
|
|
* we recognize an interrupt if the level was kept for 2 cycles
|
| 707 |
|
|
* then we don't call the service routine
|
| 708 |
|
|
* if it was 3 or more cycles, then we call the service routine
|
| 709 |
|
|
*/
|
| 710 |
|
|
begin
|
| 711 |
|
|
if (k_nmi_req)
|
| 712 |
|
|
begin
|
| 713 |
|
|
if (k_reg_nmi == 3'b111) // at least 3 cycles long
|
| 714 |
|
|
state <= `SEQ_NMI;
|
| 715 |
|
|
else
|
| 716 |
|
|
begin
|
| 717 |
|
|
state <= `SEQ_FETCH;
|
| 718 |
|
|
k_reg_nmi <= 3'h0;
|
| 719 |
|
|
end
|
| 720 |
|
|
end
|
| 721 |
|
|
else
|
| 722 |
|
|
if (k_firq_req & `FLAGF)
|
| 723 |
|
|
begin
|
| 724 |
|
|
if (k_reg_firq == 3'b111) // at least 3 cycles long
|
| 725 |
|
|
state <= `SEQ_FIRQ;
|
| 726 |
|
|
else
|
| 727 |
|
|
begin
|
| 728 |
|
|
state <= `SEQ_FETCH;
|
| 729 |
|
|
k_reg_firq <= 3'h0;
|
| 730 |
|
|
end
|
| 731 |
|
|
end
|
| 732 |
|
|
else
|
| 733 |
|
|
if (k_irq_req & `FLAGI)
|
| 734 |
|
|
begin
|
| 735 |
|
|
if (k_reg_irq == 3'b111) // at least 3 cycles long
|
| 736 |
|
|
state <= `SEQ_IRQ;
|
| 737 |
|
|
else
|
| 738 |
|
|
begin
|
| 739 |
|
|
state <= `SEQ_FETCH;
|
| 740 |
|
|
k_reg_irq <= 3'h0;
|
| 741 |
|
|
end
|
| 742 |
|
|
end
|
| 743 |
|
|
else
|
| 744 |
|
|
begin
|
| 745 |
|
|
state <= `SEQ_FETCH_1;
|
| 746 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 747 |
|
|
end
|
| 748 |
6 |
ale500 |
end
|
| 749 |
5 |
ale500 |
`SEQ_TFREXG:
|
| 750 |
|
|
state <= `SEQ_FETCH;
|
| 751 |
2 |
ale500 |
`SEQ_IND_READ_EA: // reads EA byte
|
| 752 |
|
|
begin
|
| 753 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 754 |
|
|
state <= `SEQ_IND_READ_EA_1;
|
| 755 |
|
|
k_inc_pc <= 1;
|
| 756 |
|
|
end
|
| 757 |
|
|
`SEQ_IND_READ_EA_1:
|
| 758 |
|
|
begin
|
| 759 |
|
|
k_cpu_oe <= 1; // read
|
| 760 |
|
|
state <= `SEQ_IND_READ_EA_2;
|
| 761 |
|
|
end
|
| 762 |
|
|
`SEQ_IND_READ_EA_2:
|
| 763 |
|
|
begin
|
| 764 |
|
|
k_ind_ea <= cpu_data_i;
|
| 765 |
|
|
state <= `SEQ_IND_DECODE;
|
| 766 |
|
|
end
|
| 767 |
|
|
`SEQ_IND_DECODE: // here we have to see what we need for indexed...
|
| 768 |
|
|
begin
|
| 769 |
12 |
ale500 |
k_indirect_loaded <= 1'b0;
|
| 770 |
2 |
ale500 |
if (dec_o_ea_ofs8)
|
| 771 |
|
|
begin // load 1 byte offset
|
| 772 |
|
|
state <= `SEQ_PC_READ_L;
|
| 773 |
|
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
| 774 |
|
|
end
|
| 775 |
|
|
else
|
| 776 |
|
|
if (dec_o_ea_ofs16)
|
| 777 |
|
|
begin // load 2 bytes offset
|
| 778 |
|
|
state <= `SEQ_PC_READ_H;
|
| 779 |
|
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
| 780 |
|
|
end
|
| 781 |
|
|
else
|
| 782 |
14 |
ale500 |
if (op_JSR) // jsr
|
| 783 |
|
|
next_state <= `SEQ_JSR_PUSH;
|
| 784 |
10 |
ale500 |
else
|
| 785 |
2 |
ale500 |
begin // no extra load...
|
| 786 |
16 |
ale500 |
if (dec_o_operand_read)
|
| 787 |
2 |
ale500 |
begin
|
| 788 |
|
|
next_mem_state <= `SEQ_GRAL_ALU;
|
| 789 |
4 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 790 |
12 |
ale500 |
if (dec_o_ea_indirect)
|
| 791 |
|
|
k_forced_mem_size <= 1; // to load indirect address
|
| 792 |
2 |
ale500 |
end
|
| 793 |
|
|
else
|
| 794 |
|
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
| 795 |
|
|
end
|
| 796 |
|
|
end
|
| 797 |
|
|
`SEQ_IND_DECODE_OFS: // loads argument if needed
|
| 798 |
10 |
ale500 |
begin
|
| 799 |
14 |
ale500 |
if (op_JSR) // jsr
|
| 800 |
10 |
ale500 |
next_state <= `SEQ_JSR_PUSH;
|
| 801 |
2 |
ale500 |
else
|
| 802 |
10 |
ale500 |
begin
|
| 803 |
16 |
ale500 |
if (dec_o_operand_read)
|
| 804 |
10 |
ale500 |
begin
|
| 805 |
|
|
next_mem_state <= `SEQ_GRAL_ALU;
|
| 806 |
|
|
state <= `SEQ_MEM_READ_H;
|
| 807 |
12 |
ale500 |
if (dec_o_ea_indirect)
|
| 808 |
|
|
k_forced_mem_size <= 1; // to load indirect address
|
| 809 |
10 |
ale500 |
end
|
| 810 |
|
|
else
|
| 811 |
|
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
| 812 |
|
|
end
|
| 813 |
2 |
ale500 |
end
|
| 814 |
|
|
`SEQ_JMP_LOAD_PC:
|
| 815 |
|
|
begin
|
| 816 |
|
|
state <= `SEQ_FETCH;
|
| 817 |
|
|
end
|
| 818 |
|
|
`SEQ_JSR_PUSH:
|
| 819 |
|
|
begin
|
| 820 |
9 |
ale500 |
k_pp_active_reg <= `RN_PC; // push PC
|
| 821 |
2 |
ale500 |
state <= `SEQ_PUSH_WRITE_L;
|
| 822 |
|
|
next_state <= `SEQ_JMP_LOAD_PC;
|
| 823 |
|
|
end
|
| 824 |
|
|
`SEQ_PREPUSH:
|
| 825 |
|
|
begin
|
| 826 |
|
|
next_state <= `SEQ_PREPUSH;
|
| 827 |
4 |
ale500 |
if (k_pp_regs > 0)
|
| 828 |
|
|
begin
|
| 829 |
|
|
state <= `SEQ_PUSH_WRITE_L;
|
| 830 |
|
|
end
|
| 831 |
2 |
ale500 |
else
|
| 832 |
|
|
state <= next_push_state;
|
| 833 |
6 |
ale500 |
if (k_pp_regs[7]) begin k_pp_regs[7] <= 0; k_pp_active_reg <= `RN_PC; end
|
| 834 |
2 |
ale500 |
else
|
| 835 |
6 |
ale500 |
if (k_pp_regs[6]) begin k_pp_regs[6] <= 0; k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; end
|
| 836 |
2 |
ale500 |
else
|
| 837 |
6 |
ale500 |
if (k_pp_regs[5]) begin k_pp_regs[5] <= 0; k_pp_active_reg <= `RN_IY; end
|
| 838 |
2 |
ale500 |
else
|
| 839 |
6 |
ale500 |
if (k_pp_regs[4]) begin k_pp_regs[4] <= 0; k_pp_active_reg <= `RN_IX; end
|
| 840 |
2 |
ale500 |
else
|
| 841 |
6 |
ale500 |
if (k_pp_regs[3]) begin k_pp_regs[3] <= 0; k_pp_active_reg <= `RN_DP; end
|
| 842 |
2 |
ale500 |
else
|
| 843 |
6 |
ale500 |
if (k_pp_regs[2]) begin k_pp_regs[2] <= 0; k_pp_active_reg <= `RN_ACCB; end
|
| 844 |
2 |
ale500 |
else
|
| 845 |
6 |
ale500 |
if (k_pp_regs[1]) begin k_pp_regs[1] <= 0; k_pp_active_reg <= `RN_ACCA; end
|
| 846 |
2 |
ale500 |
else
|
| 847 |
6 |
ale500 |
if (k_pp_regs[0]) begin k_pp_regs[0] <= 0; k_pp_active_reg <= `RN_CC; end
|
| 848 |
2 |
ale500 |
end
|
| 849 |
|
|
`SEQ_PREPULL:
|
| 850 |
4 |
ale500 |
begin
|
| 851 |
|
|
if (k_pp_regs != 8'h0)
|
| 852 |
|
|
begin
|
| 853 |
|
|
next_mem_state <= `SEQ_PREPULL;
|
| 854 |
|
|
end
|
| 855 |
|
|
else
|
| 856 |
|
|
state <= `SEQ_FETCH; // end of sequence
|
| 857 |
6 |
ale500 |
if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 858 |
9 |
ale500 |
else
|
| 859 |
14 |
ale500 |
if (op_RTI && (!`FLAGE)) // not all registers have to be pulled
|
| 860 |
9 |
ale500 |
begin
|
| 861 |
|
|
k_pp_active_reg <= `RN_PC; k_pp_regs <= 0; state <= `SEQ_MEM_READ_H;
|
| 862 |
|
|
end
|
| 863 |
2 |
ale500 |
else
|
| 864 |
6 |
ale500 |
if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 865 |
2 |
ale500 |
else
|
| 866 |
6 |
ale500 |
if (k_pp_regs[2]) begin k_pp_active_reg <= `RN_ACCB; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 867 |
2 |
ale500 |
else
|
| 868 |
6 |
ale500 |
if (k_pp_regs[3]) begin k_pp_active_reg <= `RN_DP; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 869 |
2 |
ale500 |
else
|
| 870 |
6 |
ale500 |
if (k_pp_regs[4]) begin k_pp_active_reg <= `RN_IX; k_pp_regs[4] <= 0; state <= `SEQ_MEM_READ_H;end
|
| 871 |
2 |
ale500 |
else
|
| 872 |
6 |
ale500 |
if (k_pp_regs[5]) begin k_pp_active_reg <= `RN_IY; k_pp_regs[5] <= 0; state <= `SEQ_MEM_READ_H;end
|
| 873 |
2 |
ale500 |
else
|
| 874 |
6 |
ale500 |
if (k_pp_regs[6]) begin k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; k_pp_regs[6] <= 0; state <= `SEQ_MEM_READ_H; end
|
| 875 |
2 |
ale500 |
else
|
| 876 |
6 |
ale500 |
if (k_pp_regs[7]) begin k_pp_active_reg <= `RN_PC; k_pp_regs[7] <= 0; state <= `SEQ_MEM_READ_H; end
|
| 877 |
2 |
ale500 |
end
|
| 878 |
|
|
`SEQ_PUSH_WRITE_L: // first low byte push
|
| 879 |
|
|
begin
|
| 880 |
|
|
k_cpu_data_o <= regs_o_left_path_data[7:0];
|
| 881 |
|
|
state <= `SEQ_PUSH_WRITE_L_1;
|
| 882 |
|
|
k_cpu_we <= 1; // write
|
| 883 |
4 |
ale500 |
k_cpu_addr <= regs_o_su - 16'h1;
|
| 884 |
|
|
k_dec_su <= 1;
|
| 885 |
2 |
ale500 |
end
|
| 886 |
|
|
`SEQ_PUSH_WRITE_L_1:
|
| 887 |
|
|
begin
|
| 888 |
6 |
ale500 |
if (k_pp_active_reg < `RN_ACCA)
|
| 889 |
2 |
ale500 |
state <= `SEQ_PUSH_WRITE_H;
|
| 890 |
|
|
else
|
| 891 |
|
|
if (k_pp_regs[3:0] > 0)
|
| 892 |
|
|
state <= `SEQ_PREPUSH;
|
| 893 |
|
|
else
|
| 894 |
4 |
ale500 |
state <= next_push_state;
|
| 895 |
|
|
k_cpu_addr <= k_cpu_addr - 16'h1; // when pushing 16 bits the second decrement comes too late
|
| 896 |
2 |
ale500 |
end
|
| 897 |
|
|
`SEQ_PUSH_WRITE_H: // reads high byte
|
| 898 |
|
|
begin
|
| 899 |
|
|
k_cpu_data_o <= regs_o_left_path_data[15:8];
|
| 900 |
|
|
state <= `SEQ_PUSH_WRITE_H_1;
|
| 901 |
4 |
ale500 |
k_cpu_we <= 1; // write
|
| 902 |
6 |
ale500 |
if (k_pp_active_reg >= `RN_ACCA)
|
| 903 |
|
|
k_cpu_addr <= regs_o_su; // address for 8 bit register
|
| 904 |
2 |
ale500 |
k_dec_su <= 1; // decrement stack pointer
|
| 905 |
|
|
end
|
| 906 |
|
|
`SEQ_PUSH_WRITE_H_1:
|
| 907 |
4 |
ale500 |
begin
|
| 908 |
|
|
if (next_state == `SEQ_JMP_LOAD_PC)
|
| 909 |
|
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
| 910 |
2 |
ale500 |
state <= next_state;
|
| 911 |
|
|
end
|
| 912 |
|
|
`SEQ_PC_READ_H: // reads high byte for [PC], used by IMM, DIR, EXT
|
| 913 |
|
|
begin
|
| 914 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 915 |
|
|
state <= `SEQ_PC_READ_H_1;
|
| 916 |
|
|
k_inc_pc <= 1;
|
| 917 |
|
|
end
|
| 918 |
|
|
`SEQ_PC_READ_H_1:
|
| 919 |
|
|
begin
|
| 920 |
|
|
k_cpu_oe <= 1; // read
|
| 921 |
|
|
state <= `SEQ_PC_READ_H_2;
|
| 922 |
|
|
end
|
| 923 |
|
|
`SEQ_PC_READ_H_2:
|
| 924 |
|
|
begin
|
| 925 |
|
|
case (dec_o_p1_mode)
|
| 926 |
|
|
`REL16, `IMMEDIATE: k_memhi <= cpu_data_i;
|
| 927 |
|
|
`EXTENDED: k_eahi <= cpu_data_i;
|
| 928 |
|
|
`INDEXED: k_ofshi <= cpu_data_i;
|
| 929 |
|
|
endcase
|
| 930 |
|
|
state <= `SEQ_PC_READ_L;
|
| 931 |
|
|
end
|
| 932 |
|
|
`SEQ_PC_READ_L: // reads low byte [PC]
|
| 933 |
|
|
begin
|
| 934 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 935 |
|
|
state <= `SEQ_PC_READ_L_1;
|
| 936 |
|
|
k_inc_pc <= 1;
|
| 937 |
|
|
end
|
| 938 |
|
|
`SEQ_PC_READ_L_1:
|
| 939 |
|
|
begin
|
| 940 |
|
|
k_cpu_oe <= 1; // read
|
| 941 |
|
|
state <= `SEQ_PC_READ_L_2;
|
| 942 |
|
|
end
|
| 943 |
|
|
`SEQ_PC_READ_L_2:
|
| 944 |
|
|
begin
|
| 945 |
|
|
case (dec_o_p1_mode)
|
| 946 |
|
|
`NONE: k_pp_regs <= cpu_data_i; // push & pull
|
| 947 |
|
|
`REL8, `REL16, `IMMEDIATE: k_memlo <= cpu_data_i;
|
| 948 |
|
|
`DIRECT, `EXTENDED: k_ealo <= cpu_data_i;
|
| 949 |
|
|
`INDEXED: k_ofslo <= cpu_data_i;
|
| 950 |
4 |
ale500 |
endcase
|
| 951 |
|
|
if ((next_state == `SEQ_JMP_LOAD_PC) & (dec_o_cond_taken))
|
| 952 |
|
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
| 953 |
2 |
ale500 |
state <= next_state;
|
| 954 |
|
|
end
|
| 955 |
|
|
`SEQ_MEM_READ_H: // reads high byte
|
| 956 |
|
|
begin
|
| 957 |
|
|
case (dec_o_p1_mode)
|
| 958 |
12 |
ale500 |
`INDEXED:
|
| 959 |
|
|
if (k_indirect_loaded)
|
| 960 |
|
|
k_cpu_addr <= { k_memhi, k_memlo };
|
| 961 |
|
|
else
|
| 962 |
|
|
k_cpu_addr <= regs_o_eamem_addr;
|
| 963 |
14 |
ale500 |
default:
|
| 964 |
|
|
if (op_PULL | op_RTI | op_RTS)
|
| 965 |
|
|
begin
|
| 966 |
|
|
k_cpu_addr <= regs_o_su;
|
| 967 |
|
|
k_inc_su <= 1;
|
| 968 |
|
|
end
|
| 969 |
|
|
else
|
| 970 |
|
|
k_cpu_addr <= { k_eahi, k_ealo };
|
| 971 |
4 |
ale500 |
endcase
|
| 972 |
6 |
ale500 |
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
| 973 |
4 |
ale500 |
state <= `SEQ_MEM_READ_H_1;
|
| 974 |
|
|
else
|
| 975 |
|
|
state <= `SEQ_MEM_READ_L_1;
|
| 976 |
|
|
k_forced_mem_size <= 0; // used for vector fetch
|
| 977 |
2 |
ale500 |
end
|
| 978 |
|
|
`SEQ_MEM_READ_H_1:
|
| 979 |
|
|
begin
|
| 980 |
|
|
k_cpu_oe <= 1; // read
|
| 981 |
|
|
state <= `SEQ_MEM_READ_H_2;
|
| 982 |
|
|
end
|
| 983 |
|
|
`SEQ_MEM_READ_H_2:
|
| 984 |
|
|
begin
|
| 985 |
16 |
ale500 |
k_memhi <= cpu_data_i;
|
| 986 |
2 |
ale500 |
state <= `SEQ_MEM_READ_L_1;
|
| 987 |
4 |
ale500 |
k_cpu_addr <= k_cpu_addr + 16'h1;
|
| 988 |
14 |
ale500 |
if (op_PULL | op_RTI | op_RTS)
|
| 989 |
|
|
k_inc_su <= 1;
|
| 990 |
2 |
ale500 |
end
|
| 991 |
4 |
ale500 |
`SEQ_MEM_READ_L: // reads low byte
|
| 992 |
2 |
ale500 |
begin
|
| 993 |
4 |
ale500 |
// falls through from READ_MEM_H with the right address
|
| 994 |
14 |
ale500 |
if (op_PULL | op_RTI | op_RTS)
|
| 995 |
|
|
begin
|
| 996 |
|
|
k_cpu_addr <= regs_o_su;
|
| 997 |
|
|
k_inc_su <= 1;
|
| 998 |
|
|
end
|
| 999 |
2 |
ale500 |
state <= `SEQ_MEM_READ_L_1;
|
| 1000 |
|
|
end
|
| 1001 |
|
|
`SEQ_MEM_READ_L_1:
|
| 1002 |
|
|
begin
|
| 1003 |
|
|
k_cpu_oe <= 1; // read
|
| 1004 |
|
|
state <= `SEQ_MEM_READ_L_2;
|
| 1005 |
|
|
end
|
| 1006 |
|
|
`SEQ_MEM_READ_L_2:
|
| 1007 |
|
|
begin
|
| 1008 |
16 |
ale500 |
k_memlo <= cpu_data_i;
|
| 1009 |
|
|
if (op_PULL | op_RTI | op_RTS) k_write_dest <= 1; // FIXME: which other opcode is inherent and needs write-back ?
|
| 1010 |
|
|
if (next_mem_state == `SEQ_LOADPC) // used by cold-reset
|
| 1011 |
10 |
ale500 |
k_write_pc <= 1;
|
| 1012 |
12 |
ale500 |
case (dec_o_p1_mode)
|
| 1013 |
|
|
`INDEXED: // address loaded, load argument
|
| 1014 |
|
|
if (k_indirect_loaded | (!dec_o_ea_indirect))
|
| 1015 |
|
|
state <= next_mem_state;
|
| 1016 |
|
|
else
|
| 1017 |
|
|
begin
|
| 1018 |
|
|
state <= `SEQ_MEM_READ_H;
|
| 1019 |
|
|
k_indirect_loaded <= 1'b1;
|
| 1020 |
|
|
end
|
| 1021 |
|
|
default:
|
| 1022 |
|
|
state <= next_mem_state;
|
| 1023 |
|
|
endcase
|
| 1024 |
2 |
ale500 |
end
|
| 1025 |
|
|
`SEQ_MEM_WRITE_H: // writes high byte
|
| 1026 |
|
|
begin
|
| 1027 |
|
|
case (dec_o_p1_mode)
|
| 1028 |
|
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
| 1029 |
|
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
| 1030 |
|
|
endcase
|
| 1031 |
4 |
ale500 |
k_cpu_data_o <= datamux_o_dest[15:8];
|
| 1032 |
2 |
ale500 |
state <= `SEQ_MEM_WRITE_H_1;
|
| 1033 |
|
|
k_cpu_we <= 1; // read
|
| 1034 |
|
|
end
|
| 1035 |
|
|
`SEQ_MEM_WRITE_H_1:
|
| 1036 |
|
|
begin
|
| 1037 |
|
|
state <= `SEQ_MEM_WRITE_L;
|
| 1038 |
|
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
| 1039 |
|
|
end
|
| 1040 |
|
|
`SEQ_MEM_WRITE_L: // reads high byte
|
| 1041 |
|
|
begin
|
| 1042 |
6 |
ale500 |
if (!dec_o_alu_size) // only if it is an 8 bit write
|
| 1043 |
2 |
ale500 |
case (dec_o_p1_mode)
|
| 1044 |
|
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
| 1045 |
|
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
| 1046 |
|
|
endcase
|
| 1047 |
|
|
k_cpu_data_o <= datamux_o_dest[7:0];
|
| 1048 |
|
|
state <= `SEQ_MEM_WRITE_L_1;
|
| 1049 |
|
|
k_cpu_we <= 1; // write
|
| 1050 |
|
|
end
|
| 1051 |
|
|
`SEQ_MEM_WRITE_L_1:
|
| 1052 |
|
|
begin
|
| 1053 |
|
|
k_write_post_incdec <= dec_o_ea_wpost;
|
| 1054 |
|
|
state <= next_mem_state;
|
| 1055 |
|
|
end
|
| 1056 |
|
|
|
| 1057 |
|
|
endcase
|
| 1058 |
|
|
end
|
| 1059 |
|
|
end
|
| 1060 |
|
|
|
| 1061 |
|
|
initial
|
| 1062 |
|
|
begin
|
| 1063 |
16 |
ale500 |
k_mem_state = 0;
|
| 1064 |
2 |
ale500 |
k_cpu_oe = 0;
|
| 1065 |
|
|
k_cpu_we = 0;
|
| 1066 |
5 |
ale500 |
k_new_pc = 16'hffff;
|
| 1067 |
|
|
k_write_tfr = 0;
|
| 1068 |
6 |
ale500 |
k_write_exg = 0;
|
| 1069 |
|
|
k_mul_cnt = 0;
|
| 1070 |
10 |
ale500 |
k_write_dest = 0;
|
| 1071 |
12 |
ale500 |
k_indirect_loaded = 0;
|
| 1072 |
2 |
ale500 |
end
|
| 1073 |
10 |
ale500 |
endmodule
|
| 1074 |
16 |
ale500 |
|
