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/*
 * (c) 2013 Alejandro Paz
 *
 *
 * An alu core
 *
 * ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL
 *
 *
 *
 */
`include "defs.v"
 
 
module alu(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        input wire sz_in, /* size, low 8 bit, high 16 bit */
        output reg [15:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire [7:0] ccr8_out, q8_out;
wire [15:0] q16_out;
wire [3:0] ccr16_out;
wire [15:0] q16_mul;
reg [15:0] ra_in, rb_in;
reg [4:0] rop_in;
 
 
mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);
alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);
alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_mul, q16_out, ccr16_out);
 
 
always @(posedge clk_in)
        begin
                ra_in <= a_in;
                rb_in <= b_in;
                rop_in <= opcode_in;
        end
 
always @(*)
        begin
                if (sz_in)
                        begin
                                q_out = q16_out;
                                CCRo = { CCR[7:4], ccr16_out };
                        end
                else
                        begin
                                q_out = { 8'h0, q8_out };
                                CCRo = ccr8_out;
                        end
        end
 
 
endmodule
/**
 * Simple 3 functions logic
 *
 */
module logic8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out /* ALU result */
        );
 
always @(*)
        begin
                case (opcode_in)
                        2'b00: q_out = b_in;
                        2'b01: q_out = a_in & b_in;
                        2'b10: q_out = a_in | b_in;
                        2'b11: q_out = a_in ^ b_in;
                endcase
        end
 
endmodule
 
/**
 * Simple ADD/SUB module
 *
 */
module arith8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire carry_in, /* condition code register */
        input wire half_c_in,
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output reg carry_out,
        output reg overflow_out,
        output reg half_c_out
        );
 
wire carry;
assign carry = opcode_in[1] ? carry_in:1'b0;
 
always @(*)
        begin
                case (opcode_in[0])
                        1'b0: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry }; // ADD/ADC
                        1'b1: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry }; // SUB/SBC
                endcase
        end
 
always @(*)
        begin
                case (opcode_in[0])
                        1'b0: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) | ((~a_in[7]) & (~b_in[7]) & q_out[7]);
                        1'b1: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) | ((~a_in[7]) & b_in[7] & q_out[7]);
                endcase
        end
 
always @(*)
        begin
                case (opcode_in[0])
                        1'b0: half_c_out = (a_in[4] ^ b_in[4] ^ q_out[4]);
                        1'b1: half_c_out = half_c_in;
                endcase
        end
 
endmodule
 
/**
 * Simple ADD/SUB module
 *
 */
module arith16(
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire carry_in, /* condition code register */
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [15:0] q_out, /* ALU result */
        output reg carry_out,
        output reg overflow_out
        );
always @(*)
        begin
                case (opcode_in)
                        2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD
                        2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB
                        2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC
                        2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC
                endcase
        end
 
always @(*)
        begin
                case (opcode_in)
                        2'b00, 2'b10: overflow_out = (a_in[15] & b_in[15] & (~q_out[15])) | ((~a_in[15]) & (~b_in[15]) & q_out[7]);
                        2'b01, 2'b11: overflow_out = (a_in[15] & (~b_in[15]) & (~q_out[15])) | ((~a_in[15]) & b_in[15] & q_out[7]);
                endcase
        end
 
endmodule
 
module shift8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire carry_in, /* condition code register */
        input wire overflow_in, /* condition code register */
        input wire [2:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output wire carry_out,
        output reg overflow_out
        );
 
always @(*)
        begin
                q_out = { a_in[7], a_in[7:1] }; // ASR
                case (opcode_in)
                        3'b000: q_out = { 1'b0, a_in[7:1] }; // LSR
                        3'b001: q_out = { a_in[6:0], 1'b0 }; // LSL
                        3'b010: q_out = { carry_in, a_in[7:1] }; // ROR
                        3'b011: q_out = { a_in[6:0], carry_in }; // ROL
                        3'b100: q_out = { a_in[7], a_in[7:1] }; // ASR
                endcase
        end
 
always @(*)
        begin
                overflow_out = overflow_in;
                case (opcode_in)
                        3'b000: overflow_out = overflow_in; // LSR
                        3'b001: overflow_out = a_in[7] ^ a_in[6]; // LSL
                        3'b010: overflow_out = overflow_in; // ROR
                        3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL
                        3'b100: overflow_out = overflow_in; // ASR
                endcase
        end
 
assign carry_out = opcode_in[0] ? a_in[7]:a_in[0];
 
endmodule
 
 
module alu8(
        input wire clk_in,
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in, h_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
assign h_in = CCR[5]; /* halb-carry flag */
 
wire [7:0] com8_r, neg8_r, daa_p0_r;
wire [3:0] daa8h_r;
 
wire [7:0] com8_w, neg8_w;
 
wire ccom8_r, cneg8_r, cdaa8_r;
 
wire vcom8_r, vneg8_r;
 
assign com8_w = ~a_in[7:0];
assign neg8_w = 8'h0 - a_in[7:0];
                // COM
assign com8_r = com8_w;
assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;
assign vcom8_r = 1'b0;
                // NEG
assign neg8_r = neg8_w;
assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];
assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);
 
reg c8, h8, n8, v8, z8;
reg [7:0] q8;
 
wire [7:0] logic_q, arith_q, shift_q;
wire arith_c, arith_v, arith_h;
wire shift_c, shift_v;
 
logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);
arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);
shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);
                // DAA
assign daa_p0_r = ((a_in[3:0] > 4'h9) | h_in ) ? a_in[7:0] + 8'h6:a_in[7:0];
assign { cdaa8_r, daa8h_r } = ((daa_p0_r[7:4] > 9) || (c_in == 1'b1)) ? { 1'b0, daa_p0_r[7:4] } + 5'h6:{ 1'b0, daa_p0_r[7:4] };
 
always @(*)
        begin
                q8 = 8'h0;
                c8 = c_in;
                h8 = h_in;
                v8 = v_in;
                case (opcode_in)
                        `SEXT:
                                begin
                                        q8 = a_in[7] ? 8'hff:8'h00;
                                end
                        `ADD, `ADC, `SUB, `SBC:
                                begin
                                        q8 = arith_q;
                                        c8 = arith_c;
                                        v8 = arith_v;
                                        h8 = arith_h;
                                end
                        `DEC, `INC:
                                begin
                                        q8 = arith_q;
                                        v8 = arith_v;
                                end
                        `COM:
                                begin
                                        q8 = com8_r;
                                        c8 = com8_r;
                                        v8 = vcom8_r;
                                end
                        `NEG:
                                begin
                                        q8 = neg8_r;
                                        c8 = cneg8_r;
                                        v8 = vneg8_r;
                                end
                        `LSR, `LSL, `ROL, `ROR,`ASR:
                                begin
                                        q8 = shift_q;
                                        c8 = shift_c;
                                        v8 = shift_v;
                                end
                        `AND, `OR, `EOR, `LD:
                                begin
                                        q8 = logic_q;
                                        v8 = 1'b0;
                                        end
                        `DAA:
                                begin // V is undefined, so we don't touch it
                                        q8 = { daa8h_r, daa_p0_r[3:0] };
                                        c8 = cdaa8_r;
                                end
                        `ST:
                                begin
                                        q8 = a_in[7:0];
                                end
                endcase
        end
/*
reg [7:0] regq8;
// register before second mux
always @(posedge clk_in)
        begin
                regq8 <= q8;
        end
*/
always @(*)
        begin
                q_out[7:0] = q8; //regq8;
                CCRo = { CCR[7:6], h8, CCR[4], q8[7], (q8 == 8'h0), v8, c8 };
        end
 
initial
        begin
        end
endmodule
 
/* ALU for 16 bit operations */
module alu16(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        input wire [15:0] q_mul_in,
        output reg [15:0] q_out, /* ALU result */
        output reg [3:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
 
`ifdef HD6309
wire [15:0] com16_r, neg16_r;
wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r;
 
wire [15:0] com16_w, neg16_w;
wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;
 
wire ccom16_r, cneg16_r;
wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r;
 
wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;
wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;
 
assign com16_w = ~a_in[15:0];
assign neg16_w = 16'h0 - a_in[15:0];
assign asr16_w = { a_in[15], a_in[15:1] };
assign shr16_w = { 1'b0, a_in[15:1] };
assign shl16_w = { a_in[14:0], 1'b0 };
assign ror16_w = { c_in, a_in[15:1] };
assign rol16_w = { a_in[14:0], c_in };
assign and16_w = a_in[15:0] & b_in[15:0];
assign or16_w = a_in[15:0] | b_in[15:0];
assign eor16_w = a_in[15:0] ^ b_in[15:0];
 
// COM
assign com16_r = com16_w;
assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;
assign vcom16_r = 1'b0;
                // NEG
assign neg16_r = neg16_w;
assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);
assign cneg16_r = neg16_w[15] | neg16_w[14] | neg16_w[13] | neg16_w[12] | neg16_w[11] | neg16_w[10] | neg16_w[9] & neg16_w[8] | neg16_w[7] | neg16_w[6] | neg16_w[5] | neg16_w[4] | neg16_w[3] | neg16_w[2] | neg16_w[1] | neg16_w[0];
                // ASR
assign asr16_r = asr16_w;
assign casr16_r = a_in[0];
assign vasr16_r = a_in[0] ^ asr16_w[15];
                // SHR
assign shr16_r = shr16_w;
assign cshr16_r = a_in[0];
assign vshr16_r = a_in[0] ^ shr16_w[15];
                // SHL
assign shl16_r = shl16_w;
assign cshl16_r = a_in[15];
assign vshl16_r = a_in[15] ^ shl16_w[15];
                // ROR
assign ror16_r = ror16_w;
assign cror16_r = a_in[0];
assign vror16_r = a_in[0] ^ ror16_w[15];
                // ROL
assign rol16_r = rol16_w;
assign crol16_r = a_in[15];
assign vrol16_r = a_in[15] ^ rol16_w[15];
                // AND
assign and16_r = and16_w;
assign cand16_r = c_in;
assign vand16_r = 1'b0;
                // OR
assign or16_r = or16_w;
                // EOR
assign eor16_r = eor16_w;
`endif
 
reg c16, n16, v16, z16;
reg [15:0] q16;
 
wire [15:0] arith_q;
wire arith_c, arith_v, arith_h;
 
arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);
 
always @(*)
        begin
                q16 = 16'h0;
                c16 = c_in;
                v16 = v_in;
                case (opcode_in)
                        `ADD, `ADC, `SUB, `SBC:
                                begin
                                        q16 = arith_q;
                                        c16 = arith_c;
                                        v16 = arith_v;
                                end
`ifdef HD6309
                        `COM:
                                begin
                                        q16 = com16_r;
                                        c16 = ccom16_r;
                                        v16 = vcom16_r;
                                end
                        `NEG:
                                begin
                                        q16 = neg16_r;
                                        c16 = cneg16_r;
                                        v16 = vneg16_r;
                                end
                        `ASR:
                                begin
                                        q16 = asr16_r;
                                        c16 = casr16_r;
                                        v16 = vasr16_r;
                                end
                        `LSR:
                                begin
                                        q16 = shr16_r;
                                        c16 = cshr16_r;
                                        v16 = vshr16_r;
                                end
                        `LSL:
                                begin
                                        q16 = shl16_r;
                                        c16 = cshl16_r;
                                        v16 = vshl16_r;
                                end
                        `ROR:
                                begin
                                        q16 = ror16_r;
                                        c16 = cror16_r;
                                        v16 = vror16_r;
                                end
                        `ROL:
                                begin
                                        q16 = rol16_r;
                                        c16 = crol16_r;
                                        v16 = vrol16_r;
                                end
                        `AND:
                                begin
                                        q16 = and16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                        end
                        `OR:
                                begin
                                        q16 = or16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
                        `EOR:
                                begin
                                        q16 = eor16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
`endif
                        `MUL:
                                begin
                                        q16 = q_mul_in;
                                        c16 = q_mul_in[7];
                                end
                        `LD:
                                begin
                                        v16 = 0;
                                        q16 = b_in[15:0];
                                end
                        `ST:
                                begin
                                        q16 = a_in[15:0];
                                end
                        `SEXT: // sign extend
                                begin
                                        q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };
                                end
                        `LEA:
                                begin
                                        q16 = a_in[15:0];
                                end
                endcase
        end
 
reg [15:0] regq16;
reg reg_n_in, reg_z_in;
/* register before second mux */
always @(posedge clk_in)
        begin
                regq16 <= q16;
                reg_n_in <= n_in;
                reg_z_in <= z_in;
        end
 
/* Negative & zero flags */
always @(*)
        begin
                n16 = q16[15];
                z16 = q16 == 16'h0;
                case (opcode_in)
                        `ADD:
                                begin
                                end
                        `ADC:
                                begin
                                end
                        `SUB: // for CMP no register result is written back
                                begin
                                end
                        `SBC:
                                begin
                                end
                        `COM:
                                begin
                                end
                        `NEG:
                                begin
                                end
                        `ASR:
                                begin
                                end
                        `LSR:
                                begin
                                end
                        `LSL:
                                begin
                                end
                        `ROR:
                                begin
                                end
                        `ROL:
                                begin
                                end
                        `AND:
                                begin
                                end
                        `OR:
                                begin
                                end
                        `EOR:
                                begin
                                end
                        `MUL:
                                begin
                                        n16 = reg_n_in;
                                end
                        `LD:
                                begin
                                end
                        `ST:
                                begin
                                end
                        `SEXT: // sign extend
                                begin
                                        n16 = reg_n_in;
                                        z16 = reg_z_in;
                                end
                        `LEA: // only Z will be affected
                                begin
                                        n16 = reg_n_in;
                                end
                endcase
        end
 
 
always @(*)
        begin
                q_out = q16;
                CCRo = { n16, z16, v16, c16 };
        end
 
endmodule
 
module mul8x8(
        input wire clk_in,
        input wire [7:0] a,
        input wire [7:0] b,
        output wire [15:0] q
        );
 
reg [15:0] pipe0, pipe1;//, pipe2, pipe3;
assign q = pipe1;
 
always @(posedge clk_in)
        begin
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0) +
                         (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0);
                pipe1 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) +
                         (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe0;
                /*
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0);
                pipe1 <= (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0) + pipe0;
                pipe2 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) + pipe1;
                pipe3 <= (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe2;
                */
        end
 
endmodule

Line No.	Rev	Author	Line
1	4	ale500	`/*`
2			`* (c) 2013 Alejandro Paz`
3			`*`
4			`*`
5			`* An alu core`
6			`*`
7			`* ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL`
8			`*`
9			`*`
10			`*`
11			`*/`
12			`include "defs.v"
13	6	ale500
14
15			`module alu(`
16			`input wire clk_in,`
17	4	ale500	`input wire [15:0] a_in,`
18			`input wire [15:0] b_in,`
19			`input wire [7:0] CCR, /* condition code register */`
20			`input wire [4:0] opcode_in, /* ALU opcode */`
21			`input wire sz_in, /* size, low 8 bit, high 16 bit */`
22			`output reg [15:0] q_out, /* ALU result */`
23			`output reg [7:0] CCRo`
24			`);`
25	2	ale500
26	6	ale500	`wire [7:0] ccr8_out, q8_out;`
27			`wire [15:0] q16_out;`
28			`wire [3:0] ccr16_out;`
29	12	ale500	`wire [15:0] q16_mul;`
30	6	ale500	`reg [15:0] ra_in, rb_in;`
31	9	ale500	`reg [4:0] rop_in;`
32	12	ale500
33
34			`mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);`
35	9	ale500	`alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);`
36	12	ale500	`alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_mul, q16_out, ccr16_out);`
37
38	6	ale500
39			`always @(posedge clk_in)`
40			`begin`
41			`ra_in <= a_in;`
42			`rb_in <= b_in;`
43	9	ale500	`rop_in <= opcode_in;`
44	6	ale500	`end`
45
46			`always @(*)`
47			`begin`
48			`if (sz_in)`
49			`begin`
50			`q_out = q16_out;`
51			`CCRo = { CCR[7:4], ccr16_out };`
52			`end`
53			`else`
54			`begin`
55			`q_out = { 8'h0, q8_out };`
56			`CCRo = ccr8_out;`
57			`end`
58			`end`
59	9	ale500
60	6	ale500
61			`endmodule`
62	9	ale500	`/**`
63			`* Simple 3 functions logic`
64			`*`
65			`*/`
66			`module logic8(`
67			`input wire [7:0] a_in,`
68			`input wire [7:0] b_in,`
69			`input wire [1:0] opcode_in, /* ALU opcode */`
70			`output reg [7:0] q_out /* ALU result */`
71			`);`
72	6	ale500
73	9	ale500	`always @(*)`
74			`begin`
75			`case (opcode_in)`
76			`2'b00: q_out = b_in;`
77			`2'b01: q_out = a_in & b_in;`
78			`2'b10: q_out = a_in \| b_in;`
79			`2'b11: q_out = a_in ^ b_in;`
80			`endcase`
81			`end`
82
83			`endmodule`
84
85			`/**`
86			`* Simple ADD/SUB module`
87			`*`
88			`*/`
89			`module arith8(`
90			`input wire [7:0] a_in,`
91			`input wire [7:0] b_in,`
92			`input wire carry_in, /* condition code register */`
93			`input wire half_c_in,`
94			`input wire [1:0] opcode_in, /* ALU opcode */`
95			`output reg [7:0] q_out, /* ALU result */`
96			`output reg carry_out,`
97			`output reg overflow_out,`
98			`output reg half_c_out`
99			`);`
100	10	ale500
101			`wire carry;`
102			`assign carry = opcode_in[1] ? carry_in:1'b0;`
103	9	ale500
104			`always @(*)`
105			`begin`
106	10	ale500	`case (opcode_in[0])`
107			`1'b0: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry }; // ADD/ADC`
108			`1'b1: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry }; // SUB/SBC`
109	9	ale500	`endcase`
110			`end`
111
112			`always @(*)`
113			`begin`
114	10	ale500	`case (opcode_in[0])`
115			`1'b0: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) \| ((~a_in[7]) & (~b_in[7]) & q_out[7]);`
116			`1'b1: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) \| ((~a_in[7]) & b_in[7] & q_out[7]);`
117	9	ale500	`endcase`
118			`end`
119
120			`always @(*)`
121			`begin`
122	10	ale500	`case (opcode_in[0])`
123	12	ale500	`1'b0: half_c_out = (a_in[4] ^ b_in[4] ^ q_out[4]);`
124	10	ale500	`1'b1: half_c_out = half_c_in;`
125	9	ale500	`endcase`
126			`end`
127
128			`endmodule`
129
130			`/**`
131			`* Simple ADD/SUB module`
132			`*`
133			`*/`
134			`module arith16(`
135			`input wire [15:0] a_in,`
136			`input wire [15:0] b_in,`
137			`input wire carry_in, /* condition code register */`
138			`input wire [1:0] opcode_in, /* ALU opcode */`
139			`output reg [15:0] q_out, /* ALU result */`
140			`output reg carry_out,`
141			`output reg overflow_out`
142			`);`
143			`always @(*)`
144			`begin`
145			`case (opcode_in)`
146			`2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD`
147			`2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB`
148			`2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC`
149			`2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC`
150			`endcase`
151			`end`
152
153			`always @(*)`
154			`begin`
155			`case (opcode_in)`
156			`2'b00, 2'b10: overflow_out = (a_in[15] & b_in[15] & (~q_out[15])) \| ((~a_in[15]) & (~b_in[15]) & q_out[7]);`
157			`2'b01, 2'b11: overflow_out = (a_in[15] & (~b_in[15]) & (~q_out[15])) \| ((~a_in[15]) & b_in[15] & q_out[7]);`
158			`endcase`
159			`end`
160
161			`endmodule`
162
163			`module shift8(`
164			`input wire [7:0] a_in,`
165			`input wire [7:0] b_in,`
166			`input wire carry_in, /* condition code register */`
167			`input wire overflow_in, /* condition code register */`
168			`input wire [2:0] opcode_in, /* ALU opcode */`
169			`output reg [7:0] q_out, /* ALU result */`
170			`output wire carry_out,`
171			`output reg overflow_out`
172			`);`
173
174			`always @(*)`
175			`begin`
176			`q_out = { a_in[7], a_in[7:1] }; // ASR`
177			`case (opcode_in)`
178			`3'b000: q_out = { 1'b0, a_in[7:1] }; // LSR`
179			`3'b001: q_out = { a_in[6:0], 1'b0 }; // LSL`
180			`3'b010: q_out = { carry_in, a_in[7:1] }; // ROR`
181			`3'b011: q_out = { a_in[6:0], carry_in }; // ROL`
182			`3'b100: q_out = { a_in[7], a_in[7:1] }; // ASR`
183			`endcase`
184			`end`
185
186			`always @(*)`
187			`begin`
188			`overflow_out = overflow_in;`
189			`case (opcode_in)`
190			`3'b000: overflow_out = overflow_in; // LSR`
191			`3'b001: overflow_out = a_in[7] ^ a_in[6]; // LSL`
192			`3'b010: overflow_out = overflow_in; // ROR`
193			`3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL`
194			`3'b100: overflow_out = overflow_in; // ASR`
195			`endcase`
196			`end`
197
198	12	ale500	`assign carry_out = opcode_in[0] ? a_in[7]:a_in[0];`
199	9	ale500
200			`endmodule`
201
202
203	6	ale500	`module alu8(`
204			`input wire clk_in,`
205	9	ale500	`input wire [7:0] a_in,`
206			`input wire [7:0] b_in,`
207	6	ale500	`input wire [7:0] CCR, /* condition code register */`
208			`input wire [4:0] opcode_in, /* ALU opcode */`
209			`output reg [7:0] q_out, /* ALU result */`
210			`output reg [7:0] CCRo`
211			`);`
212
213			`wire c_in, n_in, v_in, z_in, h_in;`
214			`assign c_in = CCR[0]; /* carry flag */`
215			`assign n_in = CCR[3]; /* neg flag */`
216			`assign v_in = CCR[1]; /* overflow flag */`
217			`assign z_in = CCR[2]; /* zero flag */`
218			`assign h_in = CCR[5]; /* halb-carry flag */`
219
220	12	ale500	`wire [7:0] com8_r, neg8_r, daa_p0_r;`
221			`wire [3:0] daa8h_r;`
222	6	ale500
223	9	ale500	`wire [7:0] com8_w, neg8_w;`
224	6	ale500
225	9	ale500	`wire ccom8_r, cneg8_r, cdaa8_r;`
226	6	ale500
227	9	ale500	`wire vcom8_r, vneg8_r;`
228	6	ale500
229			`assign com8_w = ~a_in[7:0];`
230			`assign neg8_w = 8'h0 - a_in[7:0];`
231			`// COM`
232			`assign com8_r = com8_w;`
233			`assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;`
234			`assign vcom8_r = 1'b0;`
235			`// NEG`
236			`assign neg8_r = neg8_w;`
237			`assign cneg8_r = neg8_w[7] \| neg8_w[6] \| neg8_w[5] \| neg8_w[4] \| neg8_w[3] \| neg8_w[2] \| neg8_w[1] \| neg8_w[0];`
238			`assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);`
239
240			`reg c8, h8, n8, v8, z8;`
241			`reg [7:0] q8;`
242	9	ale500
243			`wire [7:0] logic_q, arith_q, shift_q;`
244			`wire arith_c, arith_v, arith_h;`
245			`wire shift_c, shift_v;`
246
247			`logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);`
248			`arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);`
249			`shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);`
250	12	ale500	`// DAA`
251			`assign daa_p0_r = ((a_in[3:0] > 4'h9) \| h_in ) ? a_in[7:0] + 8'h6:a_in[7:0];`
252			`assign { cdaa8_r, daa8h_r } = ((daa_p0_r[7:4] > 9) \|\| (c_in == 1'b1)) ? { 1'b0, daa_p0_r[7:4] } + 5'h6:{ 1'b0, daa_p0_r[7:4] };`
253	9	ale500
254	6	ale500	`always @(*)`
255			`begin`
256			`q8 = 8'h0;`
257			`c8 = c_in;`
258			`h8 = h_in;`
259			`v8 = v_in;`
260			`case (opcode_in)`
261	12	ale500	`SEXT:
262			`begin`
263			`q8 = a_in[7] ? 8'hff:8'h00;`
264			`end`
265	9	ale500	`ADD, `ADC, `SUB, `SBC:
266	6	ale500	`begin`
267	9	ale500	`q8 = arith_q;`
268			`c8 = arith_c;`
269			`v8 = arith_v;`
270			`h8 = arith_h;`
271	6	ale500	`end`
272	12	ale500	`DEC, `INC:
273			`begin`
274			`q8 = arith_q;`
275			`v8 = arith_v;`
276			`end`
277	6	ale500	`COM:
278			`begin`
279			`q8 = com8_r;`
280			`c8 = com8_r;`
281			`v8 = vcom8_r;`
282			`end`
283			`NEG:
284			`begin`
285			`q8 = neg8_r;`
286			`c8 = cneg8_r;`
287			`v8 = vneg8_r;`
288			`end`
289	9	ale500	`LSR, `LSL, `ROL, `ROR,`ASR:
290	6	ale500	`begin`
291	9	ale500	`q8 = shift_q;`
292			`c8 = shift_c;`
293			`v8 = shift_v;`
294	6	ale500	`end`
295	9	ale500	`AND, `OR, `EOR, `LD:
296	6	ale500	`begin`
297	9	ale500	`q8 = logic_q;`
298			`v8 = 1'b0;`
299	6	ale500	`end`
300			`DAA:
301			`begin // V is undefined, so we don't touch it`
302	12	ale500	`q8 = { daa8h_r, daa_p0_r[3:0] };`
303	6	ale500	`c8 = cdaa8_r;`
304			`end`
305			`ST:
306			`begin`
307			`q8 = a_in[7:0];`
308			`end`
309			`endcase`
310			`end`
311	12	ale500	`/*`
312	6	ale500	`reg [7:0] regq8;`
313	12	ale500	`// register before second mux`
314	6	ale500	`always @(posedge clk_in)`
315			`begin`
316			`regq8 <= q8;`
317			`end`
318	12	ale500	`*/`
319	6	ale500	`always @(*)`
320			`begin`
321			`q_out[7:0] = q8; //regq8;`
322	12	ale500	`CCRo = { CCR[7:6], h8, CCR[4], q8[7], (q8 == 8'h0), v8, c8 };`
323	6	ale500	`end`
324
325			`initial`
326			`begin`
327			`end`
328			`endmodule`
329
330			`/* ALU for 16 bit operations */`
331			`module alu16(`
332			`input wire clk_in,`
333			`input wire [15:0] a_in,`
334			`input wire [15:0] b_in,`
335			`input wire [7:0] CCR, /* condition code register */`
336			`input wire [4:0] opcode_in, /* ALU opcode */`
337	12	ale500	`input wire [15:0] q_mul_in,`
338	6	ale500	`output reg [15:0] q_out, /* ALU result */`
339			`output reg [3:0] CCRo`
340			`);`
341
342			`wire c_in, n_in, v_in, z_in;`
343	2	ale500	`assign c_in = CCR[0]; /* carry flag */`
344			`assign n_in = CCR[3]; /* neg flag */`
345			`assign v_in = CCR[1]; /* overflow flag */`
346			`assign z_in = CCR[2]; /* zero flag */`
347
348	9	ale500	`ifdef HD6309
349			`wire [15:0] com16_r, neg16_r;`
350			`wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r;`
351	2	ale500
352	9	ale500	`wire [15:0] com16_w, neg16_w;`
353	6	ale500	`wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;`
354	2	ale500
355	9	ale500	`wire ccom16_r, cneg16_r;`
356			`wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r;`
357	2	ale500
358			`wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;`
359			`wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;`
360
361			`assign com16_w = ~a_in[15:0];`
362			`assign neg16_w = 16'h0 - a_in[15:0];`
363			`assign asr16_w = { a_in[15], a_in[15:1] };`
364			`assign shr16_w = { 1'b0, a_in[15:1] };`
365			`assign shl16_w = { a_in[14:0], 1'b0 };`
366			`assign ror16_w = { c_in, a_in[15:1] };`
367			`assign rol16_w = { a_in[14:0], c_in };`
368			`assign and16_w = a_in[15:0] & b_in[15:0];`
369			`assign or16_w = a_in[15:0] \| b_in[15:0];`
370			`assign eor16_w = a_in[15:0] ^ b_in[15:0];`
371
372	9	ale500	`// COM`
373	2	ale500	`assign com16_r = com16_w;`
374			`assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;`
375			`assign vcom16_r = 1'b0;`
376			`// NEG`
377			`assign neg16_r = neg16_w;`
378			`assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);`
379			`assign cneg16_r = neg16_w[15] \| neg16_w[14] \| neg16_w[13] \| neg16_w[12] \| neg16_w[11] \| neg16_w[10] \| neg16_w[9] & neg16_w[8] \| neg16_w[7] \| neg16_w[6] \| neg16_w[5] \| neg16_w[4] \| neg16_w[3] \| neg16_w[2] \| neg16_w[1] \| neg16_w[0];`
380			`// ASR`
381			`assign asr16_r = asr16_w;`
382			`assign casr16_r = a_in[0];`
383			`assign vasr16_r = a_in[0] ^ asr16_w[15];`
384			`// SHR`
385			`assign shr16_r = shr16_w;`
386			`assign cshr16_r = a_in[0];`
387			`assign vshr16_r = a_in[0] ^ shr16_w[15];`
388			`// SHL`
389			`assign shl16_r = shl16_w;`
390			`assign cshl16_r = a_in[15];`
391			`assign vshl16_r = a_in[15] ^ shl16_w[15];`
392			`// ROR`
393			`assign ror16_r = ror16_w;`
394			`assign cror16_r = a_in[0];`
395			`assign vror16_r = a_in[0] ^ ror16_w[15];`
396			`// ROL`
397			`assign rol16_r = rol16_w;`
398			`assign crol16_r = a_in[15];`
399			`assign vrol16_r = a_in[15] ^ rol16_w[15];`
400			`// AND`
401			`assign and16_r = and16_w;`
402			`assign cand16_r = c_in;`
403			`assign vand16_r = 1'b0;`
404			`// OR`
405			`assign or16_r = or16_w;`
406			`// EOR`
407			`assign eor16_r = eor16_w;`
408	9	ale500	`endif
409	2	ale500
410	6	ale500	`reg c16, n16, v16, z16;`
411	2	ale500	`reg [15:0] q16;`
412
413	9	ale500	`wire [15:0] arith_q;`
414			`wire arith_c, arith_v, arith_h;`
415
416			`arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);`
417
418	2	ale500	`always @(*)`
419			`begin`
420			`q16 = 16'h0;`
421			`c16 = c_in;`
422			`v16 = v_in;`
423			`case (opcode_in)`
424	9	ale500	`ADD, `ADC, `SUB, `SBC:
425	2	ale500	`begin`
426	9	ale500	`q16 = arith_q;`
427			`c16 = arith_c;`
428			`v16 = arith_v;`
429	2	ale500	`end`
430	6	ale500	`ifdef HD6309
431	2	ale500	`COM:
432			`begin`
433			`q16 = com16_r;`
434			`c16 = ccom16_r;`
435			`v16 = vcom16_r;`
436			`end`
437			`NEG:
438			`begin`
439			`q16 = neg16_r;`
440			`c16 = cneg16_r;`
441			`v16 = vneg16_r;`
442			`end`
443			`ASR:
444			`begin`
445			`q16 = asr16_r;`
446			`c16 = casr16_r;`
447			`v16 = vasr16_r;`
448			`end`
449			`LSR:
450			`begin`
451			`q16 = shr16_r;`
452			`c16 = cshr16_r;`
453			`v16 = vshr16_r;`
454			`end`
455			`LSL:
456			`begin`
457			`q16 = shl16_r;`
458			`c16 = cshl16_r;`
459			`v16 = vshl16_r;`
460			`end`
461			`ROR:
462			`begin`
463			`q16 = ror16_r;`
464			`c16 = cror16_r;`
465			`v16 = vror16_r;`
466			`end`
467			`ROL:
468			`begin`
469			`q16 = rol16_r;`
470			`c16 = crol16_r;`
471			`v16 = vrol16_r;`
472			`end`
473			`AND:
474			`begin`
475			`q16 = and16_r;`
476			`c16 = cand16_r;`
477			`v16 = vand16_r;`
478			`end`
479			`OR:
480			`begin`
481			`q16 = or16_r;`
482			`c16 = cand16_r;`
483			`v16 = vand16_r;`
484			`end`
485			`EOR:
486			`begin`
487			`q16 = eor16_r;`
488			`c16 = cand16_r;`
489			`v16 = vand16_r;`
490			`end`
491	6	ale500	`endif
492	2	ale500	`MUL:
493			`begin`
494	12	ale500	`q16 = q_mul_in;`
495			`c16 = q_mul_in[7];`
496	2	ale500	`end`
497			`LD:
498			`begin`
499			`v16 = 0;`
500			`q16 = b_in[15:0];`

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