URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [alu16.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


/*
 * (c) 2013 Alejandro Paz
 *
 *
 * An alu core
 *
 * ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL
 *
 *
 *
 */
`include "defs.v"
 
 
module alu(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        input wire sz_in, /* size, low 8 bit, high 16 bit */
        output reg [15:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire [7:0] ccr8_out, q8_out;
wire [15:0] q16_out;
wire [3:0] ccr16_out;
 
reg [15:0] ra_in, rb_in;
 
alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, opcode_in, q8_out, ccr8_out);
alu16 alu16(clk_in, ra_in, rb_in, CCR, opcode_in, q16_out, ccr16_out);
 
always @(posedge clk_in)
        begin
                ra_in <= a_in;
                rb_in <= b_in;
        end
 
always @(*)
        begin
                if (sz_in)
                        begin
                                q_out = q16_out;
                                CCRo = { CCR[7:4], ccr16_out };
                        end
                else
                        begin
                                q_out = { 8'h0, q8_out };
                                CCRo = ccr8_out;
                        end
        end
 
endmodule
 
module alu8(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in, h_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
assign h_in = CCR[5]; /* halb-carry flag */
 
 
wire [7:0] add8_r, adc8_r, sub8_r, sbc8_r, com8_r, neg8_r;
wire [7:0] asr8_r, shr8_r, shl8_r, ror8_r, rol8_r, and8_r, or8_r, eor8_r;
wire [3:0] daa8l_r, daa8h_r;
wire daa_lnm9;
 
wire [7:0] add8_w, adc8_w, com8_w, neg8_w, sub8_w, sbc8_w;
wire [7:0] asr8_w, shr8_w, shl8_w, ror8_w, rol8_w, and8_w, or8_w, eor8_w;
 
 
wire cadd8_w, cadc8_w, csub8_w, csbc8_w;
wire cadd16_w, cadc16_w, csub16_w, csbc16_w;
 
wire cadd8_r, cadc8_r, csub8_r, csbc8_r, ccom8_r, cneg8_r;
wire casr8_r, cshr8_r, cshl8_r, cror8_r, crol8_r, cand8_r, cdaa8_r;
 
wire vadd8_r, vadc8_r, vsub8_r, vsbc8_r, vcom8_r, vneg8_r;
wire vasr8_r, vshr8_r, vshl8_r, vror8_r, vrol8_r, vand8_r;
 
assign { cadd8_w, add8_w }   = { 1'b0, a_in[7:0] } + { 1'b0, b_in[7:0] };
 
assign { cadc8_w, adc8_w }   = { 1'b0, a_in[7:0] } + { 1'b0, b_in[7:0] } + { 8'h0, c_in };
 
 
assign { csub8_w, sub8_w }   = { 1'b0, a_in[7:0] } - { 1'b0, b_in[7:0] };
 
assign { csbc8_w, sbc8_w }   = { 1'b0, a_in[7:0] } - { 1'b0, b_in[7:0] } - { 8'h0, c_in };
 
 
assign com8_w = ~a_in[7:0];
 
assign neg8_w = 8'h0 - a_in[7:0];
 
 
assign asr8_w = { a_in[7], a_in[7:1] };
 
 
assign shr8_w = { 1'b0, a_in[7:1] };
 
 
assign shl8_w = { a_in[6:0], 1'b0 };
 
 
assign ror8_w = { c_in, a_in[7:1] };
 
 
assign rol8_w = { a_in[6:0], c_in };
 
 
assign and8_w = a_in[7:0] & b_in[7:0];
 
 
assign or8_w = a_in[7:0] | b_in[7:0];
 
 
assign eor8_w = a_in[7:0] ^ b_in[7:0];
 
 
                // ADD, ADC
assign { cadd8_r, add8_r } = { cadd8_w, add8_w };
assign vadd8_r = (a_in[7] & b_in[7] & (~add8_w[7])) | ((~a_in[7]) & (~b_in[7]) & add8_w[7]);
assign { cadc8_r, adc8_r } = { cadd8_w, add8_w };
assign vadc8_r = (a_in[7] & b_in[7] & (~add8_w[7])) | ((~a_in[7]) & (~b_in[7]) & adc8_w[7]);
                // SUB, SUBC
assign { csub8_r, sub8_r } = { csub8_w, sub8_w };
assign vsub8_r = (a_in[7] & (~b_in[7]) & (~sub8_w[7])) | ((~a_in[7]) & b_in[7] & sub8_w[7]);
assign { csbc8_r, sbc8_r } = { csbc8_w, sbc8_w };
assign vsbc8_r = (a_in[7] & b_in[7] | (~sbc8_w[7])) | ((~a_in[7]) & b_in[7] & sbc8_w[7]);
                // COM
assign com8_r = com8_w;
assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;
assign vcom8_r = 1'b0;
                // NEG
assign neg8_r = neg8_w;
assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];
assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);
                // ASR
assign asr8_r = asr8_w;
assign casr8_r = a_in[0];
assign vasr8_r = a_in[0] ^ asr8_w[7];
                // SHR
assign shr8_r = shr8_w;
assign cshr8_r = a_in[0];
assign vshr8_r = a_in[0] ^ shr8_w[7];
                // SHL
assign shl8_r = shl8_w;
assign cshl8_r = a_in[7];
assign vshl8_r = a_in[7] ^ shl8_w[7];
                // ROR
assign ror8_r = ror8_w;
assign cror8_r = a_in[0];
assign vror8_r = a_in[0] ^ shr8_w[7];
                // ROL
assign rol8_r = shl8_w;
assign crol8_r = a_in[7];
assign vrol8_r = a_in[7] ^ rol8_w[7];
                // AND
assign and8_r = and8_w;
assign cand8_r = c_in;
assign vand8_r = 1'b0;
                // OR
assign or8_r = or8_w;
                // EOR
assign eor8_r = eor8_w;
                // DAA
assign daa_lnm9 = (a_in[3:0] > 9);
assign daa8l_r = (daa_lnm9 | h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];
assign daa8h_r = ((a_in[7:4] > 9) || (c_in == 1'b1) || (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];
assign cdaa8_r = daa8h_r < a_in[7:4];
 
reg c8, h8, n8, v8, z8;
reg [7:0] q8;
 
always @(*)
        begin
                q8 = 8'h0;
                c8 = c_in;
                h8 = h_in;
                v8 = v_in;
                case (opcode_in)
                        `ADD:
                                begin
                                        q8 = add8_r;
                                        c8 = cadd8_r;
                                        v8 = vadd8_r;
                                end
                        `ADC:
                                begin
                                        q8 = adc8_r;
                                        c8 = cadc8_r;
                                        v8 = vadc8_r;
                                end
                        `CMP, `SUB: // for CMP no register result is written back
                                begin
                                        q8 = sub8_r;
                                        c8 = csub8_r;
                                        v8 = vsub8_r;
                                end
                        `SBC:
                                begin
                                        q8 = sbc8_r;
                                        c8 = csbc8_r;
                                        v8 = vsbc8_r;
                                end
                        `COM:
                                begin
                                        q8 = com8_r;
                                        c8 = com8_r;
                                        v8 = vcom8_r;
                                end
                        `NEG:
                                begin
                                        q8 = neg8_r;
                                        c8 = cneg8_r;
                                        v8 = vneg8_r;
                                end
                        `ASR:
                                begin
                                        q8 = asr8_r;
                                        c8 = casr8_r;
                                        v8 = vasr8_r;
                                end
                        `LSR:
                                begin
                                        q8 = shr8_r;
                                        c8 = cshr8_r;
                                        v8 = vshr8_r;
                                end
                        `LSL:
                                begin
                                        q8 = shl8_r;
                                        c8 = cshl8_r;
                                        v8 = vshl8_r;
                                end
                        `ROR:
                                begin
                                        q8 = ror8_r;
                                        c8 = cror8_r;
                                        v8 = vror8_r;
                                end
                        `ROL:
                                begin
                                        q8 = rol8_r;
                                        c8 = crol8_r;
                                        v8 = vrol8_r;
                                end
                        `AND:
                                begin
                                        q8 = and8_r;
                                        c8 = cand8_r;
                                        v8 = vand8_r;
                                        end
                        `OR:
                                begin
                                        q8 = or8_r;
                                        c8 = cand8_r;
                                        v8 = vand8_r;
                                end
                        `EOR:
                                begin
                                        q8 = eor8_r;
                                        c8 = cand8_r;
                                        v8 = vand8_r;
                                end
                        `DAA:
                                begin // V is undefined, so we don't touch it
                                        q8 = { daa8h_r, daa8l_r };
                                        c8 = cdaa8_r;
                                end
                        `MUL:
                                begin
 
                                end
                        `LD:
                                begin
                                        v8 = 0;
                                        q8 = b_in[7:0];
                                end
                        `ST:
                                begin
                                        q8 = a_in[7:0];
                                end
                endcase
        end
 
reg [7:0] regq8;
/* register before second mux */
always @(posedge clk_in)
        begin
                regq8 <= q8;
        end
 
always @(*)
        begin
                q_out[7:0] = q8; //regq8;
                case (opcode_in)
                        `ORCC:
                                CCRo = CCR | b_in[7:0];
                        `ANDCC:
                                CCRo = CCR & b_in[7:0];
                        default:
                                CCRo = { CCR[7:6], CCR[5], h8, q8[7], (q8 == 8'h0), v8, c8 };
                endcase
        end
 
initial
        begin
        end
endmodule
 
/* ALU for 16 bit operations */
module alu16(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        output reg [15:0] q_out, /* ALU result */
        output reg [3:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
 
wire [15:0] add16_r, adc16_r, sub16_r, sbc16_r, com16_r, neg16_r;
wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r, mul16_r;
 
wire [15:0] add16_w, adc16_w, com16_w, neg16_w, sub16_w, sbc16_w;
wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;
 
wire cadd16_w, cadc16_w, csub16_w, csbc16_w;
 
wire cadd16_r, cadc16_r, csub16_r, csbc16_r, ccom16_r, cneg16_r;
wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r, cmul16_r;
 
wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;
wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;
 
 
assign { cadd16_w, add16_w } = { 1'b0, a_in[15:0] } + { 1'b0, b_in[15:0] };
 
assign { cadc16_w, adc16_w } = { 1'b0, a_in[15:0] } + { 1'b0, b_in[15:0] } + { 16'h0, c_in };
 
 
assign { csub16_w, sub16_w } = { 1'b0, a_in[15:0] } - { 1'b0, b_in[15:0] };
 
assign { csbc16_w, sbc16_w } = { 1'b0, a_in[15:0] } - { 1'b0, b_in[15:0] } - { 16'h0, c_in };
 
 
assign com16_w = ~a_in[15:0];
 
assign neg16_w = 16'h0 - a_in[15:0];
 
assign asr16_w = { a_in[15], a_in[15:1] };
 
assign shr16_w = { 1'b0, a_in[15:1] };
 
assign shl16_w = { a_in[14:0], 1'b0 };
 
assign ror16_w = { c_in, a_in[15:1] };
 
assign rol16_w = { a_in[14:0], c_in };
 
assign and16_w = a_in[15:0] & b_in[15:0];
 
assign or16_w = a_in[15:0] | b_in[15:0];
 
assign eor16_w = a_in[15:0] ^ b_in[15:0];
 
                // ADD, ADC
assign { cadd16_r, add16_r } = { cadd16_w, add16_w };
assign vadd16_r = (a_in[15] & b_in[15] & (~add16_w[15])) | ((~a_in[15]) & (~b_in[15]) & add16_w[15]);
assign { cadc16_r, adc16_r } = { cadd16_w, add16_w };
assign vadc16_r = (a_in[15] & b_in[15] & (~add16_w[15])) | ((~a_in[15]) & (~b_in[15]) & adc16_w[15]);
                // SUB, SUBC
assign { csub16_r, sub16_r } = { csub16_w, sub16_w };
assign vsub16_r = (a_in[15] & b_in[15] & (~add16_w[15])) | ((~a_in[15]) & b_in[15] & sub16_w[15]);
assign { csbc16_r, sbc16_r } = { csbc16_w, sbc16_w };
assign vsbc16_r = (a_in[15] & b_in[15] & (~sbc16_w[15])) | ((~a_in[15]) & b_in[15] & sbc16_w[15]);
                // COM
assign com16_r = com16_w;
assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;
assign vcom16_r = 1'b0;
                // NEG
assign neg16_r = neg16_w;
assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);
assign cneg16_r = neg16_w[15] | neg16_w[14] | neg16_w[13] | neg16_w[12] | neg16_w[11] | neg16_w[10] | neg16_w[9] & neg16_w[8] | neg16_w[7] | neg16_w[6] | neg16_w[5] | neg16_w[4] | neg16_w[3] | neg16_w[2] | neg16_w[1] | neg16_w[0];
                // ASR
assign asr16_r = asr16_w;
assign casr16_r = a_in[0];
assign vasr16_r = a_in[0] ^ asr16_w[15];
                // SHR
assign shr16_r = shr16_w;
assign cshr16_r = a_in[0];
assign vshr16_r = a_in[0] ^ shr16_w[15];
                // SHL
assign shl16_r = shl16_w;
assign cshl16_r = a_in[15];
assign vshl16_r = a_in[15] ^ shl16_w[15];
                // ROR
assign ror16_r = ror16_w;
assign cror16_r = a_in[0];
assign vror16_r = a_in[0] ^ ror16_w[15];
                // ROL
assign rol16_r = rol16_w;
assign crol16_r = a_in[15];
assign vrol16_r = a_in[15] ^ rol16_w[15];
                // AND
assign and16_r = and16_w;
assign cand16_r = c_in;
assign vand16_r = 1'b0;
                // OR
assign or16_r = or16_w;
                // EOR
assign eor16_r = eor16_w;
 
wire [15:0] q16_mul;
 
mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], mul16_r);
assign cmul16_r = mul16_r[7];
 
reg c16, n16, v16, z16;
reg [15:0] q16;
 
always @(*)
        begin
                q16 = 16'h0;
                c16 = c_in;
                v16 = v_in;
                case (opcode_in)
                        `ADD:
                                begin
                                        q16 = add16_r;
                                        c16 = cadd16_r;
                                        v16 = vadd16_r;
                                end
                        `ADC:
                                begin
                                        q16 = adc16_r;
                                        c16 = cadc16_r;
                                        v16 = vadc16_r;
                                end
                        `CMP, `SUB: // for CMP no register result is written back
                                begin
                                        q16 = sub16_r;
                                        c16 = csub16_r;
                                        v16 = vsub16_r;
                                end
                        `SBC:
                                begin
                                        q16 = sbc16_r;
                                        c16 = csbc16_r;
                                        v16 = vsbc16_r;
                                end
`ifdef HD6309
                        `COM:
                                begin
                                        q16 = com16_r;
                                        c16 = ccom16_r;
                                        v16 = vcom16_r;
                                end
                        `NEG:
                                begin
                                        q16 = neg16_r;
                                        c16 = cneg16_r;
                                        v16 = vneg16_r;
                                end
                        `ASR:
                                begin
                                        q16 = asr16_r;
                                        c16 = casr16_r;
                                        v16 = vasr16_r;
                                end
                        `LSR:
                                begin
                                        q16 = shr16_r;
                                        c16 = cshr16_r;
                                        v16 = vshr16_r;
                                end
                        `LSL:
                                begin
                                        q16 = shl16_r;
                                        c16 = cshl16_r;
                                        v16 = vshl16_r;
                                end
                        `ROR:
                                begin
                                        q16 = ror16_r;
                                        c16 = cror16_r;
                                        v16 = vror16_r;
                                end
                        `ROL:
                                begin
                                        q16 = rol16_r;
                                        c16 = crol16_r;
                                        v16 = vrol16_r;
                                end
                        `AND:
                                begin
                                        q16 = and16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                        end
                        `OR:
                                begin
                                        q16 = or16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
                        `EOR:
                                begin
                                        q16 = eor16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
`endif
                        `MUL:
                                begin
                                        q16 = mul16_r;
                                        c16 = cmul16_r;
                                end
                        `LD:
                                begin
                                        v16 = 0;
                                        q16 = b_in[15:0];
                                end
                        `ST:
                                begin
                                        q16 = a_in[15:0];
                                end
                        `SEXT: // sign extend
                                begin
                                        q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };
                                end
                        `LEA:
                                begin
                                        q16 = a_in[15:0];
                                end
                endcase
        end
 
reg [15:0] regq16;
reg reg_n_in, reg_z_in;
/* register before second mux */
always @(posedge clk_in)
        begin
                regq16 <= q16;
                reg_n_in <= n_in;
                reg_z_in <= z_in;
        end
 
/* Negative & zero flags */
always @(*)
        begin
                n16 = q16[15];
                z16 = q16 == 16'h0;
                case (opcode_in)
                        `ADD:
                                begin
                                end
                        `ADC:
                                begin
                                end
                        `CMP, `SUB: // for CMP no register result is written back
                                begin
                                end
                        `SBC:
                                begin
                                end
                        `COM:
                                begin
                                end
                        `NEG:
                                begin
                                end
                        `ASR:
                                begin
                                end
                        `LSR:
                                begin
                                end
                        `LSL:
                                begin
                                end
                        `ROR:
                                begin
                                end
                        `ROL:
                                begin
                                end
                        `AND:
                                begin
                                end
                        `OR:
                                begin
                                end
                        `EOR:
                                begin
                                end
                        `MUL:
                                begin
                                        n16 = reg_n_in;
                                end
                        `LD:
                                begin
                                end
                        `ST:
                                begin
                                end
                        `SEXT: // sign extend
                                begin
                                        n16 = reg_n_in;
                                        z16 = reg_z_in;
                                end
                        `LEA: // only Z will be affected
                                begin
                                        n16 = reg_n_in;
                                end
                endcase
        end
 
 
always @(*)
        begin
                q_out = q16;
                CCRo = { n16, z16, v16, c16 };
        end
 
initial
        begin
        end
endmodule
 
module mul8x8(
        input wire clk_in,
        input wire [7:0] a,
        input wire [7:0] b,
        output wire [15:0] q
        );
 
reg [15:0] pipe0, pipe1;//, pipe2, pipe3;
assign q = pipe1;
 
always @(posedge clk_in)
        begin
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0) +
                         (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0);
                pipe1 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) +
                         (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe0;
                /*
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0);
                pipe1 <= (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0) + pipe0;
                pipe2 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) + pipe1;
                pipe3 <= (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe2;
                */
        end
 
endmodule

Browse

Tools

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [alu16.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	4	ale500	`/*`
2			`* (c) 2013 Alejandro Paz`
3			`*`
4			`*`
5			`* An alu core`
6			`*`
7			`* ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL`
8			`*`
9			`*`
10			`*`
11			`*/`
12			`include "defs.v"
13	6	ale500
14
15			`module alu(`
16			`input wire clk_in,`
17	4	ale500	`input wire [15:0] a_in,`
18			`input wire [15:0] b_in,`
19			`input wire [7:0] CCR, /* condition code register */`
20			`input wire [4:0] opcode_in, /* ALU opcode */`
21			`input wire sz_in, /* size, low 8 bit, high 16 bit */`
22			`output reg [15:0] q_out, /* ALU result */`
23			`output reg [7:0] CCRo`
24			`);`
25	2	ale500
26	6	ale500	`wire [7:0] ccr8_out, q8_out;`
27			`wire [15:0] q16_out;`
28			`wire [3:0] ccr16_out;`
29
30			`reg [15:0] ra_in, rb_in;`
31
32			`alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, opcode_in, q8_out, ccr8_out);`
33			`alu16 alu16(clk_in, ra_in, rb_in, CCR, opcode_in, q16_out, ccr16_out);`
34
35			`always @(posedge clk_in)`
36			`begin`
37			`ra_in <= a_in;`
38			`rb_in <= b_in;`
39			`end`
40
41			`always @(*)`
42			`begin`
43			`if (sz_in)`
44			`begin`
45			`q_out = q16_out;`
46			`CCRo = { CCR[7:4], ccr16_out };`
47			`end`
48			`else`
49			`begin`
50			`q_out = { 8'h0, q8_out };`
51			`CCRo = ccr8_out;`
52			`end`
53			`end`
54
55			`endmodule`
56
57			`module alu8(`
58			`input wire clk_in,`
59			`input wire [15:0] a_in,`
60			`input wire [15:0] b_in,`
61			`input wire [7:0] CCR, /* condition code register */`
62			`input wire [4:0] opcode_in, /* ALU opcode */`
63			`output reg [7:0] q_out, /* ALU result */`
64			`output reg [7:0] CCRo`
65			`);`
66
67			`wire c_in, n_in, v_in, z_in, h_in;`
68			`assign c_in = CCR[0]; /* carry flag */`
69			`assign n_in = CCR[3]; /* neg flag */`
70			`assign v_in = CCR[1]; /* overflow flag */`
71			`assign z_in = CCR[2]; /* zero flag */`
72			`assign h_in = CCR[5]; /* halb-carry flag */`
73
74
75			`wire [7:0] add8_r, adc8_r, sub8_r, sbc8_r, com8_r, neg8_r;`
76			`wire [7:0] asr8_r, shr8_r, shl8_r, ror8_r, rol8_r, and8_r, or8_r, eor8_r;`
77			`wire [3:0] daa8l_r, daa8h_r;`
78			`wire daa_lnm9;`
79
80			`wire [7:0] add8_w, adc8_w, com8_w, neg8_w, sub8_w, sbc8_w;`
81			`wire [7:0] asr8_w, shr8_w, shl8_w, ror8_w, rol8_w, and8_w, or8_w, eor8_w;`
82
83
84			`wire cadd8_w, cadc8_w, csub8_w, csbc8_w;`
85			`wire cadd16_w, cadc16_w, csub16_w, csbc16_w;`
86
87			`wire cadd8_r, cadc8_r, csub8_r, csbc8_r, ccom8_r, cneg8_r;`
88			`wire casr8_r, cshr8_r, cshl8_r, cror8_r, crol8_r, cand8_r, cdaa8_r;`
89
90			`wire vadd8_r, vadc8_r, vsub8_r, vsbc8_r, vcom8_r, vneg8_r;`
91			`wire vasr8_r, vshr8_r, vshl8_r, vror8_r, vrol8_r, vand8_r;`
92
93			`assign { cadd8_w, add8_w } = { 1'b0, a_in[7:0] } + { 1'b0, b_in[7:0] };`
94
95			`assign { cadc8_w, adc8_w } = { 1'b0, a_in[7:0] } + { 1'b0, b_in[7:0] } + { 8'h0, c_in };`
96
97
98			`assign { csub8_w, sub8_w } = { 1'b0, a_in[7:0] } - { 1'b0, b_in[7:0] };`
99
100			`assign { csbc8_w, sbc8_w } = { 1'b0, a_in[7:0] } - { 1'b0, b_in[7:0] } - { 8'h0, c_in };`
101
102
103			`assign com8_w = ~a_in[7:0];`
104
105			`assign neg8_w = 8'h0 - a_in[7:0];`
106
107
108			`assign asr8_w = { a_in[7], a_in[7:1] };`
109
110
111			`assign shr8_w = { 1'b0, a_in[7:1] };`
112
113
114			`assign shl8_w = { a_in[6:0], 1'b0 };`
115
116
117			`assign ror8_w = { c_in, a_in[7:1] };`
118
119
120			`assign rol8_w = { a_in[6:0], c_in };`
121
122
123			`assign and8_w = a_in[7:0] & b_in[7:0];`
124
125
126			`assign or8_w = a_in[7:0] \| b_in[7:0];`
127
128
129			`assign eor8_w = a_in[7:0] ^ b_in[7:0];`
130
131
132			`// ADD, ADC`
133			`assign { cadd8_r, add8_r } = { cadd8_w, add8_w };`
134			`assign vadd8_r = (a_in[7] & b_in[7] & (~add8_w[7])) \| ((~a_in[7]) & (~b_in[7]) & add8_w[7]);`
135			`assign { cadc8_r, adc8_r } = { cadd8_w, add8_w };`
136			`assign vadc8_r = (a_in[7] & b_in[7] & (~add8_w[7])) \| ((~a_in[7]) & (~b_in[7]) & adc8_w[7]);`
137			`// SUB, SUBC`
138			`assign { csub8_r, sub8_r } = { csub8_w, sub8_w };`
139			`assign vsub8_r = (a_in[7] & (~b_in[7]) & (~sub8_w[7])) \| ((~a_in[7]) & b_in[7] & sub8_w[7]);`
140			`assign { csbc8_r, sbc8_r } = { csbc8_w, sbc8_w };`
141			`assign vsbc8_r = (a_in[7] & b_in[7] \| (~sbc8_w[7])) \| ((~a_in[7]) & b_in[7] & sbc8_w[7]);`
142			`// COM`
143			`assign com8_r = com8_w;`
144			`assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;`
145			`assign vcom8_r = 1'b0;`
146			`// NEG`
147			`assign neg8_r = neg8_w;`
148			`assign cneg8_r = neg8_w[7] \| neg8_w[6] \| neg8_w[5] \| neg8_w[4] \| neg8_w[3] \| neg8_w[2] \| neg8_w[1] \| neg8_w[0];`
149			`assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);`
150			`// ASR`
151			`assign asr8_r = asr8_w;`
152			`assign casr8_r = a_in[0];`
153			`assign vasr8_r = a_in[0] ^ asr8_w[7];`
154			`// SHR`
155			`assign shr8_r = shr8_w;`
156			`assign cshr8_r = a_in[0];`
157			`assign vshr8_r = a_in[0] ^ shr8_w[7];`
158			`// SHL`
159			`assign shl8_r = shl8_w;`
160			`assign cshl8_r = a_in[7];`
161			`assign vshl8_r = a_in[7] ^ shl8_w[7];`
162			`// ROR`
163			`assign ror8_r = ror8_w;`
164			`assign cror8_r = a_in[0];`
165			`assign vror8_r = a_in[0] ^ shr8_w[7];`
166			`// ROL`
167			`assign rol8_r = shl8_w;`
168			`assign crol8_r = a_in[7];`
169			`assign vrol8_r = a_in[7] ^ rol8_w[7];`
170			`// AND`
171			`assign and8_r = and8_w;`
172			`assign cand8_r = c_in;`
173			`assign vand8_r = 1'b0;`
174			`// OR`
175			`assign or8_r = or8_w;`
176			`// EOR`
177			`assign eor8_r = eor8_w;`
178			`// DAA`
179			`assign daa_lnm9 = (a_in[3:0] > 9);`
180			`assign daa8l_r = (daa_lnm9 \| h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];`
181			`assign daa8h_r = ((a_in[7:4] > 9) \|\| (c_in == 1'b1) \|\| (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];`
182			`assign cdaa8_r = daa8h_r < a_in[7:4];`
183
184			`reg c8, h8, n8, v8, z8;`
185			`reg [7:0] q8;`
186
187			`always @(*)`
188			`begin`
189			`q8 = 8'h0;`
190			`c8 = c_in;`
191			`h8 = h_in;`
192			`v8 = v_in;`
193			`case (opcode_in)`
194			`ADD:
195			`begin`
196			`q8 = add8_r;`
197			`c8 = cadd8_r;`
198			`v8 = vadd8_r;`
199			`end`
200			`ADC:
201			`begin`
202			`q8 = adc8_r;`
203			`c8 = cadc8_r;`
204			`v8 = vadc8_r;`
205			`end`
206			`CMP, `SUB: // for CMP no register result is written back
207			`begin`
208			`q8 = sub8_r;`
209			`c8 = csub8_r;`
210			`v8 = vsub8_r;`
211			`end`
212			`SBC:
213			`begin`
214			`q8 = sbc8_r;`
215			`c8 = csbc8_r;`
216			`v8 = vsbc8_r;`
217			`end`
218			`COM:
219			`begin`
220			`q8 = com8_r;`
221			`c8 = com8_r;`
222			`v8 = vcom8_r;`
223			`end`
224			`NEG:
225			`begin`
226			`q8 = neg8_r;`
227			`c8 = cneg8_r;`
228			`v8 = vneg8_r;`
229			`end`
230			`ASR:
231			`begin`
232			`q8 = asr8_r;`
233			`c8 = casr8_r;`
234			`v8 = vasr8_r;`
235			`end`
236			`LSR:
237			`begin`
238			`q8 = shr8_r;`
239			`c8 = cshr8_r;`
240			`v8 = vshr8_r;`
241			`end`
242			`LSL:
243			`begin`
244			`q8 = shl8_r;`
245			`c8 = cshl8_r;`
246			`v8 = vshl8_r;`
247			`end`
248			`ROR:
249			`begin`
250			`q8 = ror8_r;`
251			`c8 = cror8_r;`
252			`v8 = vror8_r;`
253			`end`
254			`ROL:
255			`begin`
256			`q8 = rol8_r;`
257			`c8 = crol8_r;`
258			`v8 = vrol8_r;`
259			`end`
260			`AND:
261			`begin`
262			`q8 = and8_r;`
263			`c8 = cand8_r;`
264			`v8 = vand8_r;`
265			`end`
266			`OR:
267			`begin`
268			`q8 = or8_r;`
269			`c8 = cand8_r;`
270			`v8 = vand8_r;`
271			`end`
272			`EOR:
273			`begin`
274			`q8 = eor8_r;`
275			`c8 = cand8_r;`
276			`v8 = vand8_r;`
277			`end`
278			`DAA:
279			`begin // V is undefined, so we don't touch it`
280			`q8 = { daa8h_r, daa8l_r };`
281			`c8 = cdaa8_r;`
282			`end`
283			`MUL:
284			`begin`
285
286			`end`
287			`LD:
288			`begin`
289			`v8 = 0;`
290			`q8 = b_in[7:0];`
291			`end`
292			`ST:
293			`begin`
294			`q8 = a_in[7:0];`
295			`end`
296			`endcase`
297			`end`
298
299			`reg [7:0] regq8;`
300			`/* register before second mux */`
301			`always @(posedge clk_in)`
302			`begin`
303			`regq8 <= q8;`
304			`end`
305
306			`always @(*)`
307			`begin`
308			`q_out[7:0] = q8; //regq8;`
309			`case (opcode_in)`
310			`ORCC:
311			`CCRo = CCR \| b_in[7:0];`
312			`ANDCC:
313			`CCRo = CCR & b_in[7:0];`
314			`default:`
315			`CCRo = { CCR[7:6], CCR[5], h8, q8[7], (q8 == 8'h0), v8, c8 };`
316			`endcase`
317			`end`
318
319			`initial`
320			`begin`
321			`end`
322			`endmodule`
323
324			`/* ALU for 16 bit operations */`
325			`module alu16(`
326			`input wire clk_in,`
327			`input wire [15:0] a_in,`
328			`input wire [15:0] b_in,`
329			`input wire [7:0] CCR, /* condition code register */`
330			`input wire [4:0] opcode_in, /* ALU opcode */`
331			`output reg [15:0] q_out, /* ALU result */`
332			`output reg [3:0] CCRo`
333			`);`
334
335			`wire c_in, n_in, v_in, z_in;`
336	2	ale500	`assign c_in = CCR[0]; /* carry flag */`
337			`assign n_in = CCR[3]; /* neg flag */`
338			`assign v_in = CCR[1]; /* overflow flag */`
339			`assign z_in = CCR[2]; /* zero flag */`
340
341			`wire [15:0] add16_r, adc16_r, sub16_r, sbc16_r, com16_r, neg16_r;`
342			`wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r, mul16_r;`
343
344			`wire [15:0] add16_w, adc16_w, com16_w, neg16_w, sub16_w, sbc16_w;`
345	6	ale500	`wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;`
346	2	ale500
347			`wire cadd16_w, cadc16_w, csub16_w, csbc16_w;`
348
349			`wire cadd16_r, cadc16_r, csub16_r, csbc16_r, ccom16_r, cneg16_r;`
350			`wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r, cmul16_r;`
351	6	ale500
352	2	ale500	`wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;`
353			`wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;`
354
355	6	ale500
356	2	ale500	`assign { cadd16_w, add16_w } = { 1'b0, a_in[15:0] } + { 1'b0, b_in[15:0] };`
357	6	ale500
358	2	ale500	`assign { cadc16_w, adc16_w } = { 1'b0, a_in[15:0] } + { 1'b0, b_in[15:0] } + { 16'h0, c_in };`
359
360	6	ale500
361	2	ale500	`assign { csub16_w, sub16_w } = { 1'b0, a_in[15:0] } - { 1'b0, b_in[15:0] };`
362	6	ale500
363	2	ale500	`assign { csbc16_w, sbc16_w } = { 1'b0, a_in[15:0] } - { 1'b0, b_in[15:0] } - { 16'h0, c_in };`
364
365	6	ale500
366	2	ale500	`assign com16_w = ~a_in[15:0];`
367	6	ale500
368	2	ale500	`assign neg16_w = 16'h0 - a_in[15:0];`
369
370			`assign asr16_w = { a_in[15], a_in[15:1] };`
371
372			`assign shr16_w = { 1'b0, a_in[15:1] };`
373
374			`assign shl16_w = { a_in[14:0], 1'b0 };`
375
376			`assign ror16_w = { c_in, a_in[15:1] };`
377
378			`assign rol16_w = { a_in[14:0], c_in };`
379
380			`assign and16_w = a_in[15:0] & b_in[15:0];`
381
382			`assign or16_w = a_in[15:0] \| b_in[15:0];`
383
384			`assign eor16_w = a_in[15:0] ^ b_in[15:0];`
385
386			`// ADD, ADC`
387			`assign { cadd16_r, add16_r } = { cadd16_w, add16_w };`
388			`assign vadd16_r = (a_in[15] & b_in[15] & (~add16_w[15])) \| ((~a_in[15]) & (~b_in[15]) & add16_w[15]);`
389			`assign { cadc16_r, adc16_r } = { cadd16_w, add16_w };`
390			`assign vadc16_r = (a_in[15] & b_in[15] & (~add16_w[15])) \| ((~a_in[15]) & (~b_in[15]) & adc16_w[15]);`
391			`// SUB, SUBC`
392			`assign { csub16_r, sub16_r } = { csub16_w, sub16_w };`
393			`assign vsub16_r = (a_in[15] & b_in[15] & (~add16_w[15])) \| ((~a_in[15]) & b_in[15] & sub16_w[15]);`
394			`assign { csbc16_r, sbc16_r } = { csbc16_w, sbc16_w };`
395			`assign vsbc16_r = (a_in[15] & b_in[15] & (~sbc16_w[15])) \| ((~a_in[15]) & b_in[15] & sbc16_w[15]);`
396			`// COM`
397			`assign com16_r = com16_w;`
398			`assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;`
399			`assign vcom16_r = 1'b0;`
400			`// NEG`
401			`assign neg16_r = neg16_w;`
402			`assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);`
403			`assign cneg16_r = neg16_w[15] \| neg16_w[14] \| neg16_w[13] \| neg16_w[12] \| neg16_w[11] \| neg16_w[10] \| neg16_w[9] & neg16_w[8] \| neg16_w[7] \| neg16_w[6] \| neg16_w[5] \| neg16_w[4] \| neg16_w[3] \| neg16_w[2] \| neg16_w[1] \| neg16_w[0];`
404			`// ASR`
405			`assign asr16_r = asr16_w;`
406			`assign casr16_r = a_in[0];`
407			`assign vasr16_r = a_in[0] ^ asr16_w[15];`
408			`// SHR`
409			`assign shr16_r = shr16_w;`
410			`assign cshr16_r = a_in[0];`
411			`assign vshr16_r = a_in[0] ^ shr16_w[15];`
412			`// SHL`
413			`assign shl16_r = shl16_w;`
414			`assign cshl16_r = a_in[15];`
415			`assign vshl16_r = a_in[15] ^ shl16_w[15];`
416			`// ROR`
417			`assign ror16_r = ror16_w;`
418			`assign cror16_r = a_in[0];`
419			`assign vror16_r = a_in[0] ^ ror16_w[15];`
420			`// ROL`
421			`assign rol16_r = rol16_w;`
422			`assign crol16_r = a_in[15];`
423			`assign vrol16_r = a_in[15] ^ rol16_w[15];`
424			`// AND`
425			`assign and16_r = and16_w;`
426			`assign cand16_r = c_in;`
427			`assign vand16_r = 1'b0;`
428			`// OR`
429			`assign or16_r = or16_w;`
430			`// EOR`
431			`assign eor16_r = eor16_w;`
432	6	ale500
433			`wire [15:0] q16_mul;`
434
435			`mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], mul16_r);`
436			`assign cmul16_r = mul16_r[7];`
437	2	ale500
438	6	ale500	`reg c16, n16, v16, z16;`
439	2	ale500	`reg [15:0] q16;`
440
441			`always @(*)`
442			`begin`
443			`q16 = 16'h0;`
444			`c16 = c_in;`
445			`v16 = v_in;`
446			`case (opcode_in)`
447			`ADD:
448			`begin`
449			`q16 = add16_r;`
450			`c16 = cadd16_r;`
451			`v16 = vadd16_r;`
452			`end`
453			`ADC:
454			`begin`
455			`q16 = adc16_r;`
456			`c16 = cadc16_r;`
457			`v16 = vadc16_r;`
458			`end`
459			`CMP, `SUB: // for CMP no register result is written back
460			`begin`
461			`q16 = sub16_r;`
462			`c16 = csub16_r;`
463			`v16 = vsub16_r;`
464			`end`
465			`SBC:
466			`begin`
467			`q16 = sbc16_r;`
468			`c16 = csbc16_r;`
469			`v16 = vsbc16_r;`
470	6	ale500	`end`
471			`ifdef HD6309
472	2	ale500	`COM:
473			`begin`
474			`q16 = com16_r;`
475			`c16 = ccom16_r;`
476			`v16 = vcom16_r;`
477			`end`
478			`NEG:
479			`begin`
480			`q16 = neg16_r;`
481			`c16 = cneg16_r;`
482			`v16 = vneg16_r;`
483			`end`
484			`ASR:
485			`begin`
486			`q16 = asr16_r;`
487			`c16 = casr16_r;`
488			`v16 = vasr16_r;`
489			`end`
490			`LSR:
491			`begin`
492			`q16 = shr16_r;`
493			`c16 = cshr16_r;`
494			`v16 = vshr16_r;`
495			`end`
496			`LSL:
497			`begin`
498			`q16 = shl16_r;`
499			`c16 = cshl16_r;`
500			`v16 = vshl16_r;`
501			`end`
502			`ROR:
503			`begin`
504			`q16 = ror16_r;`
505			`c16 = cror16_r;`
506			`v16 = vror16_r;`
507			`end`
508			`ROL:
509			`begin`
510			`q16 = rol16_r;`
511			`c16 = crol16_r;`
512			`v16 = vrol16_r;`
513			`end`
514			`AND:
515			`begin`
516			`q16 = and16_r;`
517			`c16 = cand16_r;`
518			`v16 = vand16_r;`
519			`end`
520			`OR:
521			`begin`
522			`q16 = or16_r;`
523			`c16 = cand16_r;`
524			`v16 = vand16_r;`
525			`end`
526			`EOR:
527			`begin`
528			`q16 = eor16_r;`
529			`c16 = cand16_r;`
530			`v16 = vand16_r;`
531			`end`
532	6	ale500	`endif
533	2	ale500	`MUL:
534			`begin`
535			`q16 = mul16_r;`
536			`c16 = cmul16_r;`
537			`end`
538			`LD:
539			`begin`
540			`v16 = 0;`
541			`q16 = b_in[15:0];`
542			`end`
543			`ST:
544			`begin`
545			`q16 = a_in[15:0];`
546			`end`
547			`SEXT: // sign extend
548			`begin`
549			`q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };`
550	4	ale500	`end`
551			`LEA:
552			`begin`
553			`q16 = a_in[15:0];`
554			`end`
555	2	ale500	`endcase`
556			`end`
557
558			`reg [15:0] regq16;`
559			`reg reg_n_in, reg_z_in;`
560			`/* register before second mux */`
561	6	ale500	`always @(posedge clk_in)`
562	2	ale500	`begin`
563			`regq16 <= q16;`
564			`reg_n_in <= n_in;`
565			`reg_z_in <= z_in;`
566			`end`
567
568			`/* Negative & zero flags */`
569			`always @(*)`
570			`begin`
571	6	ale500	`n16 = q16[15];`
572			`z16 = q16 == 16'h0;`
573	2	ale500	`case (opcode_in)`
574			`ADD:
575			`begin`
576			`end`
577			`ADC:
578			`begin`
579			`end`
580			`CMP, `SUB: // for CMP no register result is written back
581			`begin`
582			`end`
583			`SBC:
584			`begin`
585			`end`
586			`COM:
587			`begin`
588			`end`
589			`NEG:
590			`begin`
591			`end`
592			`ASR:
593			`begin`
594			`end`
595			`LSR:
596			`begin`
597			`end`
598			`LSL:
599			`begin`
600			`end`
601			`ROR:
602			`begin`
603			`end`
604			`ROL:
605			`begin`
606			`end`
607			`AND:
608			`begin`
609			`end`
610			`OR:
611			`begin`
612			`end`
613			`EOR:
614			`begin`
615			`end`
616			`MUL:
617			`begin`
618			`n16 = reg_n_in;`
619			`end`
620			`LD:
621			`begin`
622			`end`
623			`ST:
624			`begin`
625			`end`
626			`SEXT: // sign extend
627			`begin`
628			`n16 = reg_n_in;`
629			`z16 = reg_z_in;`
630	4	ale500	`end`
631			`LEA: // only Z will be affected
632			`begin`
633			`n16 = reg_n_in;`
634	2	ale500	`end`
635			`endcase`
636			`end`
637
638
639			`always @(*)`
640			`begin`
641	6	ale500	`q_out = q16;`
642			`CCRo = { n16, z16, v16, c16 };`
643	2	ale500	`end`
644
645			`initial`
646			`begin`
647			`end`
648			`endmodule`
649
650	5	ale500	`module mul8x8(`
651	6	ale500	`input wire clk_in,`
652	5	ale500	`input wire [7:0] a,`
653			`input wire [7:0] b,`
654			`output wire [15:0] q`
655			`);`
656	6	ale500
657			`reg [15:0] pipe0, pipe1;//, pipe2, pipe3;`
658			`assign q = pipe1;`
659
660			`always @(posedge clk_in)`
661	5	ale500	`begin`
662	6	ale500	`pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0) +`
663			`(a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0);`
664			`pipe1 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) +`
665			`(a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe0;`
666			`/*`
667			`pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0);`
668			`pipe1 <= (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0) + pipe0;`
669			`pipe2 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) + pipe1;`
670			`pipe3 <= (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe2;`
671			`*/`
672			`end`
673	5	ale500
674			`endmodule`