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/*
 * (c) 2013 Alejandro Paz
 *
 *
 * An alu core
 *
 * ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL
 *
 *
 *
 */
`include "defs.v"
 
 
module alu(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        input wire sz_in, /* size, low 8 bit, high 16 bit */
        output reg [15:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire [7:0] ccr8_out, q8_out;
wire [15:0] q16_out;
wire [3:0] ccr16_out;
 
reg [15:0] ra_in, rb_in;
reg [4:0] rop_in;
alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);
alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_out, ccr16_out);
 
always @(posedge clk_in)
        begin
                ra_in <= a_in;
                rb_in <= b_in;
                rop_in <= opcode_in;
        end
 
always @(*)
        begin
                if (sz_in)
                        begin
                                q_out = q16_out;
                                CCRo = { CCR[7:4], ccr16_out };
                        end
                else
                        begin
                                q_out = { 8'h0, q8_out };
                                CCRo = ccr8_out;
                        end
        end
 
 
endmodule
/**
 * Simple 3 functions logic
 *
 */
module logic8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out /* ALU result */
        );
 
always @(*)
        begin
                case (opcode_in)
                        2'b00: q_out = b_in;
                        2'b01: q_out = a_in & b_in;
                        2'b10: q_out = a_in | b_in;
                        2'b11: q_out = a_in ^ b_in;
                endcase
        end
 
endmodule
 
/**
 * Simple ADD/SUB module
 *
 */
module arith8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire carry_in, /* condition code register */
        input wire half_c_in,
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output reg carry_out,
        output reg overflow_out,
        output reg half_c_out
        );
 
always @(*)
        begin
                case (opcode_in)
                        2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD
                        2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB
                        2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC
                        2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC
                endcase
        end
 
always @(*)
        begin
                case (opcode_in)
                        2'b00, 2'b10: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) | ((~a_in[7]) & (~b_in[7]) & q_out[7]);
                        2'b01, 2'b11: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) | ((~a_in[7]) & b_in[7] & q_out[7]);
                endcase
        end
 
always @(*)
        begin
                case (opcode_in)
                        2'b00, 2'b10: half_c_out = (a_in[3] & b_in[3] & (~q_out[3])) | ((~a_in[3]) & (~b_in[3]) & q_out[3]);
                        2'b01, 2'b11: half_c_out = half_c_in;
                endcase
        end
 
endmodule
 
/**
 * Simple ADD/SUB module
 *
 */
module arith16(
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire carry_in, /* condition code register */
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [15:0] q_out, /* ALU result */
        output reg carry_out,
        output reg overflow_out
        );
always @(*)
        begin
                case (opcode_in)
                        2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD
                        2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB
                        2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC
                        2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC
                endcase
        end
 
always @(*)
        begin
                case (opcode_in)
                        2'b00, 2'b10: overflow_out = (a_in[15] & b_in[15] & (~q_out[15])) | ((~a_in[15]) & (~b_in[15]) & q_out[7]);
                        2'b01, 2'b11: overflow_out = (a_in[15] & (~b_in[15]) & (~q_out[15])) | ((~a_in[15]) & b_in[15] & q_out[7]);
                endcase
        end
 
endmodule
 
module shift8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire carry_in, /* condition code register */
        input wire overflow_in, /* condition code register */
        input wire [2:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output wire carry_out,
        output reg overflow_out
        );
 
always @(*)
        begin
                q_out = { a_in[7], a_in[7:1] }; // ASR
                case (opcode_in)
                        3'b000: q_out = { 1'b0, a_in[7:1] }; // LSR
                        3'b001: q_out = { a_in[6:0], 1'b0 }; // LSL
                        3'b010: q_out = { carry_in, a_in[7:1] }; // ROR
                        3'b011: q_out = { a_in[6:0], carry_in }; // ROL
                        3'b100: q_out = { a_in[7], a_in[7:1] }; // ASR
                endcase
        end
 
always @(*)
        begin
                overflow_out = overflow_in;
                case (opcode_in)
                        3'b000: overflow_out = overflow_in; // LSR
                        3'b001: overflow_out = a_in[7] ^ a_in[6]; // LSL
                        3'b010: overflow_out = overflow_in; // ROR
                        3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL
                        3'b100: overflow_out = overflow_in; // ASR
                endcase
        end
 
assign carry_out = opcode_in[0] ? a_in[0]:a_in[7];
 
endmodule
 
 
module alu8(
        input wire clk_in,
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in, h_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
assign h_in = CCR[5]; /* halb-carry flag */
 
wire [7:0] com8_r, neg8_r;
wire [3:0] daa8l_r, daa8h_r;
wire daa_lnm9;
 
wire [7:0] com8_w, neg8_w;
 
wire ccom8_r, cneg8_r, cdaa8_r;
 
wire vcom8_r, vneg8_r;
 
assign com8_w = ~a_in[7:0];
assign neg8_w = 8'h0 - a_in[7:0];
                // COM
assign com8_r = com8_w;
assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;
assign vcom8_r = 1'b0;
                // NEG
assign neg8_r = neg8_w;
assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];
assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);
                // DAA
assign daa_lnm9 = (a_in[3:0] > 9);
assign daa8l_r = (daa_lnm9 | h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];
assign daa8h_r = ((a_in[7:4] > 9) || (c_in == 1'b1) || (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];
assign cdaa8_r = daa8h_r < a_in[7:4];
 
reg c8, h8, n8, v8, z8;
reg [7:0] q8;
 
wire [7:0] logic_q, arith_q, shift_q;
wire arith_c, arith_v, arith_h;
wire shift_c, shift_v;
 
logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);
arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);
shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);
 
always @(*)
        begin
                q8 = 8'h0;
                c8 = c_in;
                h8 = h_in;
                v8 = v_in;
                case (opcode_in)
                        `ADD, `ADC, `SUB, `SBC:
                                begin
                                        q8 = arith_q;
                                        c8 = arith_c;
                                        v8 = arith_v;
                                        h8 = arith_h;
                                end
                        `COM:
                                begin
                                        q8 = com8_r;
                                        c8 = com8_r;
                                        v8 = vcom8_r;
                                end
                        `NEG:
                                begin
                                        q8 = neg8_r;
                                        c8 = cneg8_r;
                                        v8 = vneg8_r;
                                end
                        `LSR, `LSL, `ROL, `ROR,`ASR:
                                begin
                                        q8 = shift_q;
                                        c8 = shift_c;
                                        v8 = shift_v;
                                end
                        `AND, `OR, `EOR, `LD:
                                begin
                                        q8 = logic_q;
                                        v8 = 1'b0;
                                        end
                        `DAA:
                                begin // V is undefined, so we don't touch it
                                        q8 = { daa8h_r, daa8l_r };
                                        c8 = cdaa8_r;
                                end
                        `ST:
                                begin
                                        q8 = a_in[7:0];
                                end
                endcase
        end
 
reg [7:0] regq8;
/* register before second mux */
always @(posedge clk_in)
        begin
                regq8 <= q8;
        end
 
always @(*)
        begin
                q_out[7:0] = q8; //regq8;
                case (opcode_in)
                        `ORCC:
                                CCRo = CCR | b_in[7:0];
                        `ANDCC:
                                CCRo = CCR & b_in[7:0];
                        default:
                                CCRo = { CCR[7:6], CCR[5], h8, q8[7], (q8 == 8'h0), v8, c8 };
                endcase
        end
 
initial
        begin
        end
endmodule
 
/* ALU for 16 bit operations */
module alu16(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        output reg [15:0] q_out, /* ALU result */
        output reg [3:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
 
`ifdef HD6309
wire [15:0] com16_r, neg16_r;
wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r;
 
wire [15:0] com16_w, neg16_w;
wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;
 
wire ccom16_r, cneg16_r;
wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r;
 
wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;
wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;
 
assign com16_w = ~a_in[15:0];
assign neg16_w = 16'h0 - a_in[15:0];
assign asr16_w = { a_in[15], a_in[15:1] };
assign shr16_w = { 1'b0, a_in[15:1] };
assign shl16_w = { a_in[14:0], 1'b0 };
assign ror16_w = { c_in, a_in[15:1] };
assign rol16_w = { a_in[14:0], c_in };
assign and16_w = a_in[15:0] & b_in[15:0];
assign or16_w = a_in[15:0] | b_in[15:0];
assign eor16_w = a_in[15:0] ^ b_in[15:0];
 
// COM
assign com16_r = com16_w;
assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;
assign vcom16_r = 1'b0;
                // NEG
assign neg16_r = neg16_w;
assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);
assign cneg16_r = neg16_w[15] | neg16_w[14] | neg16_w[13] | neg16_w[12] | neg16_w[11] | neg16_w[10] | neg16_w[9] & neg16_w[8] | neg16_w[7] | neg16_w[6] | neg16_w[5] | neg16_w[4] | neg16_w[3] | neg16_w[2] | neg16_w[1] | neg16_w[0];
                // ASR
assign asr16_r = asr16_w;
assign casr16_r = a_in[0];
assign vasr16_r = a_in[0] ^ asr16_w[15];
                // SHR
assign shr16_r = shr16_w;
assign cshr16_r = a_in[0];
assign vshr16_r = a_in[0] ^ shr16_w[15];
                // SHL
assign shl16_r = shl16_w;
assign cshl16_r = a_in[15];
assign vshl16_r = a_in[15] ^ shl16_w[15];
                // ROR
assign ror16_r = ror16_w;
assign cror16_r = a_in[0];
assign vror16_r = a_in[0] ^ ror16_w[15];
                // ROL
assign rol16_r = rol16_w;
assign crol16_r = a_in[15];
assign vrol16_r = a_in[15] ^ rol16_w[15];
                // AND
assign and16_r = and16_w;
assign cand16_r = c_in;
assign vand16_r = 1'b0;
                // OR
assign or16_r = or16_w;
                // EOR
assign eor16_r = eor16_w;
`endif
 
wire [15:0] q16_mul;
 
mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);
 
reg c16, n16, v16, z16;
reg [15:0] q16;
 
wire [15:0] arith_q;
wire arith_c, arith_v, arith_h;
 
arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);
 
always @(*)
        begin
                q16 = 16'h0;
                c16 = c_in;
                v16 = v_in;
                case (opcode_in)
                        `ADD, `ADC, `SUB, `SBC:
                                begin
                                        q16 = arith_q;
                                        c16 = arith_c;
                                        v16 = arith_v;
                                end
`ifdef HD6309
                        `COM:
                                begin
                                        q16 = com16_r;
                                        c16 = ccom16_r;
                                        v16 = vcom16_r;
                                end
                        `NEG:
                                begin
                                        q16 = neg16_r;
                                        c16 = cneg16_r;
                                        v16 = vneg16_r;
                                end
                        `ASR:
                                begin
                                        q16 = asr16_r;
                                        c16 = casr16_r;
                                        v16 = vasr16_r;
                                end
                        `LSR:
                                begin
                                        q16 = shr16_r;
                                        c16 = cshr16_r;
                                        v16 = vshr16_r;
                                end
                        `LSL:
                                begin
                                        q16 = shl16_r;
                                        c16 = cshl16_r;
                                        v16 = vshl16_r;
                                end
                        `ROR:
                                begin
                                        q16 = ror16_r;
                                        c16 = cror16_r;
                                        v16 = vror16_r;
                                end
                        `ROL:
                                begin
                                        q16 = rol16_r;
                                        c16 = crol16_r;
                                        v16 = vrol16_r;
                                end
                        `AND:
                                begin
                                        q16 = and16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                        end
                        `OR:
                                begin
                                        q16 = or16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
                        `EOR:
                                begin
                                        q16 = eor16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
`endif
                        `MUL:
                                begin
                                        q16 = q16_mul;
                                        c16 = q16_mul[7];
                                end
                        `LD:
                                begin
                                        v16 = 0;
                                        q16 = b_in[15:0];
                                end
                        `ST:
                                begin
                                        q16 = a_in[15:0];
                                end
                        `SEXT: // sign extend
                                begin
                                        q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };
                                end
                        `LEA:
                                begin
                                        q16 = a_in[15:0];
                                end
                endcase
        end
 
reg [15:0] regq16;
reg reg_n_in, reg_z_in;
/* register before second mux */
always @(posedge clk_in)
        begin
                regq16 <= q16;
                reg_n_in <= n_in;
                reg_z_in <= z_in;
        end
 
/* Negative & zero flags */
always @(*)
        begin
                n16 = q16[15];
                z16 = q16 == 16'h0;
                case (opcode_in)
                        `ADD:
                                begin
                                end
                        `ADC:
                                begin
                                end
                        `SUB: // for CMP no register result is written back
                                begin
                                end
                        `SBC:
                                begin
                                end
                        `COM:
                                begin
                                end
                        `NEG:
                                begin
                                end
                        `ASR:
                                begin
                                end
                        `LSR:
                                begin
                                end
                        `LSL:
                                begin
                                end
                        `ROR:
                                begin
                                end
                        `ROL:
                                begin
                                end
                        `AND:
                                begin
                                end
                        `OR:
                                begin
                                end
                        `EOR:
                                begin
                                end
                        `MUL:
                                begin
                                        n16 = reg_n_in;
                                end
                        `LD:
                                begin
                                end
                        `ST:
                                begin
                                end
                        `SEXT: // sign extend
                                begin
                                        n16 = reg_n_in;
                                        z16 = reg_z_in;
                                end
                        `LEA: // only Z will be affected
                                begin
                                        n16 = reg_n_in;
                                end
                endcase
        end
 
 
always @(*)
        begin
                q_out = q16;
                CCRo = { n16, z16, v16, c16 };
        end
 
endmodule
 
module mul8x8(
        input wire clk_in,
        input wire [7:0] a,
        input wire [7:0] b,
        output wire [15:0] q
        );
 
reg [15:0] pipe0, pipe1;//, pipe2, pipe3;
assign q = pipe1;
 
always @(posedge clk_in)
        begin
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0) +
                         (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0);
                pipe1 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) +
                         (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe0;
                /*
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0);
                pipe1 <= (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0) + pipe0;
                pipe2 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) + pipe1;
                pipe3 <= (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe2;
                */
        end
 
endmodule

Line No.	Rev	Author	Line
1	4	ale500	`/*`
2			`* (c) 2013 Alejandro Paz`
3			`*`
4			`*`
5			`* An alu core`
6			`*`
7			`* ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL`
8			`*`
9			`*`
10			`*`
11			`*/`
12			`include "defs.v"
13	6	ale500
14
15			`module alu(`
16			`input wire clk_in,`
17	4	ale500	`input wire [15:0] a_in,`
18			`input wire [15:0] b_in,`
19			`input wire [7:0] CCR, /* condition code register */`
20			`input wire [4:0] opcode_in, /* ALU opcode */`
21			`input wire sz_in, /* size, low 8 bit, high 16 bit */`
22			`output reg [15:0] q_out, /* ALU result */`
23			`output reg [7:0] CCRo`
24			`);`
25	2	ale500
26	6	ale500	`wire [7:0] ccr8_out, q8_out;`
27			`wire [15:0] q16_out;`
28			`wire [3:0] ccr16_out;`
29
30			`reg [15:0] ra_in, rb_in;`
31	9	ale500	`reg [4:0] rop_in;`
32			`alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);`
33			`alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_out, ccr16_out);`
34	6	ale500
35			`always @(posedge clk_in)`
36			`begin`
37			`ra_in <= a_in;`
38			`rb_in <= b_in;`
39	9	ale500	`rop_in <= opcode_in;`
40	6	ale500	`end`
41
42			`always @(*)`
43			`begin`
44			`if (sz_in)`
45			`begin`
46			`q_out = q16_out;`
47			`CCRo = { CCR[7:4], ccr16_out };`
48			`end`
49			`else`
50			`begin`
51			`q_out = { 8'h0, q8_out };`
52			`CCRo = ccr8_out;`
53			`end`
54			`end`
55	9	ale500
56	6	ale500
57			`endmodule`
58	9	ale500	`/**`
59			`* Simple 3 functions logic`
60			`*`
61			`*/`
62			`module logic8(`
63			`input wire [7:0] a_in,`
64			`input wire [7:0] b_in,`
65			`input wire [1:0] opcode_in, /* ALU opcode */`
66			`output reg [7:0] q_out /* ALU result */`
67			`);`
68	6	ale500
69	9	ale500	`always @(*)`
70			`begin`
71			`case (opcode_in)`
72			`2'b00: q_out = b_in;`
73			`2'b01: q_out = a_in & b_in;`
74			`2'b10: q_out = a_in \| b_in;`
75			`2'b11: q_out = a_in ^ b_in;`
76			`endcase`
77			`end`
78
79			`endmodule`
80
81			`/**`
82			`* Simple ADD/SUB module`
83			`*`
84			`*/`
85			`module arith8(`
86			`input wire [7:0] a_in,`
87			`input wire [7:0] b_in,`
88			`input wire carry_in, /* condition code register */`
89			`input wire half_c_in,`
90			`input wire [1:0] opcode_in, /* ALU opcode */`
91			`output reg [7:0] q_out, /* ALU result */`
92			`output reg carry_out,`
93			`output reg overflow_out,`
94			`output reg half_c_out`
95			`);`
96
97			`always @(*)`
98			`begin`
99			`case (opcode_in)`
100			`2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD`
101			`2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB`
102			`2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC`
103			`2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC`
104			`endcase`
105			`end`
106
107			`always @(*)`
108			`begin`
109			`case (opcode_in)`
110			`2'b00, 2'b10: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) \| ((~a_in[7]) & (~b_in[7]) & q_out[7]);`
111			`2'b01, 2'b11: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) \| ((~a_in[7]) & b_in[7] & q_out[7]);`
112			`endcase`
113			`end`
114
115			`always @(*)`
116			`begin`
117			`case (opcode_in)`
118			`2'b00, 2'b10: half_c_out = (a_in[3] & b_in[3] & (~q_out[3])) \| ((~a_in[3]) & (~b_in[3]) & q_out[3]);`
119			`2'b01, 2'b11: half_c_out = half_c_in;`
120			`endcase`
121			`end`
122
123			`endmodule`
124
125			`/**`
126			`* Simple ADD/SUB module`
127			`*`
128			`*/`
129			`module arith16(`
130			`input wire [15:0] a_in,`
131			`input wire [15:0] b_in,`
132			`input wire carry_in, /* condition code register */`
133			`input wire [1:0] opcode_in, /* ALU opcode */`
134			`output reg [15:0] q_out, /* ALU result */`
135			`output reg carry_out,`
136			`output reg overflow_out`
137			`);`
138			`always @(*)`
139			`begin`
140			`case (opcode_in)`
141			`2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD`
142			`2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB`
143			`2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC`
144			`2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC`
145			`endcase`
146			`end`
147
148			`always @(*)`
149			`begin`
150			`case (opcode_in)`
151			`2'b00, 2'b10: overflow_out = (a_in[15] & b_in[15] & (~q_out[15])) \| ((~a_in[15]) & (~b_in[15]) & q_out[7]);`
152			`2'b01, 2'b11: overflow_out = (a_in[15] & (~b_in[15]) & (~q_out[15])) \| ((~a_in[15]) & b_in[15] & q_out[7]);`
153			`endcase`
154			`end`
155
156			`endmodule`
157
158			`module shift8(`
159			`input wire [7:0] a_in,`
160			`input wire [7:0] b_in,`
161			`input wire carry_in, /* condition code register */`
162			`input wire overflow_in, /* condition code register */`
163			`input wire [2:0] opcode_in, /* ALU opcode */`
164			`output reg [7:0] q_out, /* ALU result */`
165			`output wire carry_out,`
166			`output reg overflow_out`
167			`);`
168
169			`always @(*)`
170			`begin`
171			`q_out = { a_in[7], a_in[7:1] }; // ASR`
172			`case (opcode_in)`
173			`3'b000: q_out = { 1'b0, a_in[7:1] }; // LSR`
174			`3'b001: q_out = { a_in[6:0], 1'b0 }; // LSL`
175			`3'b010: q_out = { carry_in, a_in[7:1] }; // ROR`
176			`3'b011: q_out = { a_in[6:0], carry_in }; // ROL`
177			`3'b100: q_out = { a_in[7], a_in[7:1] }; // ASR`
178			`endcase`
179			`end`
180
181			`always @(*)`
182			`begin`
183			`overflow_out = overflow_in;`
184			`case (opcode_in)`
185			`3'b000: overflow_out = overflow_in; // LSR`
186			`3'b001: overflow_out = a_in[7] ^ a_in[6]; // LSL`
187			`3'b010: overflow_out = overflow_in; // ROR`
188			`3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL`
189			`3'b100: overflow_out = overflow_in; // ASR`
190			`endcase`
191			`end`
192
193			`assign carry_out = opcode_in[0] ? a_in[0]:a_in[7];`
194
195			`endmodule`
196
197
198	6	ale500	`module alu8(`
199			`input wire clk_in,`
200	9	ale500	`input wire [7:0] a_in,`
201			`input wire [7:0] b_in,`
202	6	ale500	`input wire [7:0] CCR, /* condition code register */`
203			`input wire [4:0] opcode_in, /* ALU opcode */`
204			`output reg [7:0] q_out, /* ALU result */`
205			`output reg [7:0] CCRo`
206			`);`
207
208			`wire c_in, n_in, v_in, z_in, h_in;`
209			`assign c_in = CCR[0]; /* carry flag */`
210			`assign n_in = CCR[3]; /* neg flag */`
211			`assign v_in = CCR[1]; /* overflow flag */`
212			`assign z_in = CCR[2]; /* zero flag */`
213			`assign h_in = CCR[5]; /* halb-carry flag */`
214
215	9	ale500	`wire [7:0] com8_r, neg8_r;`
216	6	ale500	`wire [3:0] daa8l_r, daa8h_r;`
217			`wire daa_lnm9;`
218
219	9	ale500	`wire [7:0] com8_w, neg8_w;`
220	6	ale500
221	9	ale500	`wire ccom8_r, cneg8_r, cdaa8_r;`
222	6	ale500
223	9	ale500	`wire vcom8_r, vneg8_r;`
224	6	ale500
225			`assign com8_w = ~a_in[7:0];`
226			`assign neg8_w = 8'h0 - a_in[7:0];`
227			`// COM`
228			`assign com8_r = com8_w;`
229			`assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;`
230			`assign vcom8_r = 1'b0;`
231			`// NEG`
232			`assign neg8_r = neg8_w;`
233			`assign cneg8_r = neg8_w[7] \| neg8_w[6] \| neg8_w[5] \| neg8_w[4] \| neg8_w[3] \| neg8_w[2] \| neg8_w[1] \| neg8_w[0];`
234			`assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);`
235			`// DAA`
236			`assign daa_lnm9 = (a_in[3:0] > 9);`
237			`assign daa8l_r = (daa_lnm9 \| h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];`
238			`assign daa8h_r = ((a_in[7:4] > 9) \|\| (c_in == 1'b1) \|\| (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];`
239			`assign cdaa8_r = daa8h_r < a_in[7:4];`
240
241			`reg c8, h8, n8, v8, z8;`
242			`reg [7:0] q8;`
243	9	ale500
244			`wire [7:0] logic_q, arith_q, shift_q;`
245			`wire arith_c, arith_v, arith_h;`
246			`wire shift_c, shift_v;`
247
248			`logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);`
249			`arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);`
250			`shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);`
251
252	6	ale500	`always @(*)`
253			`begin`
254			`q8 = 8'h0;`
255			`c8 = c_in;`
256			`h8 = h_in;`
257			`v8 = v_in;`
258			`case (opcode_in)`
259	9	ale500	`ADD, `ADC, `SUB, `SBC:
260	6	ale500	`begin`
261	9	ale500	`q8 = arith_q;`
262			`c8 = arith_c;`
263			`v8 = arith_v;`
264			`h8 = arith_h;`
265	6	ale500	`end`
266			`COM:
267			`begin`
268			`q8 = com8_r;`
269			`c8 = com8_r;`
270			`v8 = vcom8_r;`
271			`end`
272			`NEG:
273			`begin`
274			`q8 = neg8_r;`
275			`c8 = cneg8_r;`
276			`v8 = vneg8_r;`
277			`end`
278	9	ale500	`LSR, `LSL, `ROL, `ROR,`ASR:
279	6	ale500	`begin`
280	9	ale500	`q8 = shift_q;`
281			`c8 = shift_c;`
282			`v8 = shift_v;`
283	6	ale500	`end`
284	9	ale500	`AND, `OR, `EOR, `LD:
285	6	ale500	`begin`
286	9	ale500	`q8 = logic_q;`
287			`v8 = 1'b0;`
288	6	ale500	`end`
289			`DAA:
290			`begin // V is undefined, so we don't touch it`
291			`q8 = { daa8h_r, daa8l_r };`
292			`c8 = cdaa8_r;`
293			`end`
294			`ST:
295			`begin`
296			`q8 = a_in[7:0];`
297			`end`
298			`endcase`
299			`end`
300
301			`reg [7:0] regq8;`
302			`/* register before second mux */`
303			`always @(posedge clk_in)`
304			`begin`
305			`regq8 <= q8;`
306			`end`
307
308			`always @(*)`
309			`begin`
310			`q_out[7:0] = q8; //regq8;`
311			`case (opcode_in)`
312			`ORCC:
313			`CCRo = CCR \| b_in[7:0];`
314			`ANDCC:
315			`CCRo = CCR & b_in[7:0];`
316			`default:`
317			`CCRo = { CCR[7:6], CCR[5], h8, q8[7], (q8 == 8'h0), v8, c8 };`
318			`endcase`
319			`end`
320
321			`initial`
322			`begin`
323			`end`
324			`endmodule`
325
326			`/* ALU for 16 bit operations */`
327			`module alu16(`
328			`input wire clk_in,`
329			`input wire [15:0] a_in,`
330			`input wire [15:0] b_in,`
331			`input wire [7:0] CCR, /* condition code register */`
332			`input wire [4:0] opcode_in, /* ALU opcode */`
333			`output reg [15:0] q_out, /* ALU result */`
334			`output reg [3:0] CCRo`
335			`);`
336
337			`wire c_in, n_in, v_in, z_in;`
338	2	ale500	`assign c_in = CCR[0]; /* carry flag */`
339			`assign n_in = CCR[3]; /* neg flag */`
340			`assign v_in = CCR[1]; /* overflow flag */`
341			`assign z_in = CCR[2]; /* zero flag */`
342
343	9	ale500	`ifdef HD6309
344			`wire [15:0] com16_r, neg16_r;`
345			`wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r;`
346	2	ale500
347	9	ale500	`wire [15:0] com16_w, neg16_w;`
348	6	ale500	`wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;`
349	2	ale500
350	9	ale500	`wire ccom16_r, cneg16_r;`
351			`wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r;`
352	2	ale500
353			`wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;`
354			`wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;`
355
356			`assign com16_w = ~a_in[15:0];`
357			`assign neg16_w = 16'h0 - a_in[15:0];`
358			`assign asr16_w = { a_in[15], a_in[15:1] };`
359			`assign shr16_w = { 1'b0, a_in[15:1] };`
360			`assign shl16_w = { a_in[14:0], 1'b0 };`
361			`assign ror16_w = { c_in, a_in[15:1] };`
362			`assign rol16_w = { a_in[14:0], c_in };`
363			`assign and16_w = a_in[15:0] & b_in[15:0];`
364			`assign or16_w = a_in[15:0] \| b_in[15:0];`
365			`assign eor16_w = a_in[15:0] ^ b_in[15:0];`
366
367	9	ale500	`// COM`
368	2	ale500	`assign com16_r = com16_w;`
369			`assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;`
370			`assign vcom16_r = 1'b0;`
371			`// NEG`
372			`assign neg16_r = neg16_w;`
373			`assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);`
374			`assign cneg16_r = neg16_w[15] \| neg16_w[14] \| neg16_w[13] \| neg16_w[12] \| neg16_w[11] \| neg16_w[10] \| neg16_w[9] & neg16_w[8] \| neg16_w[7] \| neg16_w[6] \| neg16_w[5] \| neg16_w[4] \| neg16_w[3] \| neg16_w[2] \| neg16_w[1] \| neg16_w[0];`
375			`// ASR`
376			`assign asr16_r = asr16_w;`
377			`assign casr16_r = a_in[0];`
378			`assign vasr16_r = a_in[0] ^ asr16_w[15];`
379			`// SHR`
380			`assign shr16_r = shr16_w;`
381			`assign cshr16_r = a_in[0];`
382			`assign vshr16_r = a_in[0] ^ shr16_w[15];`
383			`// SHL`
384			`assign shl16_r = shl16_w;`
385			`assign cshl16_r = a_in[15];`
386			`assign vshl16_r = a_in[15] ^ shl16_w[15];`
387			`// ROR`
388			`assign ror16_r = ror16_w;`
389			`assign cror16_r = a_in[0];`
390			`assign vror16_r = a_in[0] ^ ror16_w[15];`
391			`// ROL`
392			`assign rol16_r = rol16_w;`
393			`assign crol16_r = a_in[15];`
394			`assign vrol16_r = a_in[15] ^ rol16_w[15];`
395			`// AND`
396			`assign and16_r = and16_w;`
397			`assign cand16_r = c_in;`
398			`assign vand16_r = 1'b0;`
399			`// OR`
400			`assign or16_r = or16_w;`
401			`// EOR`
402			`assign eor16_r = eor16_w;`
403	9	ale500	`endif
404	6	ale500
405			`wire [15:0] q16_mul;`
406
407	9	ale500	`mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);`
408	2	ale500
409	6	ale500	`reg c16, n16, v16, z16;`
410	2	ale500	`reg [15:0] q16;`
411
412	9	ale500	`wire [15:0] arith_q;`
413			`wire arith_c, arith_v, arith_h;`
414
415			`arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);`
416
417	2	ale500	`always @(*)`
418			`begin`
419			`q16 = 16'h0;`
420			`c16 = c_in;`
421			`v16 = v_in;`
422			`case (opcode_in)`
423	9	ale500	`ADD, `ADC, `SUB, `SBC:
424	2	ale500	`begin`
425	9	ale500	`q16 = arith_q;`
426			`c16 = arith_c;`
427			`v16 = arith_v;`
428	2	ale500	`end`
429	6	ale500	`ifdef HD6309
430	2	ale500	`COM:
431			`begin`
432			`q16 = com16_r;`
433			`c16 = ccom16_r;`
434			`v16 = vcom16_r;`
435			`end`
436			`NEG:
437			`begin`
438			`q16 = neg16_r;`
439			`c16 = cneg16_r;`
440			`v16 = vneg16_r;`
441			`end`
442			`ASR:
443			`begin`
444			`q16 = asr16_r;`
445			`c16 = casr16_r;`
446			`v16 = vasr16_r;`
447			`end`
448			`LSR:
449			`begin`
450			`q16 = shr16_r;`
451			`c16 = cshr16_r;`
452			`v16 = vshr16_r;`
453			`end`
454			`LSL:
455			`begin`
456			`q16 = shl16_r;`
457			`c16 = cshl16_r;`
458			`v16 = vshl16_r;`
459			`end`
460			`ROR:
461			`begin`
462			`q16 = ror16_r;`
463			`c16 = cror16_r;`
464			`v16 = vror16_r;`
465			`end`
466			`ROL:
467			`begin`
468			`q16 = rol16_r;`
469			`c16 = crol16_r;`
470			`v16 = vrol16_r;`
471			`end`
472			`AND:
473			`begin`
474			`q16 = and16_r;`
475			`c16 = cand16_r;`
476			`v16 = vand16_r;`
477			`end`
478			`OR:
479			`begin`
480			`q16 = or16_r;`
481			`c16 = cand16_r;`
482			`v16 = vand16_r;`
483			`end`
484			`EOR:
485			`begin`
486			`q16 = eor16_r;`
487			`c16 = cand16_r;`
488			`v16 = vand16_r;`
489			`end`
490	6	ale500	`endif
491	2	ale500	`MUL:
492			`begin`
493	9	ale500	`q16 = q16_mul;`
494			`c16 = q16_mul[7];`
495	2	ale500	`end`
496			`LD:
497			`begin`
498			`v16 = 0;`
499			`q16 = b_in[15:0];`
500			`end`

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