URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [decoders.v] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log


 
/*
 * Signals which registers have to be read/written for the current opcode
 *
 *
 *
 */
`include "defs.v"
module decode_regs(
        input wire cpu_clk,
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        output reg [3:0] path_left_addr_o,
        output reg [3:0] path_right_addr_o,
        output reg [3:0] dest_reg_o,
        output wire write_dest,
        output wire source_size,
        output wire result_size
        );
reg [3:0] path_left_addr, path_right_addr, dest_reg;
// for registers, memory writes are handled differently
assign write_dest = (dest_reg != `RN_INV);
assign source_size = (path_left_addr < `RN_ACCA);
assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
always @(opcode, postbyte0, page2_valid, page3_valid)
        begin
                path_left_addr = `RN_INV;
                path_right_addr = `RN_INV;
                dest_reg = `RN_INV;
                if (page2_valid)
                        begin
                                casex(postbyte0)
                                        8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
                                        8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
                                        8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
                                        8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
                                endcase
                                casex (postbyte0) // right arm
                                        8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
                                        8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
                                        8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
                                        8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
                                        8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
                                        8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
                                endcase
                                casex(postbyte0) // dest
                                        8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy
                                        8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
                                        8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
                                        8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
                                        8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
                                endcase
                        end
                if (page3_valid)
                        begin
                                casex(postbyte0)
                                        8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
                                endcase
                                casex (postbyte0) // right arm
                                        8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
                                        8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
                                        8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
                                endcase
                                casex(postbyte0) // dest
                                        8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
                                endcase
                        end
                // destination
                casex(opcode)
                        8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg
                        8'h30: dest_reg = `RN_IX;
                        8'h31: dest_reg = `RN_IY;
                        8'h32: dest_reg = `RN_S;
                        8'h33: dest_reg = `RN_U;
                        8'h39: dest_reg = `RN_PC; // rts
                        8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
                        8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
                        8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
                        8'h0x, 8'h7x: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
                        8'h6x:
                                case (opcode[3:0])
                                        4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
                                        default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
                                endcase
                        8'h8x, 8'h9x, 8'hax, 8'hbx:
                                case (opcode[3:0]) // default A->A
                                        4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
                                        4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
                                        4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
                                        4'hc: path_left_addr = `RN_IX; // cmpx
                                        4'hd: begin end // nothing active, jsr
                                        4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
                                        4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
                                        default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
                                endcase
                        8'hcx, 8'hdx, 8'hex, 8'hfx:
                                case (opcode[3:0])
                                        4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
                                        4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
                                        4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
                                        4'hd: begin path_left_addr = `RN_ACCD; end // LDD
                                        4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU
                                        4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
                                        default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
                                endcase
                endcase
                casex (opcode) // right arm
                        // 8x and Cx
                        8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb
                        8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
                        8'b1x00_010x, 8'b1x00_0110,     8'b1x00_10xx: path_right_addr = `RN_IMM8;
                        // 9, A, B, D, E, F
                        8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
                        8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx
                        8'b1x01_010x, 8'b1x01_0110,     8'b1x01_10xx: path_right_addr = `RN_MEM8;
                        8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
                        8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
                        8'b1x1x_010x, 8'b1x1x_0110,     8'b1x1x_10xx: path_right_addr = `RN_MEM8;
                endcase
        end
always @(posedge cpu_clk)
        begin
                path_right_addr_o <= path_right_addr;
                path_left_addr_o <= path_left_addr;
                dest_reg_o <= dest_reg;
        end
endmodule
 
/* Decodes module and addressing mode for page 1 opcodes */
module decode_op(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        output reg [2:0] mode,
        output reg [2:0] optype,
        output reg use_s
        );
 
wire [3:0] oplo;
reg size;
assign oplo = opcode[3:0];
 
always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
        begin
                //dsize = `DSZ_8; // data operand size
                //msize = `MSZ_8; // memory operand size
                optype = `OP_NONE;
                use_s = 1;
                mode = `NONE;
                size = 0;
                // Addressing mode
                casex(opcode)
                        8'h0x: begin mode = `DIRECT; end
                        8'h12, 8'h13, 8'h19: mode = `INHERENT;
                        8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
                        8'h16: mode = `REL16;
                        8'h17: begin mode = `REL16; optype = `OP_JSR; end
                        8'h1a, 8'h1c, 8'h1d, 8'h1e, 8'h1f: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
 
                        8'h2x: mode = `REL8;
                        8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED;  optype = `OP_LEA; end
                        8'h34: begin optype = `OP_PUSH; mode = `NONE; end
                        8'h35: begin optype = `OP_PULL; mode = `NONE; end
                        8'h36: begin optype = `OP_PUSH; mode = `NONE; use_s = 0; end
                        8'h37: begin optype = `OP_PULL; mode = `NONE; use_s = 0; end
                        8'h38, 8'h3e: mode = `NONE;
                        // don't change to inh because SEQ_MEM_READ_x would not use register S as address
                        8'h39, 8'h3b: begin  mode = `NONE; optype = `OP_RTS; end
                        8'h3a, 8'h3c, 8'h3d, 8'h3f: mode = `INHERENT;
 
                        8'h4x: begin mode = `INHERENT; end
                        8'h5x: begin mode = `INHERENT; end
                        8'h6x: begin mode = `INDEXED; end
                        8'h7x: begin mode = `EXTENDED; end
                        8'h8x:
                                begin
                                        case (oplo)
                                                4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
                                                4'hd: mode = `REL8; // bsr
                                                default: mode = `IMMEDIATE;
                                        endcase
                                end
                        8'hcx:
                                begin
                                        case (oplo)
                                                4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
                                                default: mode = `IMMEDIATE;
                                        endcase
                                end
                        8'h9x, 8'hdx: begin mode = `DIRECT; end
                        8'hax, 8'hex: begin mode = `INDEXED; end
                        8'hbx, 8'hfx: begin mode = `EXTENDED; end
                endcase
                // Opcode type
                casex(opcode)
                        8'b1xxx0110: optype = `OP_LD;
                        8'b1xxx0111: optype = `OP_ST;
                        8'b11xx1100: optype = `OP_LD; // LDD
                        8'b10xx1101: begin optype = `OP_JSR; end// bsr & jsr
                        8'b1xxx1110: optype = `OP_LD; // LDX, LDU
                        8'b1xxx1111, 8'b11xx1101: optype = `OP_ST;
                endcase
                if (page2_valid == 1'b1)
                        begin
                                casex(postbyte0)
                                        8'h1x: mode = `REL16;
                                        8'h2f: mode = `INHERENT;
                                        8'h83: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
                                        8'h8c: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
                                        8'h8e: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
                                        //8'h9f, 8'haf, 8'hbf: begin  mem16 = 1; size = 1; end
                                        8'hce: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
                                        //8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
                                endcase
                                casex( postbyte0)
                                        8'h9x, 8'hdx: mode = `DIRECT;
                                        8'hax, 8'hex: mode = `INDEXED;
                                        8'hbx, 8'hfx: mode = `EXTENDED;
                                endcase
                                casex( postbyte0)
                                        8'b1xxx1110: optype = `OP_LD; // LDY, LDS
                                        8'b1xxx1111, 8'b1xxx1101: optype = `OP_ST; // STY, STS
                                endcase
                        end
                if (page3_valid == 1'b1)
                        begin
                                casex(postbyte0)
                                        8'h2f: mode = `INHERENT;
                                        8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
                                        //8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
                                        8'h8c: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
                                        8'h8e: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
                                        //8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
                                        8'hce: begin mode = `IMMEDIATE; size = 1; end
                                        //8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
                                        //8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
                                endcase
                                casex( postbyte0)
                                        8'h9x, 8'hdx: mode = `DIRECT;
                                        8'hax, 8'hex: mode = `INDEXED;
                                        8'hbx, 8'hfx: mode = `EXTENDED;
                                endcase
                        end
        end
 
endmodule
 
/* Decodes the Effective Address postbyte
   to recover size of offset to load and post-incr/pre-decr info
 */
module decode_ea(
        input wire [7:0] eapostbyte,
        output reg noofs,
        output reg ofs8, // needs an 8 bit offset
        output reg ofs16, // needs an 16 bit offset
        output reg write_post, // needs to write back a predecr or post incr
        output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address
        );
 
assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;
always @(*)
        begin
                noofs = 0;
                ofs8 = 0;
                ofs16 = 0;
                write_post = 0;
                casex (eapostbyte)
                        8'b0xxxxxxx, 8'b1xx00100: noofs = 1;
                        8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;
                        8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;
                        8'b1xx11111: ofs16 = 1; // extended indirect
                        8'b1xxx00xx: write_post = 1;
                endcase
        end
endmodule
 
module decode_alu(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode
        input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode
        output reg [4:0] alu_opcode,
        output reg [1:0] dec_alu_right_path_mod,
        output wire dest_flags
        );
 
assign dest_flags = alu_opcode != `NOP;
always @(*)
        begin
                alu_opcode = `NOP;
                dec_alu_right_path_mod = `MOD_DEFAULT;
                casex (opcode)
                        8'b1xxx_0000: alu_opcode = `SUB;
                        8'b1xxx_0001: alu_opcode = `SUB; // CMP
                        8'b1xxx_0010: alu_opcode = `SBC;
                        8'b10xx_0011: alu_opcode = `SUB;
                        8'b11xx_0011: alu_opcode = `ADD;
                        8'b1xxx_0100: alu_opcode = `AND;
                        8'b1xxx_0101: alu_opcode = `AND; // BIT
                        8'b1xxx_0110: alu_opcode = `LD;
                        8'b1xxx_0111: alu_opcode = `ST;
                        8'b1xxx_1000: alu_opcode = `EOR;
                        8'b1xxx_1001: alu_opcode = `ADC;
                        8'b1xxx_1010: alu_opcode = `OR;
                        8'b1xxx_1011: alu_opcode = `ADD;
                        8'b10xx_1100: alu_opcode = `SUB; // CMP
                        8'b11xx_1100: alu_opcode = `LD;
                        8'b11xx_1101: alu_opcode = `LD;
                        8'b1xxx_1110: alu_opcode = `LD;
                        8'b1xxx_1111: alu_opcode = `ST;
 
                        8'h00, 8'b01xx_0000: alu_opcode = `NEG;
                        8'h03, 8'b01xx_0011: alu_opcode = `COM;
                        8'h04, 8'b01xx_0100: alu_opcode = `LSR;
                        8'h06, 8'b01xx_0110: alu_opcode = `ROR;
                        8'h07, 8'b01xx_0111: alu_opcode = `ASR;
                        8'h08, 8'b01xx_1000: alu_opcode = `LSL;
                        8'h09, 8'b01xx_1001: alu_opcode = `ROL;
                        8'h0a, 8'b01xx_1010: begin alu_opcode = `SUB; dec_alu_right_path_mod = `MOD_MINUS1; end // dec
                        8'h0c, 8'b01xx_1100: begin alu_opcode = `ADD; dec_alu_right_path_mod = `MOD_ONE; end // inc
                        8'h0d, 8'b01xx_1101: alu_opcode = `AND;
                        8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
 
                        8'h19: alu_opcode = `DAA;
                        8'h1a: alu_opcode = `ORCC;
                        8'h1c, 8'h3c: alu_opcode = `ANDCC;
                        8'h1d: alu_opcode = `SEXT;
                        //8'h1e: alu_opcode = `EXG;
                        8'b0011_000x: alu_opcode = `LEA;
                        8'h3d: alu_opcode = `MUL;
                endcase
                if (page2_valid)
                        casex (postbyte0)
                                8'b10xx_0011,
                                8'b10xx_1010: alu_opcode = `SUB; //CMP
                                8'b1xxx_1110: alu_opcode = `LD;
                                8'b1xxx_1111: alu_opcode = `ST;
                        endcase
                if (page3_valid)
                        casex (postbyte0)
                                8'b10xx_0011,
                                8'b10xx_1010: alu_opcode = `SUB; //CMP
                                8'b1xxx_1110: alu_opcode = `LD;
                                8'b1xxx_1111: alu_opcode = `ST;
                        endcase
        end
 
endmodule
/* decodes the condition and checks the flags to see if it is met */
module test_condition(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid,
        input wire [7:0] CCR,
        output reg cond_taken
        );
 
wire [7:0] op = page2_valid ? postbyte0:opcode;
 
always @(*)
        begin
                cond_taken = 1'b0;
                if ((op == 8'h16) || (op == 8'h17) || (op == 8'h8D))
                        cond_taken = 1'b1; // LBRA/LBSR, BSR
                if (op[7:4] == 4'h2)
                        case (op[3:0])
                                4'h0: cond_taken = 1'b1; // BRA
                                4'h1: cond_taken = 0; // BRN
                                4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
                                4'h3: cond_taken = `DFLAGC | `DFLAGZ; // BLS
                                4'h4: cond_taken = !`DFLAGC; // BCC, BHS
                                4'h5: cond_taken = `DFLAGC; // BCS, BLO
                                4'h6: cond_taken = !`DFLAGZ; // BNE
                                4'h7: cond_taken = `DFLAGZ; // BEQ
                                4'h8: cond_taken = !`DFLAGV; // BVC
                                4'h9: cond_taken = `DFLAGV; // BVS
                                4'ha: cond_taken = !`DFLAGN; // BPL
                                4'hb: cond_taken = `DFLAGN; // BMI
                                4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
                                4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
                                4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
                                4'hf: cond_taken = (`DFLAGN != `DFLAGV) | (`DFLAGZ); // BLE
                endcase
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	ale500
2			`/*`
3			`* Signals which registers have to be read/written for the current opcode`
4			`*`
5			`*`
6			`*`
7			`*/`
8			`include "defs.v"
9	9	ale500	`module decode_regs(`
10			`input wire cpu_clk,`
11	2	ale500	`input wire [7:0] opcode,`
12			`input wire [7:0] postbyte0,`
13			`input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
14			`input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
15	9	ale500	`output reg [3:0] path_left_addr_o,`
16			`output reg [3:0] path_right_addr_o,`
17			`output reg [3:0] dest_reg_o,`
18	4	ale500	`output wire write_dest,`
19			`output wire source_size,`
20	2	ale500	`output wire result_size`
21	9	ale500	`);`
22			`reg [3:0] path_left_addr, path_right_addr, dest_reg;`
23	2	ale500	`// for registers, memory writes are handled differently`
24	4	ale500	assign write_dest = (dest_reg != `RN_INV);
25			assign source_size = (path_left_addr < `RN_ACCA);
26	2	ale500	assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
27			`always @(opcode, postbyte0, page2_valid, page3_valid)`
28			`begin`
29			path_left_addr = `RN_INV;
30			path_right_addr = `RN_INV;
31			dest_reg = `RN_INV;
32	4	ale500	`if (page2_valid)`
33	2	ale500	`begin`
34			`casex(postbyte0)`
35	4	ale500	8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
36			8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
37			8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
38			8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
39			8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
40	2	ale500	`endcase`
41			`casex (postbyte0) // right arm`
42	4	ale500	8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
43	2	ale500	8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
44			8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
45			8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
46	10	ale500	8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
47	4	ale500	8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
48	2	ale500	`endcase`
49			`casex(postbyte0) // dest`
50	10	ale500	`8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd`
51			`8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy`
52			8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
53	4	ale500	8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
54	10	ale500	8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
55			8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
56	2	ale500	`endcase`
57	4	ale500	`end`
58			`if (page3_valid)`
59			`begin`
60			`casex(postbyte0)`
61			8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
62			8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
63			`endcase`
64			`casex (postbyte0) // right arm`
65	10	ale500	8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
66			8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
67			8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
68	4	ale500	`endcase`
69			`casex(postbyte0) // dest`
70			`8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu`
71			`8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps`
72			`endcase`
73	2	ale500	`end`
74			`// destination`
75	5	ale500	`casex(opcode)`
76			`8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg`
77	2	ale500	8'h30: dest_reg = `RN_IX;
78			8'h31: dest_reg = `RN_IY;
79			8'h32: dest_reg = `RN_S;
80			8'h33: dest_reg = `RN_U;
81			8'h39: dest_reg = `RN_PC; // rts
82			8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
83			8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
84			8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
85			8'h0x, 8'h7x: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
86			`8'h6x:`
87			`case (opcode[3:0])`
88			4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
89			default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
90			`endcase`
91	10	ale500	`8'h8x, 8'h9x, 8'hax, 8'hbx:`
92			`case (opcode[3:0]) // default A->A`
93	9	ale500	4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
94	2	ale500	4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
95	10	ale500	4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
96	4	ale500	4'hc: path_left_addr = `RN_IX; // cmpx
97	2	ale500	`4'hd: begin end // nothing active, jsr`
98	10	ale500	4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
99			4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
100	2	ale500	default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
101			`endcase`
102	10	ale500	`8'hcx, 8'hdx, 8'hex, 8'hfx:`
103	2	ale500	`case (opcode[3:0])`
104	9	ale500	4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
105	2	ale500	4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
106			4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
107	10	ale500	4'hd: begin path_left_addr = `RN_ACCD; end // LDD
108			4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU
109			4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
110	2	ale500	default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
111			`endcase`
112			`endcase`
113			`casex (opcode) // right arm`
114			`// 8x and Cx`
115	10	ale500	8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb
116			8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
117			8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
118	2	ale500	`// 9, A, B, D, E, F`
119			8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
120	10	ale500	8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx
121			8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx: path_right_addr = `RN_MEM8;
122	2	ale500	8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
123	10	ale500	8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
124			8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
125	2	ale500	`endcase`
126			`end`
127	9	ale500	`always @(posedge cpu_clk)`
128			`begin`
129			`path_right_addr_o <= path_right_addr;`
130			`path_left_addr_o <= path_left_addr;`
131			`dest_reg_o <= dest_reg;`
132			`end`
133	2	ale500	`endmodule`
134
135			`/* Decodes module and addressing mode for page 1 opcodes */`
136			`module decode_op(`
137			`input wire [7:0] opcode,`
138			`input wire [7:0] postbyte0,`
139			`input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
140			`input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
141			`output reg [2:0] mode,`
142			`output reg [2:0] optype,`
143			`output reg use_s`
144			`);`
145
146			`wire [3:0] oplo;`
147			`reg size;`
148			`assign oplo = opcode[3:0];`
149
150			`always @(opcode, postbyte0, page2_valid, page3_valid, oplo)`
151			`begin`
152			//dsize = `DSZ_8; // data operand size
153			//msize = `MSZ_8; // memory operand size
154			optype = `OP_NONE;
155			`use_s = 1;`
156			mode = `NONE;
157			`size = 0;`
158			`// Addressing mode`
159			`casex(opcode)`
160			8'h0x: begin mode = `DIRECT; end
161			8'h12, 8'h13, 8'h19: mode = `INHERENT;
162			8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
163			8'h16: mode = `REL16;
164			8'h17: begin mode = `REL16; optype = `OP_JSR; end
165	5	ale500	8'h1a, 8'h1c, 8'h1d, 8'h1e, 8'h1f: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
166	2	ale500
167			8'h2x: mode = `REL8;
168			8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; optype = `OP_LEA; end
169			8'h34: begin optype = `OP_PUSH; mode = `NONE; end
170			8'h35: begin optype = `OP_PULL; mode = `NONE; end
171			8'h36: begin optype = `OP_PUSH; mode = `NONE; use_s = 0; end
172			8'h37: begin optype = `OP_PULL; mode = `NONE; use_s = 0; end
173			8'h38, 8'h3e: mode = `NONE;
174			`// don't change to inh because SEQ_MEM_READ_x would not use register S as address`
175			8'h39, 8'h3b: begin mode = `NONE; optype = `OP_RTS; end
176			8'h3a, 8'h3c, 8'h3d, 8'h3f: mode = `INHERENT;
177
178			8'h4x: begin mode = `INHERENT; end
179			8'h5x: begin mode = `INHERENT; end
180			8'h6x: begin mode = `INDEXED; end
181			8'h7x: begin mode = `EXTENDED; end
182			`8'h8x:`
183			`begin`
184			`case (oplo)`
185			4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
186			4'hd: mode = `REL8; // bsr
187			default: mode = `IMMEDIATE;
188			`endcase`
189			`end`
190			`8'hcx:`
191			`begin`
192			`case (oplo)`
193			4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
194			default: mode = `IMMEDIATE;
195			`endcase`
196			`end`
197			8'h9x, 8'hdx: begin mode = `DIRECT; end
198			8'hax, 8'hex: begin mode = `INDEXED; end
199			8'hbx, 8'hfx: begin mode = `EXTENDED; end
200			`endcase`
201			`// Opcode type`
202			`casex(opcode)`
203			8'b1xxx0110: optype = `OP_LD;
204			8'b1xxx0111: optype = `OP_ST;
205			8'b11xx1100: optype = `OP_LD; // LDD
206			8'b10xx1101: begin optype = `OP_JSR; end// bsr & jsr
207			8'b1xxx1110: optype = `OP_LD; // LDX, LDU
208	10	ale500	8'b1xxx1111, 8'b11xx1101: optype = `OP_ST;
209	2	ale500	`endcase`
210			`if (page2_valid == 1'b1)`
211			`begin`
212			`casex(postbyte0)`
213			8'h1x: mode = `REL16;
214			8'h2f: mode = `INHERENT;
215			8'h83: begin mode = `IMMEDIATE; size = 1; end
216			`//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end`
217			8'h8c: begin mode = `IMMEDIATE; size = 1; end
218			`//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end`
219			8'h8e: begin mode = `IMMEDIATE; size = 1; end
220			`//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end`
221			`//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end`
222			8'hce: begin mode = `IMMEDIATE; size = 1; end
223			`//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end`
224			`//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end`
225			`endcase`
226			`casex( postbyte0)`
227			8'h9x, 8'hdx: mode = `DIRECT;
228			8'hax, 8'hex: mode = `INDEXED;
229			8'hbx, 8'hfx: mode = `EXTENDED;
230			`endcase`
231			`casex( postbyte0)`
232			8'b1xxx1110: optype = `OP_LD; // LDY, LDS
233			8'b1xxx1111, 8'b1xxx1101: optype = `OP_ST; // STY, STS
234			`endcase`
235			`end`
236			`if (page3_valid == 1'b1)`
237			`begin`
238			`casex(postbyte0)`
239			8'h2f: mode = `INHERENT;
240			8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
241			`//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD`
242			8'h8c: begin mode = `IMMEDIATE; size = 1; end
243			`//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end`
244			8'h8e: begin mode = `IMMEDIATE; size = 1; end
245			`//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end`
246			`//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end`
247			8'hce: begin mode = `IMMEDIATE; size = 1; end
248			`//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end`
249			`//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end`
250			`endcase`
251			`casex( postbyte0)`
252			8'h9x, 8'hdx: mode = `DIRECT;
253			8'hax, 8'hex: mode = `INDEXED;
254			8'hbx, 8'hfx: mode = `EXTENDED;
255			`endcase`
256			`end`
257			`end`
258
259			`endmodule`
260
261			`/* Decodes the Effective Address postbyte`
262			`to recover size of offset to load and post-incr/pre-decr info`
263			`*/`
264			`module decode_ea(`
265			`input wire [7:0] eapostbyte,`
266			`output reg noofs,`
267			`output reg ofs8, // needs an 8 bit offset`
268			`output reg ofs16, // needs an 16 bit offset`
269			`output reg write_post, // needs to write back a predecr or post incr`
270			`output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address`
271			`);`
272
273			`assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;`
274			`always @(*)`
275			`begin`
276			`noofs = 0;`
277			`ofs8 = 0;`
278			`ofs16 = 0;`
279			`write_post = 0;`
280			`casex (eapostbyte)`
281			`8'b0xxxxxxx, 8'b1xx00100: noofs = 1;`
282			`8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;`
283			`8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;`
284			`8'b1xx11111: ofs16 = 1; // extended indirect`
285			`8'b1xxx00xx: write_post = 1;`
286			`endcase`
287			`end`
288			`endmodule`
289
290			`module decode_alu(`
291			`input wire [7:0] opcode,`
292			`input wire [7:0] postbyte0,`
293			`input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode`
294			`input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode`
295			`output reg [4:0] alu_opcode,`
296			`output reg [1:0] dec_alu_right_path_mod,`
297			`output wire dest_flags`
298			`);`
299
300			assign dest_flags = alu_opcode != `NOP;
301			`always @(*)`
302			`begin`
303			alu_opcode = `NOP;
304			dec_alu_right_path_mod = `MOD_DEFAULT;
305			`casex (opcode)`
306			8'b1xxx_0000: alu_opcode = `SUB;
307	9	ale500	8'b1xxx_0001: alu_opcode = `SUB; // CMP
308	2	ale500	8'b1xxx_0010: alu_opcode = `SBC;
309			8'b10xx_0011: alu_opcode = `SUB;
310			8'b11xx_0011: alu_opcode = `ADD;
311			8'b1xxx_0100: alu_opcode = `AND;
312	9	ale500	8'b1xxx_0101: alu_opcode = `AND; // BIT
313	2	ale500	8'b1xxx_0110: alu_opcode = `LD;
314			8'b1xxx_0111: alu_opcode = `ST;
315			8'b1xxx_1000: alu_opcode = `EOR;
316			8'b1xxx_1001: alu_opcode = `ADC;
317			8'b1xxx_1010: alu_opcode = `OR;
318			8'b1xxx_1011: alu_opcode = `ADD;
319	9	ale500	8'b10xx_1100: alu_opcode = `SUB; // CMP
320	2	ale500	8'b11xx_1100: alu_opcode = `LD;
321			8'b11xx_1101: alu_opcode = `LD;
322			8'b1xxx_1110: alu_opcode = `LD;
323			8'b1xxx_1111: alu_opcode = `ST;
324
325			8'h00, 8'b01xx_0000: alu_opcode = `NEG;
326			8'h03, 8'b01xx_0011: alu_opcode = `COM;
327			8'h04, 8'b01xx_0100: alu_opcode = `LSR;
328			8'h06, 8'b01xx_0110: alu_opcode = `ROR;
329			8'h07, 8'b01xx_0111: alu_opcode = `ASR;
330			8'h08, 8'b01xx_1000: alu_opcode = `LSL;
331			8'h09, 8'b01xx_1001: alu_opcode = `ROL;
332			8'h0a, 8'b01xx_1010: begin alu_opcode = `SUB; dec_alu_right_path_mod = `MOD_MINUS1; end // dec
333			8'h0c, 8'b01xx_1100: begin alu_opcode = `ADD; dec_alu_right_path_mod = `MOD_ONE; end // inc
334			8'h0d, 8'b01xx_1101: alu_opcode = `AND;
335			8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
336
337			8'h19: alu_opcode = `DAA;
338			8'h1a: alu_opcode = `ORCC;
339	6	ale500	8'h1c, 8'h3c: alu_opcode = `ANDCC;
340	2	ale500	8'h1d: alu_opcode = `SEXT;
341	9	ale500	//8'h1e: alu_opcode = `EXG;
342	4	ale500	8'b0011_000x: alu_opcode = `LEA;
343	2	ale500	8'h3d: alu_opcode = `MUL;
344			`endcase`
345			`if (page2_valid)`
346			`casex (postbyte0)`
347			`8'b10xx_0011,`
348	9	ale500	8'b10xx_1010: alu_opcode = `SUB; //CMP
349	2	ale500	8'b1xxx_1110: alu_opcode = `LD;
350			8'b1xxx_1111: alu_opcode = `ST;
351			`endcase`
352			`if (page3_valid)`
353			`casex (postbyte0)`
354			`8'b10xx_0011,`
355	9	ale500	8'b10xx_1010: alu_opcode = `SUB; //CMP
356	2	ale500	8'b1xxx_1110: alu_opcode = `LD;
357			8'b1xxx_1111: alu_opcode = `ST;
358			`endcase`
359			`end`
360
361			`endmodule`
362			`/* decodes the condition and checks the flags to see if it is met */`
363			`module test_condition(`
364			`input wire [7:0] opcode,`
365			`input wire [7:0] postbyte0,`
366			`input wire page2_valid,`
367			`input wire [7:0] CCR,`
368			`output reg cond_taken`
369			`);`
370
371			`wire [7:0] op = page2_valid ? postbyte0:opcode;`
372
373			`always @(*)`
374			`begin`
375			`cond_taken = 1'b0;`
376			`if ((op == 8'h16) \|\| (op == 8'h17) \|\| (op == 8'h8D))`
377			`cond_taken = 1'b1; // LBRA/LBSR, BSR`
378			`if (op[7:4] == 4'h2)`
379			`case (op[3:0])`
380			`4'h0: cond_taken = 1'b1; // BRA`
381			`4'h1: cond_taken = 0; // BRN`
382			4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
383			4'h3: cond_taken = `DFLAGC \| `DFLAGZ; // BLS
384			4'h4: cond_taken = !`DFLAGC; // BCC, BHS
385			4'h5: cond_taken = `DFLAGC; // BCS, BLO
386			4'h6: cond_taken = !`DFLAGZ; // BNE
387			4'h7: cond_taken = `DFLAGZ; // BEQ
388			4'h8: cond_taken = !`DFLAGV; // BVC
389			4'h9: cond_taken = `DFLAGV; // BVS
390			4'ha: cond_taken = !`DFLAGN; // BPL
391			4'hb: cond_taken = `DFLAGN; // BMI
392			4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
393			4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
394			4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
395			4'hf: cond_taken = (`DFLAGN != `DFLAGV) \| (`DFLAGZ); // BLE
396			`endcase`
397			`end`
398
399			`endmodule`

Browse

Tools

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [decoders.v] - Blame information for rev 10