| 1 |
2 |
ale500 |
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/*
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| 3 |
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* Signals which registers have to be read/written for the current opcode
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*
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*
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*
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*/
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`include "defs.v"
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9 |
ale500 |
module decode_regs(
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| 10 |
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input wire cpu_clk,
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2 |
ale500 |
input wire [7:0] opcode,
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input wire [7:0] postbyte0,
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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11 |
ale500 |
output wire [3:0] path_left_addr_o,
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output wire [3:0] path_right_addr_o,
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output wire [3:0] dest_reg_o,
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output reg [3:0] path_left_addr_lo,
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output reg [3:0] path_right_addr_lo,
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output reg [3:0] dest_reg_lo,
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4 |
ale500 |
output wire write_dest,
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output wire source_size,
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2 |
ale500 |
output wire result_size
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ale500 |
);
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reg [3:0] path_left_addr, path_right_addr, dest_reg;
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2 |
ale500 |
// for registers, memory writes are handled differently
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4 |
ale500 |
assign write_dest = (dest_reg != `RN_INV);
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assign source_size = (path_left_addr < `RN_ACCA);
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ale500 |
assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
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11 |
ale500 |
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assign path_right_addr_o = path_right_addr;
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assign path_left_addr_o = path_left_addr;
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assign dest_reg_o = dest_reg;
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ale500 |
always @(opcode, postbyte0, page2_valid, page3_valid)
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begin
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path_left_addr = `RN_INV;
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path_right_addr = `RN_INV;
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dest_reg = `RN_INV;
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4 |
ale500 |
if (page2_valid)
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2 |
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begin
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casex(postbyte0)
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4 |
ale500 |
8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
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8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
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8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
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8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
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ale500 |
endcase
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casex (postbyte0) // right arm
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4 |
ale500 |
8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
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2 |
ale500 |
8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
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10 |
ale500 |
8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
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4 |
ale500 |
8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
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2 |
ale500 |
endcase
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casex(postbyte0) // dest
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10 |
ale500 |
8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy
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8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
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4 |
ale500 |
8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
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8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
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8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
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2 |
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endcase
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4 |
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end
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if (page3_valid)
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begin
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casex(postbyte0)
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
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endcase
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casex (postbyte0) // right arm
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10 |
ale500 |
8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
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4 |
ale500 |
endcase
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casex(postbyte0) // dest
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
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endcase
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2 |
ale500 |
end
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// destination
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5 |
ale500 |
casex(opcode)
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8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg
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ale500 |
8'h30: dest_reg = `RN_IX;
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8'h31: dest_reg = `RN_IY;
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8'h32: dest_reg = `RN_S;
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8'h33: dest_reg = `RN_U;
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8'h39: dest_reg = `RN_PC; // rts
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8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
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8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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11 |
ale500 |
8'h0x, 8'h6x, 8'h7x:
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2 |
ale500 |
case (opcode[3:0])
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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endcase
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10 |
ale500 |
8'h8x, 8'h9x, 8'hax, 8'hbx:
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case (opcode[3:0]) // default A->A
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9 |
ale500 |
4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
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| 102 |
2 |
ale500 |
4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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| 103 |
10 |
ale500 |
4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
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4 |
ale500 |
4'hc: path_left_addr = `RN_IX; // cmpx
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2 |
ale500 |
4'hd: begin end // nothing active, jsr
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10 |
ale500 |
4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
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2 |
ale500 |
default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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endcase
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10 |
ale500 |
8'hcx, 8'hdx, 8'hex, 8'hfx:
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2 |
ale500 |
case (opcode[3:0])
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9 |
ale500 |
4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
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2 |
ale500 |
4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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10 |
ale500 |
4'hd: begin path_left_addr = `RN_ACCD; end // LDD
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU
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| 117 |
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4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
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2 |
ale500 |
default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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endcase
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endcase
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casex (opcode) // right arm
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// 8x and Cx
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10 |
ale500 |
8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb
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8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
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8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
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2 |
ale500 |
// 9, A, B, D, E, F
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8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
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| 128 |
10 |
ale500 |
8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx
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8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx: path_right_addr = `RN_MEM8;
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2 |
ale500 |
8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
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10 |
ale500 |
8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
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8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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2 |
ale500 |
endcase
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end
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| 135 |
11 |
ale500 |
// latched versions are used to fetch regsiters
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| 136 |
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// not-latched version in the decoder
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| 137 |
9 |
ale500 |
always @(posedge cpu_clk)
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| 138 |
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begin
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| 139 |
11 |
ale500 |
path_right_addr_lo <= path_right_addr;
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| 140 |
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path_left_addr_lo <= path_left_addr;
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| 141 |
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dest_reg_lo <= dest_reg;
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| 142 |
9 |
ale500 |
end
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11 |
ale500 |
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| 144 |
2 |
ale500 |
endmodule
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| 145 |
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| 146 |
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/* Decodes module and addressing mode for page 1 opcodes */
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| 147 |
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module decode_op(
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| 148 |
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input wire [7:0] opcode,
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| 149 |
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input wire [7:0] postbyte0,
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| 150 |
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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| 151 |
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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| 152 |
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output reg [2:0] mode,
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| 153 |
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output reg [2:0] optype,
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| 154 |
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output reg use_s
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| 155 |
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);
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| 156 |
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| 157 |
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wire [3:0] oplo;
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| 158 |
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reg size;
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| 159 |
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assign oplo = opcode[3:0];
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| 160 |
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| 161 |
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always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
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| 162 |
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begin
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| 163 |
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//dsize = `DSZ_8; // data operand size
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| 164 |
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//msize = `MSZ_8; // memory operand size
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| 165 |
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optype = `OP_NONE;
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| 166 |
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use_s = 1;
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| 167 |
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mode = `NONE;
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| 168 |
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size = 0;
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| 169 |
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// Addressing mode
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| 170 |
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casex(opcode)
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| 171 |
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8'h0x: begin mode = `DIRECT; end
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| 172 |
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8'h12, 8'h13, 8'h19: mode = `INHERENT;
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| 173 |
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8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
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| 174 |
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8'h16: mode = `REL16;
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| 175 |
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8'h17: begin mode = `REL16; optype = `OP_JSR; end
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| 176 |
5 |
ale500 |
8'h1a, 8'h1c, 8'h1d, 8'h1e, 8'h1f: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
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| 177 |
2 |
ale500 |
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| 178 |
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8'h2x: mode = `REL8;
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| 179 |
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8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; optype = `OP_LEA; end
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| 180 |
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8'h34: begin optype = `OP_PUSH; mode = `NONE; end
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| 181 |
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8'h35: begin optype = `OP_PULL; mode = `NONE; end
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| 182 |
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8'h36: begin optype = `OP_PUSH; mode = `NONE; use_s = 0; end
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| 183 |
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8'h37: begin optype = `OP_PULL; mode = `NONE; use_s = 0; end
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| 184 |
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8'h38, 8'h3e: mode = `NONE;
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| 185 |
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// don't change to inh because SEQ_MEM_READ_x would not use register S as address
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| 186 |
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8'h39, 8'h3b: begin mode = `NONE; optype = `OP_RTS; end
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| 187 |
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8'h3a, 8'h3c, 8'h3d, 8'h3f: mode = `INHERENT;
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| 188 |
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| 189 |
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8'h4x: begin mode = `INHERENT; end
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| 190 |
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8'h5x: begin mode = `INHERENT; end
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| 191 |
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8'h6x: begin mode = `INDEXED; end
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| 192 |
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8'h7x: begin mode = `EXTENDED; end
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| 193 |
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8'h8x:
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| 194 |
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begin
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| 195 |
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case (oplo)
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| 196 |
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4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
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| 197 |
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4'hd: mode = `REL8; // bsr
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| 198 |
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default: mode = `IMMEDIATE;
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| 199 |
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endcase
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| 200 |
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end
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| 201 |
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8'hcx:
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| 202 |
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begin
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| 203 |
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case (oplo)
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| 204 |
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4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
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| 205 |
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default: mode = `IMMEDIATE;
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| 206 |
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endcase
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| 207 |
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end
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| 208 |
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8'h9x, 8'hdx: begin mode = `DIRECT; end
|
| 209 |
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8'hax, 8'hex: begin mode = `INDEXED; end
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| 210 |
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8'hbx, 8'hfx: begin mode = `EXTENDED; end
|
| 211 |
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endcase
|
| 212 |
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// Opcode type
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| 213 |
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casex(opcode)
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| 214 |
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8'b1xxx0110: optype = `OP_LD;
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| 215 |
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8'b1xxx0111: optype = `OP_ST;
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| 216 |
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8'b11xx1100: optype = `OP_LD; // LDD
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| 217 |
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8'b10xx1101: begin optype = `OP_JSR; end// bsr & jsr
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| 218 |
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8'b1xxx1110: optype = `OP_LD; // LDX, LDU
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| 219 |
10 |
ale500 |
8'b1xxx1111, 8'b11xx1101: optype = `OP_ST;
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| 220 |
2 |
ale500 |
endcase
|
| 221 |
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if (page2_valid == 1'b1)
|
| 222 |
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begin
|
| 223 |
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casex(postbyte0)
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| 224 |
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8'h1x: mode = `REL16;
|
| 225 |
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8'h2f: mode = `INHERENT;
|
| 226 |
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8'h83: begin mode = `IMMEDIATE; size = 1; end
|
| 227 |
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//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
|
| 228 |
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8'h8c: begin mode = `IMMEDIATE; size = 1; end
|
| 229 |
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//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
|
| 230 |
|
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8'h8e: begin mode = `IMMEDIATE; size = 1; end
|
| 231 |
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//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
|
| 232 |
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//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
|
| 233 |
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8'hce: begin mode = `IMMEDIATE; size = 1; end
|
| 234 |
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//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
|
| 235 |
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//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
|
| 236 |
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endcase
|
| 237 |
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casex( postbyte0)
|
| 238 |
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8'h9x, 8'hdx: mode = `DIRECT;
|
| 239 |
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8'hax, 8'hex: mode = `INDEXED;
|
| 240 |
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8'hbx, 8'hfx: mode = `EXTENDED;
|
| 241 |
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endcase
|
| 242 |
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casex( postbyte0)
|
| 243 |
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8'b1xxx1110: optype = `OP_LD; // LDY, LDS
|
| 244 |
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8'b1xxx1111, 8'b1xxx1101: optype = `OP_ST; // STY, STS
|
| 245 |
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endcase
|
| 246 |
|
|
end
|
| 247 |
|
|
if (page3_valid == 1'b1)
|
| 248 |
|
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begin
|
| 249 |
|
|
casex(postbyte0)
|
| 250 |
|
|
8'h2f: mode = `INHERENT;
|
| 251 |
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8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
|
| 252 |
|
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//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
|
| 253 |
|
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8'h8c: begin mode = `IMMEDIATE; size = 1; end
|
| 254 |
|
|
//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
|
| 255 |
|
|
8'h8e: begin mode = `IMMEDIATE; size = 1; end
|
| 256 |
|
|
//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
|
| 257 |
|
|
//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
|
| 258 |
|
|
8'hce: begin mode = `IMMEDIATE; size = 1; end
|
| 259 |
|
|
//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
|
| 260 |
|
|
//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
|
| 261 |
|
|
endcase
|
| 262 |
|
|
casex( postbyte0)
|
| 263 |
|
|
8'h9x, 8'hdx: mode = `DIRECT;
|
| 264 |
|
|
8'hax, 8'hex: mode = `INDEXED;
|
| 265 |
|
|
8'hbx, 8'hfx: mode = `EXTENDED;
|
| 266 |
|
|
endcase
|
| 267 |
|
|
end
|
| 268 |
|
|
end
|
| 269 |
|
|
|
| 270 |
|
|
endmodule
|
| 271 |
|
|
|
| 272 |
|
|
/* Decodes the Effective Address postbyte
|
| 273 |
|
|
to recover size of offset to load and post-incr/pre-decr info
|
| 274 |
|
|
*/
|
| 275 |
|
|
module decode_ea(
|
| 276 |
|
|
input wire [7:0] eapostbyte,
|
| 277 |
|
|
output reg noofs,
|
| 278 |
|
|
output reg ofs8, // needs an 8 bit offset
|
| 279 |
|
|
output reg ofs16, // needs an 16 bit offset
|
| 280 |
|
|
output reg write_post, // needs to write back a predecr or post incr
|
| 281 |
|
|
output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address
|
| 282 |
|
|
);
|
| 283 |
|
|
|
| 284 |
|
|
assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;
|
| 285 |
|
|
always @(*)
|
| 286 |
|
|
begin
|
| 287 |
|
|
noofs = 0;
|
| 288 |
|
|
ofs8 = 0;
|
| 289 |
|
|
ofs16 = 0;
|
| 290 |
|
|
write_post = 0;
|
| 291 |
|
|
casex (eapostbyte)
|
| 292 |
|
|
8'b0xxxxxxx, 8'b1xx00100: noofs = 1;
|
| 293 |
|
|
8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;
|
| 294 |
|
|
8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;
|
| 295 |
|
|
8'b1xx11111: ofs16 = 1; // extended indirect
|
| 296 |
|
|
8'b1xxx00xx: write_post = 1;
|
| 297 |
|
|
endcase
|
| 298 |
|
|
end
|
| 299 |
|
|
endmodule
|
| 300 |
|
|
|
| 301 |
|
|
module decode_alu(
|
| 302 |
|
|
input wire [7:0] opcode,
|
| 303 |
|
|
input wire [7:0] postbyte0,
|
| 304 |
|
|
input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode
|
| 305 |
|
|
input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode
|
| 306 |
|
|
output reg [4:0] alu_opcode,
|
| 307 |
|
|
output reg [1:0] dec_alu_right_path_mod,
|
| 308 |
|
|
output wire dest_flags
|
| 309 |
|
|
);
|
| 310 |
|
|
|
| 311 |
|
|
assign dest_flags = alu_opcode != `NOP;
|
| 312 |
|
|
always @(*)
|
| 313 |
|
|
begin
|
| 314 |
|
|
alu_opcode = `NOP;
|
| 315 |
|
|
dec_alu_right_path_mod = `MOD_DEFAULT;
|
| 316 |
|
|
casex (opcode)
|
| 317 |
|
|
8'b1xxx_0000: alu_opcode = `SUB;
|
| 318 |
9 |
ale500 |
8'b1xxx_0001: alu_opcode = `SUB; // CMP
|
| 319 |
2 |
ale500 |
8'b1xxx_0010: alu_opcode = `SBC;
|
| 320 |
|
|
8'b10xx_0011: alu_opcode = `SUB;
|
| 321 |
|
|
8'b11xx_0011: alu_opcode = `ADD;
|
| 322 |
|
|
8'b1xxx_0100: alu_opcode = `AND;
|
| 323 |
9 |
ale500 |
8'b1xxx_0101: alu_opcode = `AND; // BIT
|
| 324 |
2 |
ale500 |
8'b1xxx_0110: alu_opcode = `LD;
|
| 325 |
|
|
8'b1xxx_0111: alu_opcode = `ST;
|
| 326 |
|
|
8'b1xxx_1000: alu_opcode = `EOR;
|
| 327 |
|
|
8'b1xxx_1001: alu_opcode = `ADC;
|
| 328 |
|
|
8'b1xxx_1010: alu_opcode = `OR;
|
| 329 |
|
|
8'b1xxx_1011: alu_opcode = `ADD;
|
| 330 |
9 |
ale500 |
8'b10xx_1100: alu_opcode = `SUB; // CMP
|
| 331 |
2 |
ale500 |
8'b11xx_1100: alu_opcode = `LD;
|
| 332 |
|
|
8'b11xx_1101: alu_opcode = `LD;
|
| 333 |
|
|
8'b1xxx_1110: alu_opcode = `LD;
|
| 334 |
|
|
8'b1xxx_1111: alu_opcode = `ST;
|
| 335 |
|
|
|
| 336 |
|
|
8'h00, 8'b01xx_0000: alu_opcode = `NEG;
|
| 337 |
|
|
8'h03, 8'b01xx_0011: alu_opcode = `COM;
|
| 338 |
|
|
8'h04, 8'b01xx_0100: alu_opcode = `LSR;
|
| 339 |
|
|
8'h06, 8'b01xx_0110: alu_opcode = `ROR;
|
| 340 |
|
|
8'h07, 8'b01xx_0111: alu_opcode = `ASR;
|
| 341 |
|
|
8'h08, 8'b01xx_1000: alu_opcode = `LSL;
|
| 342 |
|
|
8'h09, 8'b01xx_1001: alu_opcode = `ROL;
|
| 343 |
11 |
ale500 |
8'h0a, 8'b01xx_1010: begin alu_opcode = `SUB; dec_alu_right_path_mod = `MOD_ONE; end // dec
|
| 344 |
2 |
ale500 |
8'h0c, 8'b01xx_1100: begin alu_opcode = `ADD; dec_alu_right_path_mod = `MOD_ONE; end // inc
|
| 345 |
|
|
8'h0d, 8'b01xx_1101: alu_opcode = `AND;
|
| 346 |
|
|
8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
|
| 347 |
|
|
|
| 348 |
|
|
8'h19: alu_opcode = `DAA;
|
| 349 |
|
|
8'h1a: alu_opcode = `ORCC;
|
| 350 |
6 |
ale500 |
8'h1c, 8'h3c: alu_opcode = `ANDCC;
|
| 351 |
2 |
ale500 |
8'h1d: alu_opcode = `SEXT;
|
| 352 |
9 |
ale500 |
//8'h1e: alu_opcode = `EXG;
|
| 353 |
4 |
ale500 |
8'b0011_000x: alu_opcode = `LEA;
|
| 354 |
2 |
ale500 |
8'h3d: alu_opcode = `MUL;
|
| 355 |
|
|
endcase
|
| 356 |
|
|
if (page2_valid)
|
| 357 |
|
|
casex (postbyte0)
|
| 358 |
|
|
8'b10xx_0011,
|
| 359 |
9 |
ale500 |
8'b10xx_1010: alu_opcode = `SUB; //CMP
|
| 360 |
2 |
ale500 |
8'b1xxx_1110: alu_opcode = `LD;
|
| 361 |
|
|
8'b1xxx_1111: alu_opcode = `ST;
|
| 362 |
|
|
endcase
|
| 363 |
|
|
if (page3_valid)
|
| 364 |
|
|
casex (postbyte0)
|
| 365 |
|
|
8'b10xx_0011,
|
| 366 |
9 |
ale500 |
8'b10xx_1010: alu_opcode = `SUB; //CMP
|
| 367 |
2 |
ale500 |
8'b1xxx_1110: alu_opcode = `LD;
|
| 368 |
|
|
8'b1xxx_1111: alu_opcode = `ST;
|
| 369 |
|
|
endcase
|
| 370 |
|
|
end
|
| 371 |
|
|
|
| 372 |
|
|
endmodule
|
| 373 |
|
|
/* decodes the condition and checks the flags to see if it is met */
|
| 374 |
|
|
module test_condition(
|
| 375 |
|
|
input wire [7:0] opcode,
|
| 376 |
|
|
input wire [7:0] postbyte0,
|
| 377 |
|
|
input wire page2_valid,
|
| 378 |
|
|
input wire [7:0] CCR,
|
| 379 |
|
|
output reg cond_taken
|
| 380 |
|
|
);
|
| 381 |
|
|
|
| 382 |
|
|
wire [7:0] op = page2_valid ? postbyte0:opcode;
|
| 383 |
|
|
|
| 384 |
|
|
always @(*)
|
| 385 |
|
|
begin
|
| 386 |
|
|
cond_taken = 1'b0;
|
| 387 |
|
|
if ((op == 8'h16) || (op == 8'h17) || (op == 8'h8D))
|
| 388 |
|
|
cond_taken = 1'b1; // LBRA/LBSR, BSR
|
| 389 |
|
|
if (op[7:4] == 4'h2)
|
| 390 |
|
|
case (op[3:0])
|
| 391 |
|
|
4'h0: cond_taken = 1'b1; // BRA
|
| 392 |
|
|
4'h1: cond_taken = 0; // BRN
|
| 393 |
|
|
4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
|
| 394 |
|
|
4'h3: cond_taken = `DFLAGC | `DFLAGZ; // BLS
|
| 395 |
|
|
4'h4: cond_taken = !`DFLAGC; // BCC, BHS
|
| 396 |
|
|
4'h5: cond_taken = `DFLAGC; // BCS, BLO
|
| 397 |
|
|
4'h6: cond_taken = !`DFLAGZ; // BNE
|
| 398 |
|
|
4'h7: cond_taken = `DFLAGZ; // BEQ
|
| 399 |
|
|
4'h8: cond_taken = !`DFLAGV; // BVC
|
| 400 |
|
|
4'h9: cond_taken = `DFLAGV; // BVS
|
| 401 |
|
|
4'ha: cond_taken = !`DFLAGN; // BPL
|
| 402 |
|
|
4'hb: cond_taken = `DFLAGN; // BMI
|
| 403 |
|
|
4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
|
| 404 |
|
|
4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
|
| 405 |
|
|
4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
|
| 406 |
|
|
4'hf: cond_taken = (`DFLAGN != `DFLAGV) | (`DFLAGZ); // BLE
|
| 407 |
|
|
endcase
|
| 408 |
|
|
end
|
| 409 |
|
|
|
| 410 |
|
|
endmodule
|
