URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [defs.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


 
`default_nettype none
 
`define RN_ACCD         4'h0
`define RN_IX           4'h1
`define RN_IY           4'h2
`define RN_U            4'h3
`define RN_S            4'h4
`define RN_PC           4'h5
`define RN_MEM16        4'h6
`define RN_IMM16        4'h7
`define RN_ACCA         4'h8
`define RN_ACCB         4'h9
`define RN_CC           4'ha
`define RN_DP           4'hb
`define RN_MEM8         4'hc
`define RN_IMM8         4'hd
`define RN_INV          4'hf
 
 
// opcodes that need an ALU result
`define NOP    5'b00000
`define CMP    5'b00001
`define SBC    5'b00010
`define ADD    5'b00011
`define AND    5'b00100
`define BIT    5'b00101
`define LD     5'b00110
`define ST     5'b00111
`define EOR    5'b01000
`define ADC    5'b01001
`define OR     5'b01010
`define SUB    5'b01011
`define T168L  5'b01100
`define T168H  5'b01101
`define SEXT   5'b01110
`define EXG    5'b01111
 
`define NEG    5'b10000
`define COM    5'b10001
`define LSR    5'b10010
`define ROR    5'b10011
`define ASR    5'b10100
`define LSL    5'b10101
`define ROL    5'b10110
`define ORCC   5'b10111
`define ANDCC  5'b11000
`define DAA    5'b11001
`define MUL    5'b11010
`define T816   5'b11011
`define LEA    5'b11100
 
/* Sequencer states */
 
`define SEQ_COLDRESET           'h00
`define SEQ_NMI                         'h01
`define SEQ_SWI                         'h02
`define SEQ_IRQ                         'h03
`define SEQ_FIRQ                        'h04
`define SEQ_SWI2                        'h05
`define SEQ_SWI3                        'h06
`define SEQ_UNDEF                       'h07
`define SEQ_LOADPC              'h08
`define SEQ_FETCH                       'h09
`define SEQ_FETCH_1             'h0a
`define SEQ_FETCH_2             'h0b
`define SEQ_FETCH_3             'h0c
`define SEQ_FETCH_4             'h0d
`define SEQ_FETCH_5             'h0e
 
`define SEQ_DECODE                      'h0f
`define SEQ_DECODE_P23          'h10
 
`define SEQ_GRAL_ALU            'h11
`define SEQ_GRAL_WBACK          'h12
`define SEQ_CWAI_STACK          'h13 // stacks registers
`define SEQ_CWAI_WAIT           'h14 // waits for an interrupt
`define SEQ_TFREXG                      'h15
 
`define SEQ_IND_READ_EA         'h16 // offset 8 or 16 bits
`define SEQ_IND_READ_EA_1       'h17
`define SEQ_IND_READ_EA_2       'h18 // real operand from memory indirect
`define SEQ_IND_DECODE          'h19
`define SEQ_IND_DECODE_OFS  'h1a // used to load 8 or 16 bits offset
`define SEQ_JMP_LOAD_PC         'h1b
 
 
`define SEQ_JSR_PUSH            'h1c
`define SEQ_JSR_PUSH_L          'h1d
`define SEQ_RTS_POP_L           'h1e
`define SEQ_RTS_POP_H           'h1f
 
`define SEQ_PREPUSH                     'h20
`define SEQ_PREPULL                     'h21
`define SEQ_PUSH_WRITE_L        'h22
`define SEQ_PUSH_WRITE_L_1      'h23
`define SEQ_PUSH_WRITE_H        'h24
`define SEQ_PUSH_WRITE_H_1      'h25
`define SEQ_SYNC                        'h26
 
`define SEQ_PC_READ_H           'h30
`define SEQ_PC_READ_H_1         'h31
`define SEQ_PC_READ_H_2         'h32
`define SEQ_PC_READ_L           'h33
`define SEQ_PC_READ_L_1         'h34
`define SEQ_PC_READ_L_2         'h35
 
`define SEQ_MEM_READ_H          'h36
`define SEQ_MEM_READ_H_1        'h37
`define SEQ_MEM_READ_H_2        'h38
`define SEQ_MEM_READ_L          'h39
`define SEQ_MEM_READ_L_1        'h3a
`define SEQ_MEM_READ_L_2        'h3b
`define SEQ_MEM_WRITE_H         'h3c
`define SEQ_MEM_WRITE_H_1       'h3d
`define SEQ_MEM_WRITE_L         'h3e
`define SEQ_MEM_WRITE_L_1       'h3f
 
 
//`define FLAGC regs_o_CCR[0]
//`define FLAGV regs_o_CCR[1]
//`define FLAGZ regs_o_CCR[2]
//`define FLAGN regs_o_CCR[3]
`define FLAGI regs_o_CCR[5]
`define FLAGF regs_o_CCR[6]
//`define FLAGE regs_o_CCR[7]
 
`define DFLAGC CCR[0]
`define DFLAGV CCR[1]
`define DFLAGZ CCR[2]
`define DFLAGN CCR[3]
// some wires exist only for simulation
`define SIMULATION 1
// Adressing modes
`define NONE            3'h0
`define IMMEDIATE   3'h1
`define INHERENT        3'h2
`define DIRECT          3'h3
`define INDEXED         3'h4
`define EXTENDED        3'h5
`define REL8            3'h6
`define REL16           3'h7
 
// Address size
 
// memory transfer size, read or written, used for addresses 
`define MSZ_0   2'h0
`define MSZ_8   2'h1
`define MSZ_16  2'h2
// Data transfer size, to save to register, used for data from memory and to save results to memory/registers
`define DSZ_0   2'h0
`define DSZ_8   2'h1
`define DSZ_16  2'h2
 
`define OP_NONE         3'h0
`define OP_PUSH         3'h1
`define OP_PULL         3'h2
`define OP_RTS          3'h3
`define OP_JSR          3'h4
`define OP_ST           3'h5
`define OP_LD           3'h6
`define OP_LEA          3'h7
 
/* alu decoder right path modifier */
`define MOD_DEFAULT 2'h0
`define MOD_ONE         2'h1
`define MOD_ZERO        2'h2
`define MOD_MINUS1      2'h3
 
`define MEMDEST_PC      2'h0
`define MEMDEST_MH      2'h1
`define MEMDEST_AH      2'h2
`define MEMDEST_I16     2'h3

Line No.	Rev	Author	Line
1	2	ale500
2			`default_nettype none
3
4			`define RN_ACCD 4'h0
5			`define RN_IX 4'h1
6			`define RN_IY 4'h2
7			`define RN_U 4'h3
8			`define RN_S 4'h4
9			`define RN_PC 4'h5
10			`define RN_MEM16 4'h6
11			`define RN_IMM16 4'h7
12			`define RN_ACCA 4'h8
13			`define RN_ACCB 4'h9
14			`define RN_CC 4'ha
15			`define RN_DP 4'hb
16			`define RN_MEM8 4'hc
17			`define RN_IMM8 4'hd
18			`define RN_INV 4'hf
19
20
21			`// opcodes that need an ALU result`
22			`define NOP 5'b00000
23			`define CMP 5'b00001
24			`define SBC 5'b00010
25			`define ADD 5'b00011
26			`define AND 5'b00100
27			`define BIT 5'b00101
28			`define LD 5'b00110
29			`define ST 5'b00111
30			`define EOR 5'b01000
31			`define ADC 5'b01001
32			`define OR 5'b01010
33			`define SUB 5'b01011
34			`define T168L 5'b01100
35			`define T168H 5'b01101
36			`define SEXT 5'b01110
37			`define EXG 5'b01111
38
39			`define NEG 5'b10000
40	4	ale500	`define COM 5'b10001
41			`define LSR 5'b10010
42			`define ROR 5'b10011
43			`define ASR 5'b10100
44			`define LSL 5'b10101
45			`define ROL 5'b10110
46			`define ORCC 5'b10111
47			`define ANDCC 5'b11000
48			`define DAA 5'b11001
49			`define MUL 5'b11010
50			`define T816 5'b11011
51			`define LEA 5'b11100
52	2	ale500
53			`/* Sequencer states */`
54
55			`define SEQ_COLDRESET 'h00
56			`define SEQ_NMI 'h01
57			`define SEQ_SWI 'h02
58			`define SEQ_IRQ 'h03
59			`define SEQ_FIRQ 'h04
60			`define SEQ_SWI2 'h05
61			`define SEQ_SWI3 'h06
62			`define SEQ_UNDEF 'h07
63			`define SEQ_LOADPC 'h08
64			`define SEQ_FETCH 'h09
65			`define SEQ_FETCH_1 'h0a
66			`define SEQ_FETCH_2 'h0b
67			`define SEQ_FETCH_3 'h0c
68			`define SEQ_FETCH_4 'h0d
69			`define SEQ_FETCH_5 'h0e
70
71			`define SEQ_DECODE 'h0f
72			`define SEQ_DECODE_P23 'h10
73
74	5	ale500	`define SEQ_GRAL_ALU 'h11
75			`define SEQ_GRAL_WBACK 'h12
76	6	ale500	`define SEQ_CWAI_STACK 'h13 // stacks registers
77			`define SEQ_CWAI_WAIT 'h14 // waits for an interrupt
78			`define SEQ_TFREXG 'h15
79	2	ale500
80	6	ale500	`define SEQ_IND_READ_EA 'h16 // offset 8 or 16 bits
81			`define SEQ_IND_READ_EA_1 'h17
82			`define SEQ_IND_READ_EA_2 'h18 // real operand from memory indirect
83			`define SEQ_IND_DECODE 'h19
84			`define SEQ_IND_DECODE_OFS 'h1a // used to load 8 or 16 bits offset
85			`define SEQ_JMP_LOAD_PC 'h1b
86	2	ale500
87
88	6	ale500	`define SEQ_JSR_PUSH 'h1c
89			`define SEQ_JSR_PUSH_L 'h1d
90			`define SEQ_RTS_POP_L 'h1e
91			`define SEQ_RTS_POP_H 'h1f
92	2	ale500
93			`define SEQ_PREPUSH 'h20
94			`define SEQ_PREPULL 'h21
95			`define SEQ_PUSH_WRITE_L 'h22
96			`define SEQ_PUSH_WRITE_L_1 'h23
97			`define SEQ_PUSH_WRITE_H 'h24
98			`define SEQ_PUSH_WRITE_H_1 'h25
99	6	ale500	`define SEQ_SYNC 'h26
100	2	ale500
101			`define SEQ_PC_READ_H 'h30
102			`define SEQ_PC_READ_H_1 'h31
103			`define SEQ_PC_READ_H_2 'h32
104			`define SEQ_PC_READ_L 'h33
105			`define SEQ_PC_READ_L_1 'h34
106			`define SEQ_PC_READ_L_2 'h35
107
108			`define SEQ_MEM_READ_H 'h36
109			`define SEQ_MEM_READ_H_1 'h37
110			`define SEQ_MEM_READ_H_2 'h38
111			`define SEQ_MEM_READ_L 'h39
112			`define SEQ_MEM_READ_L_1 'h3a
113			`define SEQ_MEM_READ_L_2 'h3b
114			`define SEQ_MEM_WRITE_H 'h3c
115			`define SEQ_MEM_WRITE_H_1 'h3d
116			`define SEQ_MEM_WRITE_L 'h3e
117			`define SEQ_MEM_WRITE_L_1 'h3f
118
119
120			//`define FLAGC regs_o_CCR[0]
121			//`define FLAGV regs_o_CCR[1]
122			//`define FLAGZ regs_o_CCR[2]
123			//`define FLAGN regs_o_CCR[3]
124			`define FLAGI regs_o_CCR[5]
125			`define FLAGF regs_o_CCR[6]
126			//`define FLAGE regs_o_CCR[7]
127
128			`define DFLAGC CCR[0]
129			`define DFLAGV CCR[1]
130			`define DFLAGZ CCR[2]
131			`define DFLAGN CCR[3]
132			`// some wires exist only for simulation`
133			`define SIMULATION 1
134			`// Adressing modes`
135			`define NONE 3'h0
136			`define IMMEDIATE 3'h1
137			`define INHERENT 3'h2
138			`define DIRECT 3'h3
139			`define INDEXED 3'h4
140			`define EXTENDED 3'h5
141			`define REL8 3'h6
142			`define REL16 3'h7
143
144			`// Address size`
145
146			`// memory transfer size, read or written, used for addresses`
147			`define MSZ_0 2'h0
148			`define MSZ_8 2'h1
149			`define MSZ_16 2'h2
150			`// Data transfer size, to save to register, used for data from memory and to save results to memory/registers`
151			`define DSZ_0 2'h0
152			`define DSZ_8 2'h1
153			`define DSZ_16 2'h2
154
155			`define OP_NONE 3'h0
156			`define OP_PUSH 3'h1
157			`define OP_PULL 3'h2
158			`define OP_RTS 3'h3
159			`define OP_JSR 3'h4
160			`define OP_ST 3'h5
161			`define OP_LD 3'h6
162			`define OP_LEA 3'h7
163
164			`/* alu decoder right path modifier */`
165			`define MOD_DEFAULT 2'h0
166			`define MOD_ONE 2'h1
167			`define MOD_ZERO 2'h2
168			`define MOD_MINUS1 2'h3
169
170			`define MEMDEST_PC 2'h0
171			`define MEMDEST_MH 2'h1
172			`define MEMDEST_AH 2'h2
173			`define MEMDEST_I16 2'h3

Browse

Tools

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [defs.v] - Blame information for rev 6