Subversion Repositories 6809_6309_compatible_core

$date

        Sun Jun 22 08:16:49 2014

$end

$version

        Icarus Verilog

$end

$timescale

        1ns

$end

$scope module tb $end

$var wire 16 ! addr_o [15:0] $end

$var wire 8 " data_o_o [7:0] $end

$var wire 1 # we $end

$var wire 1 $ oe $end

$var wire 8 % data_o [7:0] $end

$var wire 8 & data_i [7:0] $end

$var wire 16 ' addr [15:0] $end

$var reg 1 ( clk $end

$var reg 1 ) reset $end

$scope module cpu $end

$var wire 1 ( cpu_clk $end

$var wire 1 * cpu_firq_n $end

$var wire 1 + cpu_irq_n $end

$var wire 1 , cpu_nmi_n $end

$var wire 1 ) cpu_reset $end

$var wire 6 - cpu_state_o [5:0] $end

$var wire 1 . debug_clk $end

$var wire 1 / debug_data_o $end

$var wire 1 0 k_firq_req $end

$var wire 1 1 k_irq_req $end

$var wire 1 2 k_nmi_req $end

$var wire 1 3 k_reset $end

$var wire 16 4 regs_o_su [15:0] $end

$var wire 16 5 regs_o_right_path_data [15:0] $end

$var wire 16 6 regs_o_pc [15:0] $end

$var wire 16 7 regs_o_left_path_data [15:0] $end

$var wire 16 8 regs_o_eamem_addr [15:0] $end

$var wire 8 9 regs_o_dp [7:0] $end

$var wire 8 : regs_o_CCR [7:0] $end

$var wire 1 ; dec_o_write_flags $end

$var wire 1 < dec_o_wdest $end

$var wire 1 = dec_o_use_s $end

$var wire 1 > dec_o_source_size $end

$var wire 2 ? dec_o_right_path_mod [1:0] $end

$var wire 4 @ dec_o_right_path_addr [3:0] $end

$var wire 3 A dec_o_p1_optype [2:0] $end

$var wire 3 B dec_o_p1_mode [2:0] $end

$var wire 4 C dec_o_left_path_addr [3:0] $end

$var wire 1 D dec_o_ea_wpost $end

$var wire 1 E dec_o_ea_ofs8 $end

$var wire 1 F dec_o_ea_ofs16 $end

$var wire 1 G dec_o_ea_ofs0 $end

$var wire 1 H dec_o_ea_indirect $end

$var wire 4 I dec_o_dest_reg_addr [3:0] $end

$var wire 1 J dec_o_cond_taken $end

$var wire 1 K dec_o_alu_size $end

$var wire 5 L dec_o_alu_opcode [4:0] $end

$var wire 1 # cpu_we_o $end

$var wire 1 $ cpu_oe_o $end

$var wire 8 M cpu_data_o [7:0] $end

$var wire 8 N cpu_data_i [7:0] $end

$var wire 16 O cpu_addr_o [15:0] $end

$var wire 16 P alu_o_result [15:0] $end

$var wire 8 Q alu_o_CCR [7:0] $end

$var reg 4 R datamux_o_alu_in_left_path_addr [3:0] $end

$var reg 16 S datamux_o_alu_in_left_path_data [15:0] $end

$var reg 16 T datamux_o_alu_in_right_path_data [15:0] $end

$var reg 16 U datamux_o_dest [15:0] $end

$var reg 4 V datamux_o_dest_reg_addr [3:0] $end

$var reg 1 W k_clear_e $end

$var reg 16 X k_cpu_addr [15:0] $end

$var reg 8 Y k_cpu_data_o [7:0] $end

$var reg 1 $ k_cpu_oe $end

$var reg 1 # k_cpu_we $end

$var reg 1 Z k_dec_su $end

$var reg 8 [ k_eahi [7:0] $end

$var reg 8 \ k_ealo [7:0] $end

$var reg 1 ] k_forced_mem_size $end

$var reg 1 ^ k_inc_pc $end

$var reg 1 _ k_inc_su $end

$var reg 8 ` k_ind_ea [7:0] $end

$var reg 2 a k_mem_dest [1:0] $end

$var reg 8 b k_memhi [7:0] $end

$var reg 8 c k_memlo [7:0] $end

$var reg 1 d k_mul_cnt $end

$var reg 16 e k_new_pc [15:0] $end

$var reg 8 f k_ofshi [7:0] $end

$var reg 8 g k_ofslo [7:0] $end

$var reg 8 h k_opcode [7:0] $end

$var reg 1 i k_p2_valid $end

$var reg 1 j k_p3_valid $end

$var reg 8 k k_postbyte [7:0] $end

$var reg 4 l k_pp_active_reg [3:0] $end

$var reg 8 m k_pp_regs [7:0] $end

$var reg 3 n k_reg_firq [2:0] $end

$var reg 3 o k_reg_irq [2:0] $end

$var reg 3 p k_reg_nmi [2:0] $end

$var reg 1 q k_set_e $end

$var reg 1 r k_write_dest $end

$var reg 1 s k_write_exg $end

$var reg 1 t k_write_pc $end

$var reg 1 u k_write_post_incdec $end

$var reg 1 v k_write_tfr $end

$var reg 6 w next_mem_state [5:0] $end

$var reg 6 x next_push_state [5:0] $end

$var reg 6 y next_state [5:0] $end

$var reg 6 z state [5:0] $end

$scope module alu $end

$var wire 16 { a_in [15:0] $end

$var wire 16 | b_in [15:0] $end

$var wire 1 ( clk_in $end

$var wire 1 K sz_in $end

$var wire 8 } q8_out [7:0] $end

$var wire 16 ~ q16_out [15:0] $end

$var wire 5 !" opcode_in [4:0] $end

$var wire 8 "" ccr8_out [7:0] $end

$var wire 4 #" ccr16_out [3:0] $end

$var wire 8 $" CCR [7:0] $end

$var reg 8 %" CCRo [7:0] $end

$var reg 16 &" q_out [15:0] $end

$var reg 16 '" ra_in [15:0] $end

$var reg 16 (" rb_in [15:0] $end

$var reg 5 )" rop_in [4:0] $end

$scope module alu16 $end

$var wire 16 *" a_in [15:0] $end

$var wire 16 +" b_in [15:0] $end

$var wire 1 ( clk_in $end

$var wire 5 ," opcode_in [4:0] $end

$var wire 1 -" z_in $end

$var wire 1 ." v_in $end

$var wire 16 /" q16_mul [15:0] $end

$var wire 1 0" n_in $end

$var wire 1 1" c_in $end

$var wire 1 2" arith_v $end

$var wire 16 3" arith_q [15:0] $end

$var wire 1 4" arith_c $end

$var wire 8 5" CCR [7:0] $end

$var reg 4 6" CCRo [3:0] $end

$var reg 1 7" c16 $end

$var reg 1 8" n16 $end

$var reg 16 9" q16 [15:0] $end

$var reg 16 :" q_out [15:0] $end

$var reg 1 ;" reg_n_in $end

$var reg 1 <" reg_z_in $end

$var reg 16 =" regq16 [15:0] $end

$var reg 1 >" v16 $end

$var reg 1 ?" z16 $end

$scope module a16 $end

$var wire 16 @" a_in [15:0] $end

$var wire 16 A" b_in [15:0] $end

$var wire 1 1" carry_in $end

$var wire 2 B" opcode_in [1:0] $end

$var reg 1 4" carry_out $end

$var reg 1 2" overflow_out $end

$var reg 16 C" q_out [15:0] $end

$upscope $end

$scope module mulu $end

$var wire 8 D" a [7:0] $end

$var wire 8 E" b [7:0] $end

$var wire 1 ( clk_in $end

$var wire 16 F" q [15:0] $end

$var reg 16 G" pipe0 [15:0] $end

$var reg 16 H" pipe1 [15:0] $end

$upscope $end

$upscope $end

$scope module alu8 $end

$var wire 8 I" a_in [7:0] $end

$var wire 8 J" b_in [7:0] $end

$var wire 1 ( clk_in $end

$var wire 1 K" cneg8_r $end

$var wire 8 L" com8_r [7:0] $end

$var wire 8 M" com8_w [7:0] $end

$var wire 8 N" neg8_r [7:0] $end

$var wire 5 O" opcode_in [4:0] $end

$var wire 1 P" vcom8_r $end

$var wire 1 Q" vneg8_r $end

$var wire 1 R" z_in $end

$var wire 1 S" v_in $end

$var wire 1 T" shift_v $end

$var wire 8 U" shift_q [7:0] $end

$var wire 1 V" shift_c $end

$var wire 8 W" neg8_w [7:0] $end

$var wire 1 X" n_in $end

$var wire 8 Y" logic_q [7:0] $end

$var wire 1 Z" h_in $end

$var wire 1 [" daa_lnm9 $end

$var wire 4 \" daa8l_r [3:0] $end

$var wire 4 ]" daa8h_r [3:0] $end

$var wire 1 ^" cdaa8_r $end

$var wire 1 _" ccom8_r $end

$var wire 1 `" c_in $end

$var wire 1 a" arith_v $end

$var wire 8 b" arith_q [7:0] $end

$var wire 1 c" arith_h $end

$var wire 1 d" arith_c $end

$var wire 8 e" CCR [7:0] $end

$var reg 8 f" CCRo [7:0] $end

$var reg 1 g" c8 $end

$var reg 1 h" h8 $end

$var reg 8 i" q8 [7:0] $end

$var reg 8 j" q_out [7:0] $end

$var reg 8 k" regq8 [7:0] $end

$var reg 1 l" v8 $end

$scope module a8 $end

$var wire 8 m" a_in [7:0] $end

$var wire 8 n" b_in [7:0] $end

$var wire 1 `" carry_in $end

$var wire 1 Z" half_c_in $end

$var wire 2 o" opcode_in [1:0] $end

$var wire 1 p" carry $end

$var reg 1 d" carry_out $end

$var reg 1 c" half_c_out $end

$var reg 1 a" overflow_out $end

$var reg 8 q" q_out [7:0] $end

$upscope $end

$scope module l8 $end

$var wire 8 r" a_in [7:0] $end

$var wire 8 s" b_in [7:0] $end

$var wire 2 t" opcode_in [1:0] $end

$var reg 8 u" q_out [7:0] $end

$upscope $end

$scope module s8 $end

$var wire 8 v" a_in [7:0] $end

$var wire 8 w" b_in [7:0] $end

$var wire 1 `" carry_in $end

$var wire 3 x" opcode_in [2:0] $end

$var wire 1 S" overflow_in $end

$var wire 1 V" carry_out $end

$var reg 1 T" overflow_out $end

$var reg 8 y" q_out [7:0] $end

$upscope $end

$upscope $end

$upscope $end

$scope module dec_alu $end

$var wire 8 z" opcode [7:0] $end

$var wire 1 i page2_valid $end

$var wire 1 j page3_valid $end

$var wire 8 {" postbyte0 [7:0] $end

$var wire 1 ; dest_flags $end

$var reg 5 |" alu_opcode [4:0] $end

$var reg 2 }" dec_alu_right_path_mod [1:0] $end

$upscope $end

$scope module dec_ea $end

$var wire 8 ~" eapostbyte [7:0] $end

$var wire 1 H isind $end

$var reg 1 G noofs $end

$var reg 1 F ofs16 $end

$var reg 1 E ofs8 $end

$var reg 1 D write_post $end

$upscope $end

$scope module dec_op $end

$var wire 8 !# opcode [7:0] $end

$var wire 1 i page2_valid $end

$var wire 1 j page3_valid $end

$var wire 8 "# postbyte0 [7:0] $end

$var wire 4 ## oplo [3:0] $end

$var reg 3 $# mode [2:0] $end

$var reg 3 %# optype [2:0] $end

$var reg 1 &# size $end

$var reg 1 = use_s $end

$upscope $end

$scope module dec_regs $end

$var wire 1 ( cpu_clk $end

$var wire 8 '# opcode [7:0] $end

$var wire 1 i page2_valid $end

$var wire 1 j page3_valid $end

$var wire 8 (# postbyte0 [7:0] $end

$var wire 1 < write_dest $end

$var wire 1 > source_size $end

$var wire 1 K result_size $end

$var reg 4 )# dest_reg [3:0] $end

$var reg 4 *# dest_reg_o [3:0] $end

$var reg 4 +# path_left_addr [3:0] $end

$var reg 4 ,# path_left_addr_o [3:0] $end

$var reg 4 -# path_right_addr [3:0] $end

$var reg 4 .# path_right_addr_o [3:0] $end

$upscope $end

$scope module regs $end

$var wire 8 /# CCR_in [7:0] $end

$var wire 1 W clear_e $end

$var wire 1 ( clk_in $end

$var wire 16 0# data_w [15:0] $end

$var wire 1 Z dec_su $end

$var wire 16 1# eamem_addr_o [15:0] $end

$var wire 8 2# eapostbyte [7:0] $end

$var wire 4 3# exg_dest_r [3:0] $end

$var wire 1 ^ inc_pc $end

$var wire 1 _ inc_su $end

$var wire 16 4# new_pc [15:0] $end

$var wire 16 5# offset16 [15:0] $end

$var wire 4 6# path_left_addr [3:0] $end

$var wire 4 7# path_right_addr [3:0] $end

$var wire 8 8# reg_dp [7:0] $end

$var wire 16 9# reg_pc [15:0] $end

$var wire 1 q set_e $end

$var wire 1 = use_s $end

$var wire 1 s write_exg $end

$var wire 1 :# write_flags $end

$var wire 1 t write_pc $end

$var wire 1 u write_post $end

$var wire 1 r write_reg $end

$var wire 4 ;# write_reg_addr [3:0] $end

$var wire 1 v write_tfr $end

$var wire 4 <# right_reg [3:0] $end

$var wire 16 =# right [15:0] $end

$var wire 16 ># reg_su [15:0] $end

$var wire 16 ?# pc_plus_1 [15:0] $end

$var wire 16 @# left [15:0] $end

$var wire 16 A# eamem_addr [15:0] $end

$var wire 16 B# ea_reg_post [15:0] $end

$var wire 8 C# CCR_o [7:0] $end

$var reg 8 D# ACCA [7:0] $end

$var reg 8 E# ACCB [7:0] $end

$var reg 8 F# DP [7:0] $end

$var reg 16 G# IX [15:0] $end

$var reg 16 H# IY [15:0] $end

$var reg 16 I# PC [15:0] $end

$var reg 16 J# SS [15:0] $end

$var reg 16 K# SU [15:0] $end

$var reg 1 L# cff $end

$var reg 1 M# eflag $end

$var reg 1 N# fflag $end

$var reg 1 O# hflag $end

$var reg 1 P# intff $end

$var reg 1 Q# nff $end

$var reg 16 R# path_left_data [15:0] $end

$var reg 16 S# path_right_data [15:0] $end

$var reg 1 T# vff $end

$var reg 1 U# zff $end

$scope module ea $end

$var wire 8 V# acca [7:0] $end

$var wire 8 W# accb [7:0] $end

$var wire 16 X# ea_reg_post_o [15:0] $end

$var wire 16 Y# eamem_addr_o [15:0] $end

$var wire 8 Z# eapostbyte [7:0] $end

$var wire 16 [# ix [15:0] $end

$var wire 16 \# iy [15:0] $end

$var wire 16 ]# offset16 [15:0] $end

$var wire 16 ^# pc [15:0] $end

$var wire 16 _# s [15:0] $end

$var wire 16 `# u [15:0] $end

$var reg 16 a# ea_reg [15:0] $end

$var reg 16 b# ea_reg_post [15:0] $end

$var reg 16 c# eamem_addr [15:0] $end

$upscope $end

$upscope $end

$scope module test_cond $end

$var wire 8 d# CCR [7:0] $end

$var wire 8 e# opcode [7:0] $end

$var wire 1 i page2_valid $end

$var wire 8 f# postbyte0 [7:0] $end

$var wire 8 g# op [7:0] $end

$var reg 1 J cond_taken $end

$upscope $end

$upscope $end

$scope module imem $end

$var wire 16 h# addr [15:0] $end

$var wire 8 i# data_i [7:0] $end

$var wire 8 j# data_o [7:0] $end

$var wire 8 k# mem0 [7:0] $end

$var wire 8 l# mem1 [7:0] $end

$var wire 8 m# mem2 [7:0] $end

$var wire 8 n# mem3 [7:0] $end

$var wire 1 o# oe $end

$var wire 1 p# we $end

$var reg 8 q# latecheddata [7:0] $end

$var integer 32 r# i [31:0] $end

$upscope $end

$upscope $end

$enddefinitions $end

#0

$dumpvars

b10000000000000000 r#

bx q#

1p#

1o#

b10100101 n#

b10100101 m#

b10100101 l#

b10100101 k#

bx j#

bx i#

bx h#

bx g#

bx f#

bx e#

b0 d#

bx c#

bx b#

bx a#

b111000000000 `#

b111100000000 _#

b1111111111111110 ^#

bx ]#

b1010010101011010 \#

b0 [#

bx Z#

bx Y#

bx X#

bx W#

bx V#

0U#

0T#

b1111111111111111 S#

b1111111111111111 R#

0Q#

0P#

0O#

0N#

0M#

0L#

b111000000000 K#

b111100000000 J#

b1111111111111110 I#

b1010010101011010 H#

b0 G#

b0 F#

bx E#

bx D#

b0 C#

bx B#

bx A#

b0 @#

b1111111111111111 ?#

b111x00000000 >#

b1111111111111111 =#

bx <#

bx ;#

0:#

b1111111111111110 9#

b0 8#

bx 7#

bx 6#

bx 5#

bx 4#

bx 3#

bx 2#

bx 1#

b0 0#

b100 /#

bx .#

bx -#

bx ,#

bx +#

bx *#

bx )#

bx (#

bx '#

x&#

bx %#

bx $#

bx ##

bx "#

bx !#

bx ~"

bx }"

bx |"

bx {"

bx z"

bx y"

bx x"

bx w"

bx v"

bx u"

bx t"

bx s"

bx r"

bx q"

0p"

bx o"

bx n"

bx m"

0l"

bx k"

b0 j"

b0 i"

0h"

0g"

b100 f"

b0 e"

xd"

xc"

bx b"

xa"

0`"

x_"

x^"

bx ]"

bx \"

x["

0Z"

bx Y"

0X"

bx W"

xV"

bx U"

0T"

0S"

0R"

xQ"

0P"

bx O"

bx N"

bx M"

bx L"

xK"

bx J"

bx I"

bx H"

bx G"

bx F"

bx E"

bx D"

bx C"

bx B"

bx A"

bx @"

1?"

0>"

bx ="

x<"

x;"

b0 :"

b0 9"

08"

07"

b100 6"

b0 5"

x4"

bx 3"

x2"

01"

00"

bx /"

0."

0-"

bx ,"

bx +"

bx *"

bx )"

bx ("

bx '"

b0 &"

b100 %"

b0 $"

b100 #"

b100 ""

bx !"

b0 ~

b0 }

bx |

b1111111111111111 {

b0 z

bx y

bx x

bx w

0v

xu

xt

0s

0r

xq

b0 p

b0 o

b0 n

bx m

bx l

bx k

xj

xi

bx h

bx g

bx f

bx e

0d

bx c

bx b

b0 a

bx `

x_

x^

x]

bx \

bx [

xZ

bx Y

bx X

xW

bx V

b0 U

bx T

b1111111111111111 S

bx R

b100 Q

b0 P

bx O

bx N

bx M

bx L

xK

0J

bx I

xH

xG

xF

xE

xD

bx C

bx B

bx A

bx @

bx ?

x>

x=

x<

x;

b0 :

b0 9

bx 8

b1111111111111111 7

b1111111111111110 6

b1111111111111111 5

b111x00000000 4

13

02

01

00

0/

z.

b0 -

z,

z+

z*

1)

0(

bx '

bx &

bx %

0$

0#

bx "

bx !

$end

#5

1^"

0Q"

0_"

1K"

b101 \"

b101 ]"

1V"

b0 L"

b0 M"

1["

b11111111 U"

b11111111 y"

b1 N"

b1 W"

b11111111 I"

b11111111 m"

b11111111 r"

b11111111 v"

b11111111 D"

b0 k"

0<"

0;"

b0 ="

b1111111111111111 '"

b1111111111111111 *"

b1111111111111111 @"

1(

#10

0(

#15

1(

#20

0(

#25

1(

#30

0(

#35

1(

#40

0(

#45

1(

#46

03

0)

#50

0(

#55

b1000 w

b11111110 \

b11111111 [

b110110 -

b110110 z

1]

b0z n

b0z o

b0z p

1(

#60

0(

#65

0]

b110111 -

b110111 z

b1111111111111110 !

b1111111111111110 '

b1111111111111110 O

b1111111111111110 X

b1111111111111110 h#

b0zz n

b0zz o

b0zz p

1(

#70

0(

#75

b10000 &

b10000 N

b10000 j#

b10000 q#

x0

x1

x2

b111000 -

b111000 z

0o#

1$

bz n

bz o

bz p

1(

#80

0(

#85

b10000xxxxxxxx e

b10000xxxxxxxx 4#

b1111111111111111 !

b1111111111111111 '

b1111111111111111 O

b1111111111111111 X

b1111111111111111 h#

b111010 -

b111010 z

b10000 b

1o#

0$

1(

#90

0(

#95

b0 &

b0 N

b0 j#

b0 q#

b111011 -

b111011 z

0o#

1$

1(

#100

0(

#105

b101 <#

b1000000000000 e

b1000000000000 4#

b1000 -

b1000 z

1t

b0 c

1o#

0$

1(

#110

0(

#115

bx <#

bx1xxxxxxxxxxx1 =#

bx 8

bx 1#

bx A#

bx Y#

bx c#

b1000000000001 ?#

b1000000000000 6

b1000000000000 9#

b1000000000000 I#

b1000000000000 ^#

b1 a

b1001 -

b1001 z

0t

1(

#120

0(

#125

b1000000000000 !

b1000000000000 '

b1000000000000 O

b1000000000000 X

b1000000000000 h#

b1010 -

b1010 z

1(

#130

0(

#135

b10001110 &

b10001110 N

b10001110 j#

b10001110 q#

b1111111111111111 T

b1111111111111111 |

b11111110 e

b11111110 4#

b111100000000 4

b111100000000 >#

b101 <#

b0 ?

b0 }"

1;

b1001 L

b1001 !"

b1001 |"

0&#

b11 B

b11 $#

1=

b110 A

b110 %#

x<

bx )#

b1101 -#

x>

bx +#

b1000000000001 =#

b1011 -

b1011 z

b1111 l

0j

0i

1^

0o#

1$

1(

#140

0(

#145

b0 @#

b0 U

b0 0#

1K

02"

04"

b0 3"

b0 C"

b100 Q

b100 %"

b100 /#

b0 P

b0 &"

b11111110 U"

b11111110 y"

0c"

0a"

0d"

b0 b"

b0 q"

b11111111 Y"

b11111111 u"

b100 #"

b100 6"

b0 ~

b0 :"

bx <#

1?"

08"

b1 B"

b100 ""

b100 f"

b0 }

b0 j"

0h"

0l"

0g"

b0 i"

b1 t"

b1 o"

b1 x"

b11111111 J"

b11111111 n"

b11111111 s"

b11111111 w"

b11111111 E"

0>"

07"

b0 9"

bx 8

bx 1#

bx A#

bx Y#

bx c#

b1000000000000 e

b1000000000000 4#