Subversion Repositories 6809_6309_compatible_core

$date

        Wed Jul 02 12:37:24 2014

$end

$version

        Icarus Verilog

$end

$timescale

        1ns

$end

$scope module tb $end

$var wire 16 ! addr [15:0] $end

$var wire 16 " addr_o [15:0] $end

$var wire 8 # data_i [7:0] $end

$var wire 8 $ data_o [7:0] $end

$var wire 8 % data_o_o [7:0] $end

$var wire 1 & oe $end

$var wire 1 ' we $end

$var reg 1 ( clk $end

$var reg 1 ) reset $end

$scope module cpu $end

$var wire 8 * alu_o_CCR [7:0] $end

$var wire 16 + alu_o_result [15:0] $end

$var wire 16 , cpu_addr_o [15:0] $end

$var wire 1 - cpu_clk $end

$var wire 8 . cpu_data_i [7:0] $end

$var wire 8 / cpu_data_o [7:0] $end

$var wire 1 0 cpu_firq_n $end

$var wire 1 1 cpu_irq_n $end

$var wire 1 2 cpu_nmi_n $end

$var wire 1 & cpu_oe_o $end

$var wire 1 3 cpu_reset $end

$var wire 6 4 cpu_state_o [5:0] $end

$var wire 1 ' cpu_we_o $end

$var wire 1 5 debug_clk $end

$var wire 1 6 debug_data_o $end

$var wire 4 7 dec_lo_dest_reg_addr [3:0] $end

$var wire 4 8 dec_lo_left_path_addr [3:0] $end

$var wire 4 9 dec_lo_right_path_addr [3:0] $end

$var wire 5 : dec_o_alu_opcode [4:0] $end

$var wire 1 ; dec_o_alu_size $end

$var wire 1 < dec_o_cond_taken $end

$var wire 4 = dec_o_dest_reg_addr [3:0] $end

$var wire 1 > dec_o_ea_indirect $end

$var wire 1 ? dec_o_ea_ofs0 $end

$var wire 1 @ dec_o_ea_ofs16 $end

$var wire 1 A dec_o_ea_ofs8 $end

$var wire 1 B dec_o_ea_wpost $end

$var wire 4 C dec_o_left_path_addr [3:0] $end

$var wire 3 D dec_o_p1_mode [2:0] $end

$var wire 3 E dec_o_p1_optype [2:0] $end

$var wire 4 F dec_o_right_path_addr [3:0] $end

$var wire 2 G dec_o_right_path_mod [1:0] $end

$var wire 1 H dec_o_source_size $end

$var wire 1 I dec_o_use_s $end

$var wire 1 J dec_o_wdest $end

$var wire 1 K dec_o_write_flags $end

$var wire 1 L k_firq_req $end

$var wire 1 M k_irq_req $end

$var wire 1 N k_nmi_req $end

$var wire 1 O k_reset $end

$var wire 8 P regs_o_CCR [7:0] $end

$var wire 8 Q regs_o_dp [7:0] $end

$var wire 16 R regs_o_eamem_addr [15:0] $end

$var wire 16 S regs_o_left_path_data [15:0] $end

$var wire 16 T regs_o_pc [15:0] $end

$var wire 16 U regs_o_right_path_data [15:0] $end

$var wire 16 V regs_o_su [15:0] $end

$var reg 4 W datamux_o_alu_in_left_path_addr [3:0] $end

$var reg 16 X datamux_o_alu_in_left_path_data [15:0] $end

$var reg 16 Y datamux_o_alu_in_right_path_data [15:0] $end

$var reg 16 Z datamux_o_dest [15:0] $end

$var reg 4 [ datamux_o_dest_reg_addr [3:0] $end

$var reg 1 \ k_clear_e $end

$var reg 16 ] k_cpu_addr [15:0] $end

$var reg 8 ^ k_cpu_data_o [7:0] $end

$var reg 1 _ k_cpu_oe $end

$var reg 1 ` k_cpu_we $end

$var reg 1 a k_dec_su $end

$var reg 8 b k_eahi [7:0] $end

$var reg 8 c k_ealo [7:0] $end

$var reg 1 d k_forced_mem_size $end

$var reg 1 e k_inc_pc $end

$var reg 1 f k_inc_su $end

$var reg 8 g k_ind_ea [7:0] $end

$var reg 2 h k_mem_dest [1:0] $end

$var reg 8 i k_memhi [7:0] $end

$var reg 8 j k_memlo [7:0] $end

$var reg 1 k k_mul_cnt $end

$var reg 16 l k_new_pc [15:0] $end

$var reg 8 m k_ofshi [7:0] $end

$var reg 8 n k_ofslo [7:0] $end

$var reg 8 o k_opcode [7:0] $end

$var reg 1 p k_p2_valid $end

$var reg 1 q k_p3_valid $end

$var reg 8 r k_postbyte [7:0] $end

$var reg 4 s k_pp_active_reg [3:0] $end

$var reg 8 t k_pp_regs [7:0] $end

$var reg 3 u k_reg_firq [2:0] $end

$var reg 3 v k_reg_irq [2:0] $end

$var reg 3 w k_reg_nmi [2:0] $end

$var reg 1 x k_set_e $end

$var reg 1 y k_write_dest $end

$var reg 1 z k_write_exg $end

$var reg 1 { k_write_pc $end

$var reg 1 | k_write_post_incdec $end

$var reg 1 } k_write_tfr $end

$var reg 6 ~ next_mem_state [5:0] $end

$var reg 6 !" next_push_state [5:0] $end

$var reg 6 "" next_state [5:0] $end

$var reg 6 #" state [5:0] $end

$scope module alu $end

$var wire 8 $" CCR [7:0] $end

$var wire 16 %" a_in [15:0] $end

$var wire 16 &" b_in [15:0] $end

$var wire 4 '" ccr16_out [3:0] $end

$var wire 8 (" ccr8_out [7:0] $end

$var wire 1 - clk_in $end

$var wire 5 )" opcode_in [4:0] $end

$var wire 16 *" q16_out [15:0] $end

$var wire 8 +" q8_out [7:0] $end

$var wire 1 ; sz_in $end

$var reg 8 ," CCRo [7:0] $end

$var reg 16 -" q_out [15:0] $end

$var reg 16 ." ra_in [15:0] $end

$var reg 16 /" rb_in [15:0] $end

$var reg 5 0" rop_in [4:0] $end

$scope module alu8 $end

$var wire 8 1" CCR [7:0] $end

$var wire 8 2" a_in [7:0] $end

$var wire 1 3" arith_c $end

$var wire 1 4" arith_h $end

$var wire 8 5" arith_q [7:0] $end

$var wire 1 6" arith_v $end

$var wire 8 7" b_in [7:0] $end

$var wire 1 8" c_in $end

$var wire 1 9" ccom8_r $end

$var wire 1 :" cdaa8_r $end

$var wire 1 - clk_in $end

$var wire 1 ;" cneg8_r $end

$var wire 8 <" com8_r [7:0] $end

$var wire 8 =" com8_w [7:0] $end

$var wire 4 >" daa8h_r [3:0] $end

$var wire 4 ?" daa8l_r [3:0] $end

$var wire 1 @" daa_lnm9 $end

$var wire 1 A" h_in $end

$var wire 8 B" logic_q [7:0] $end

$var wire 1 C" n_in $end

$var wire 8 D" neg8_r [7:0] $end

$var wire 8 E" neg8_w [7:0] $end

$var wire 5 F" opcode_in [4:0] $end

$var wire 1 G" shift_c $end

$var wire 8 H" shift_q [7:0] $end

$var wire 1 I" shift_v $end

$var wire 1 J" v_in $end

$var wire 1 K" vcom8_r $end

$var wire 1 L" vneg8_r $end

$var wire 1 M" z_in $end

$var reg 8 N" CCRo [7:0] $end

$var reg 1 O" c8 $end

$var reg 1 P" h8 $end

$var reg 8 Q" q8 [7:0] $end

$var reg 8 R" q_out [7:0] $end

$var reg 8 S" regq8 [7:0] $end

$var reg 1 T" v8 $end

$scope module l8 $end

$var wire 8 U" a_in [7:0] $end

$var wire 8 V" b_in [7:0] $end

$var wire 2 W" opcode_in [1:0] $end

$var reg 8 X" q_out [7:0] $end

$upscope $end

$scope module a8 $end

$var wire 8 Y" a_in [7:0] $end

$var wire 8 Z" b_in [7:0] $end

$var wire 1 [" carry $end

$var wire 1 8" carry_in $end

$var wire 1 A" half_c_in $end

$var wire 2 \" opcode_in [1:0] $end

$var reg 1 ]" carry_out $end

$var reg 1 ^" half_c_out $end

$var reg 1 _" overflow_out $end

$var reg 8 `" q_out [7:0] $end

$upscope $end

$scope module s8 $end

$var wire 8 a" a_in [7:0] $end

$var wire 8 b" b_in [7:0] $end

$var wire 1 8" carry_in $end

$var wire 1 G" carry_out $end

$var wire 3 c" opcode_in [2:0] $end

$var wire 1 J" overflow_in $end

$var reg 1 d" overflow_out $end

$var reg 8 e" q_out [7:0] $end

$upscope $end

$upscope $end

$scope module alu16 $end

$var wire 8 f" CCR [7:0] $end

$var wire 16 g" a_in [15:0] $end

$var wire 1 h" arith_c $end

$var wire 16 i" arith_q [15:0] $end

$var wire 1 j" arith_v $end

$var wire 16 k" b_in [15:0] $end

$var wire 1 l" c_in $end

$var wire 1 - clk_in $end

$var wire 1 m" n_in $end

$var wire 5 n" opcode_in [4:0] $end

$var wire 16 o" q16_mul [15:0] $end

$var wire 1 p" v_in $end

$var wire 1 q" z_in $end

$var reg 4 r" CCRo [3:0] $end

$var reg 1 s" c16 $end

$var reg 1 t" n16 $end

$var reg 16 u" q16 [15:0] $end

$var reg 16 v" q_out [15:0] $end

$var reg 1 w" reg_n_in $end

$var reg 1 x" reg_z_in $end

$var reg 16 y" regq16 [15:0] $end

$var reg 1 z" v16 $end

$var reg 1 {" z16 $end

$scope module mulu $end

$var wire 8 |" a [7:0] $end

$var wire 8 }" b [7:0] $end

$var wire 1 - clk_in $end

$var wire 16 ~" q [15:0] $end

$var reg 16 !# pipe0 [15:0] $end

$var reg 16 "# pipe1 [15:0] $end

$upscope $end

$scope module a16 $end

$var wire 16 ## a_in [15:0] $end

$var wire 16 $# b_in [15:0] $end

$var wire 1 l" carry_in $end

$var wire 2 %# opcode_in [1:0] $end

$var reg 1 &# carry_out $end

$var reg 1 '# overflow_out $end

$var reg 16 (# q_out [15:0] $end

$upscope $end

$upscope $end

$upscope $end

$scope module regs $end

$var wire 8 )# CCR_in [7:0] $end

$var wire 8 *# CCR_o [7:0] $end

$var wire 1 +# clear_e $end

$var wire 1 - clk_in $end

$var wire 16 ,# data_w [15:0] $end

$var wire 1 -# dec_su $end

$var wire 16 .# ea_reg_post [15:0] $end

$var wire 16 /# eamem_addr [15:0] $end

$var wire 16 0# eamem_addr_o [15:0] $end

$var wire 8 1# eapostbyte [7:0] $end

$var wire 4 2# exg_dest_r [3:0] $end

$var wire 1 3# inc_pc $end

$var wire 1 4# inc_su $end

$var wire 16 5# left [15:0] $end

$var wire 16 6# new_pc [15:0] $end

$var wire 16 7# offset16 [15:0] $end

$var wire 4 8# path_left_addr [3:0] $end

$var wire 4 9# path_right_addr [3:0] $end

$var wire 16 :# pc_plus_1 [15:0] $end

$var wire 8 ;# reg_dp [7:0] $end

$var wire 16 <# reg_pc [15:0] $end

$var wire 16 =# reg_su [15:0] $end

$var wire 16 ># right [15:0] $end

$var wire 4 ?# right_reg [3:0] $end

$var wire 1 @# set_e $end

$var wire 1 I use_s $end

$var wire 1 A# write_exg $end

$var wire 1 B# write_flags $end

$var wire 1 C# write_pc $end

$var wire 1 D# write_post $end

$var wire 1 E# write_reg $end

$var wire 4 F# write_reg_addr [3:0] $end

$var wire 1 G# write_tfr $end

$var reg 8 H# ACCA [7:0] $end

$var reg 8 I# ACCB [7:0] $end

$var reg 8 J# DP [7:0] $end

$var reg 16 K# IX [15:0] $end

$var reg 16 L# IY [15:0] $end

$var reg 16 M# PC [15:0] $end

$var reg 16 N# SS [15:0] $end

$var reg 16 O# SU [15:0] $end

$var reg 1 P# cff $end

$var reg 1 Q# eflag $end

$var reg 1 R# fflag $end

$var reg 1 S# hflag $end

$var reg 1 T# intff $end

$var reg 1 U# nff $end

$var reg 16 V# path_left_data [15:0] $end

$var reg 16 W# path_right_data [15:0] $end

$var reg 1 X# vff $end

$var reg 1 Y# zff $end

$scope module ea $end

$var wire 8 Z# acca [7:0] $end

$var wire 8 [# accb [7:0] $end

$var wire 16 \# ea_reg_post_o [15:0] $end

$var wire 16 ]# eamem_addr_o [15:0] $end

$var wire 8 ^# eapostbyte [7:0] $end

$var wire 16 _# ix [15:0] $end

$var wire 16 `# iy [15:0] $end

$var wire 16 a# offset16 [15:0] $end

$var wire 16 b# pc [15:0] $end

$var wire 16 c# s [15:0] $end

$var wire 16 d# u [15:0] $end

$var reg 16 e# ea_reg [15:0] $end

$var reg 16 f# ea_reg_post [15:0] $end

$var reg 16 g# eamem_addr [15:0] $end

$upscope $end

$upscope $end

$scope module dec_regs $end

$var wire 1 - cpu_clk $end

$var wire 4 h# dest_reg_o [3:0] $end

$var wire 8 i# opcode [7:0] $end

$var wire 1 j# page2_valid $end

$var wire 1 k# page3_valid $end

$var wire 4 l# path_left_addr_o [3:0] $end

$var wire 4 m# path_right_addr_o [3:0] $end

$var wire 8 n# postbyte0 [7:0] $end

$var wire 1 ; result_size $end

$var wire 1 H source_size $end

$var wire 1 J write_dest $end

$var reg 4 o# dest_reg [3:0] $end

$var reg 4 p# dest_reg_lo [3:0] $end

$var reg 4 q# path_left_addr [3:0] $end

$var reg 4 r# path_left_addr_lo [3:0] $end

$var reg 4 s# path_right_addr [3:0] $end

$var reg 4 t# path_right_addr_lo [3:0] $end

$upscope $end

$scope module dec_op $end

$var wire 8 u# opcode [7:0] $end

$var wire 4 v# oplo [3:0] $end

$var wire 1 j# page2_valid $end

$var wire 1 k# page3_valid $end

$var wire 8 w# postbyte0 [7:0] $end

$var reg 3 x# mode [2:0] $end

$var reg 3 y# optype [2:0] $end

$var reg 1 z# size $end

$var reg 1 {# use_s $end

$upscope $end

$scope module dec_ea $end

$var wire 8 |# eapostbyte [7:0] $end

$var wire 1 > isind $end

$var reg 1 }# noofs $end

$var reg 1 ~# ofs16 $end

$var reg 1 !$ ofs8 $end

$var reg 1 "$ write_post $end

$upscope $end

$scope module dec_alu $end

$var wire 1 K dest_flags $end

$var wire 8 #$ opcode [7:0] $end

$var wire 1 j# page2_valid $end

$var wire 1 k# page3_valid $end

$var wire 8 $$ postbyte0 [7:0] $end

$var reg 5 %$ alu_opcode [4:0] $end

$var reg 2 &$ dec_alu_right_path_mod [1:0] $end

$upscope $end

$scope module test_cond $end

$var wire 8 '$ CCR [7:0] $end

$var wire 8 ($ op [7:0] $end

$var wire 8 )$ opcode [7:0] $end

$var wire 1 j# page2_valid $end

$var wire 8 *$ postbyte0 [7:0] $end

$var reg 1 +$ cond_taken $end

$upscope $end

$upscope $end

$scope module imem $end

$var wire 16 ,$ addr [15:0] $end

$var wire 8 -$ data_i [7:0] $end

$var wire 8 .$ data_o [7:0] $end

$var wire 8 /$ mem0 [7:0] $end

$var wire 8 0$ mem1 [7:0] $end

$var wire 8 1$ mem2 [7:0] $end

$var wire 8 2$ mem3 [7:0] $end

$var wire 1 3$ oe $end

$var wire 1 4$ we $end

$var integer 32 5$ i [31:0] $end

$var reg 8 6$ latecheddata [7:0] $end

$upscope $end

$upscope $end

$enddefinitions $end

#0

$dumpvars

bx 6$

b10000000000000000 5$

14$

13$

b10100101 2$

b10100101 1$

b10100101 0$

b10100101 /$

bx .$

bx -$

bx ,$

0+$

bx *$

bx )$

bx ($

b0 '$

bx &$

bx %$

bx $$

bx #$

x"$

x!$

x~#

x}#

bx |#

1{#

0z#

b110 y#

b11 x#

bx w#

bx v#

bx u#

bx t#

bx s#

bx r#

bx q#

bx p#

bx o#

bx n#

bx m#

bx l#

xk#

xj#

bx i#

bx h#

bx g#

bx f#

bx e#

b111000000000 d#

b111100000000 c#

b1111111111111110 b#

bx a#

b1010010101011010 `#

b0 _#

bx ^#

bx ]#

bx \#

bx [#

bx Z#

0Y#

0X#

b1111111111111111 W#

b1111111111111111 V#

0U#

0T#

0S#

0R#

0Q#

0P#

b111000000000 O#

b111100000000 N#

b1111111111111110 M#

b1010010101011010 L#

b0 K#

b0 J#

bx I#

bx H#

0G#

bx F#

0E#

xD#

xC#

0B#

0A#

x@#

bx ?#

b1111111111111111 >#

b111100000000 =#

b1111111111111110 <#

b0 ;#

b1111111111111111 :#

bx 9#

bx 8#

bx 7#

bx 6#

b0 5#

x4#

x3#

bx 2#

bx 1#

bx 0#

bx /#

bx .#

x-#

b0 ,#

x+#

b0 *#

b100 )#

bx (#

x'#

x&#

bx %#

bx $#

bx ##

bx "#

bx !#

bx ~"

bx }"

bx |"

1{"

0z"

bx y"

xx"

xw"

b0 v"

b0 u"

0t"

0s"

b100 r"

0q"

0p"

bx o"

bx n"

0m"

0l"

bx k"

xj"

bx i"

xh"

bx g"

b0 f"

bx e"

0d"

bx c"

bx b"

bx a"

bx `"

x_"

x^"

x]"

bx \"

0["

bx Z"

bx Y"

bx X"

bx W"

bx V"

bx U"

0T"

bx S"

b0 R"

b0 Q"

0P"

0O"

b100 N"

0M"

xL"

0K"

0J"

0I"

bx H"

xG"

bx F"

bx E"

bx D"

0C"

bx B"

0A"

x@"

bx ?"

bx >"

bx ="

bx <"

x;"

x:"

x9"

08"

bx 7"

x6"

bx 5"

x4"

x3"

bx 2"

b0 1"

bx 0"

bx /"

bx ."

b0 -"

b100 ,"

b0 +"

b0 *"

bx )"

b100 ("

b100 '"

bx &"

b1111111111111111 %"

b0 $"

b0 #"

bx ""

bx !"

bx ~

0}

x|

x{

0z

0y

xx

b0 w

b0 v

b0 u

bx t

bx s

bx r

xq

xp

bx o

bx n

bx m

bx l

0k

bx j

bx i

b0 h

bx g

xf

xe

xd

bx c

bx b

xa

0`

0_

bx ^

bx ]

x\

bx [

b0 Z

bx Y

b1111111111111111 X

bx W

b111100000000 V

b1111111111111111 U

b1111111111111110 T

b1111111111111111 S

bx R

b0 Q

b0 P

1O

0N

0M

0L

xK

xJ

1I

xH

bx G

bx F

b110 E

b11 D

bx C

xB

xA

x@

x?

x>

bx =

0<

x;

bx :

bx 9

bx 8

bx 7

06

z5

b0 4

13

z2

z1

z0

bx /

bx .

0-

bx ,

b0 +

b100 *

1)

0(

0'

0&

bx %

bx $

bx #

bx "

bx !

$end

#5

1:"

0L"

09"

1;"

b101 ?"

b101 >"

1G"

b0 <"

b0 ="

b11111111 e"

b11111111 H"

1@"

b11111111 2"

b11111111 U"

b11111111 Y"

b11111111 a"

b1 E"

b1 D"

b11111111 |"

b0 S"

0x"

0w"

b0 y"

b1111111111111111 ."

b1111111111111111 g"

b1111111111111111 ##

1(

1-

#10

0(

0-

#15

1(

1-

#20

0(

0-

#25

1(

1-

#30

0(

0-

#35

1(

1-

#40

0(

0-

#45

1(

1-

#46

0)

0O

03

#50

0(

0-

#55

b1000 ~

b11111110 c

b11111111 b

b110110 #"

b110110 4

1d

b0z u

b0z v

b0z w

1(

1-

#60

0(

0-

#65

0d

b110111 #"

b110111 4

b1111111111111110 ]

b1111111111111110 !

b1111111111111110 ,

b1111111111111110 ,$

b1111111111111110 "

b0zz u

b0zz v

b0zz w

1(

1-

#70

0(

0-

#75

b10000 6$

b10000 #

b10000 .

b10000 .$

xL

xM

xN

b111000 #"

b111000 4

1_

03$

1&

bz u

bz v

bz w

1(

1-

#80

0(

0-

#85

b10000xxxxxxxx l

b10000xxxxxxxx 6#

b1111111111111111 ]

b1111111111111111 !

b1111111111111111 ,

b1111111111111111 ,$

b1111111111111111 "

b111010 #"

b111010 4

b10000 i

0_

13$

0&

1(

1-

#90

0(

0-

#95

b0 6$

b0 #

b0 .

b0 .$

b111011 #"

b111011 4

1_

03$

1&

1(

1-

#100

0(

0-

#105

b101 ?#

b1000000000000 l

b1000000000000 6#

b1000 #"

b1000 4

1{

1C#

b0 j

0_

13$

0&

1(

1-

#110

0(

0-

#115

bx ?#

bx1xxxxxxxxxxx1 >#

bx g#

bx /#

bx ]#

bx R

bx 0#

b11111110 l

b11111110 6#

b1000000000000 M#

b1000000000001 :#

b1000000000000 b#

b1000000000000 T

b1000000000000 <#

b1 h

b1001 #"

b1001 4

0{

0C#

1(

1-

#120

0(

0-

#125

b1000000000000 ]

b1000000000000 !

b1000000000000 ,

b1000000000000 ,$

b1000000000000 "

b1010 #"

b1010 4

1(

1-

#130

0(

0-

#135

b10001110 6$

b10001110 #

b10001110 .

b10001110 .$

b1111111111111111 Y

b1111111111111111 &"

b11111110 l

b11111110 6#

b101 ?#

b0 &$

b0 G

b1001 %$

1K

b1001 :

b1001 )"

b11 x#

b11 D

b110 y#

b110 E

bx o#

xJ

bx =

bx h#

b1101 s#

b1101 F

b1101 m#

bx q#

xH

bx C

bx l#

b1000000000001 >#

b1011 #"

b1011 4

b1111 s

0q

0k#

0p

0j#

1e

13#

1_

03$

1&

1(

1-

#140

0(

0-

#145

b0 5#

b0 Z

b0 ,#

b100 ,"

b100 *