Subversion Repositories 6809_6309_compatible_core

$date

        Mon Dec 30 08:33:05 2013

$end

$version

        Icarus Verilog

$end

$timescale

        1ns

$end

$scope module tb $end

$var wire 16 ! addr_o [15:0] $end

$var wire 8 " data_o_o [7:0] $end

$var wire 1 # we $end

$var wire 1 $ oe $end

$var wire 8 % data_o [7:0] $end

$var wire 8 & data_i [7:0] $end

$var wire 16 ' addr [15:0] $end

$var reg 1 ( clk $end

$var reg 1 ) reset $end

$scope module cpu $end

$var wire 1 ( cpu_clk $end

$var wire 1 * cpu_firq_n $end

$var wire 1 + cpu_irq_n $end

$var wire 1 , cpu_nmi_n $end

$var wire 1 ) cpu_reset $end

$var wire 6 - cpu_state_o [5:0] $end

$var wire 1 . k_clk $end

$var wire 1 / k_firq_req $end

$var wire 1 0 k_irq_req $end

$var wire 1 1 k_nmi_req $end

$var wire 1 2 k_reset $end

$var wire 16 3 regs_o_su [15:0] $end

$var wire 16 4 regs_o_right_path_data [15:0] $end

$var wire 16 5 regs_o_pc [15:0] $end

$var wire 16 6 regs_o_left_path_data [15:0] $end

$var wire 16 7 regs_o_eamem_addr [15:0] $end

$var wire 8 8 regs_o_dp [7:0] $end

$var wire 8 9 regs_o_CCR [7:0] $end

$var wire 1 : dec_o_write_flags $end

$var wire 1 ; dec_o_wdest $end

$var wire 1 < dec_o_use_s $end

$var wire 1 = dec_o_source_size $end

$var wire 2 > dec_o_right_path_mod [1:0] $end

$var wire 4 ? dec_o_right_path_addr [3:0] $end

$var wire 3 @ dec_o_p1_optype [2:0] $end

$var wire 3 A dec_o_p1_mode [2:0] $end

$var wire 4 B dec_o_left_path_addr [3:0] $end

$var wire 1 C dec_o_ea_wpost $end

$var wire 1 D dec_o_ea_ofs8 $end

$var wire 1 E dec_o_ea_ofs16 $end

$var wire 1 F dec_o_ea_ofs0 $end

$var wire 1 G dec_o_ea_indirect $end

$var wire 4 H dec_o_dest_reg_addr [3:0] $end

$var wire 1 I dec_o_cond_taken $end

$var wire 1 J dec_o_alu_size $end

$var wire 5 K dec_o_alu_opcode [4:0] $end

$var wire 1 # cpu_we_o $end

$var wire 1 $ cpu_oe_o $end

$var wire 8 L cpu_data_o [7:0] $end

$var wire 8 M cpu_data_i [7:0] $end

$var wire 16 N cpu_addr_o [15:0] $end

$var wire 16 O alu_o_result [15:0] $end

$var wire 8 P alu_o_CCR [7:0] $end

$var reg 4 Q datamux_o_alu_in_left_path_addr [3:0] $end

$var reg 16 R datamux_o_alu_in_left_path_data [15:0] $end

$var reg 16 S datamux_o_alu_in_right_path_data [15:0] $end

$var reg 16 T datamux_o_dest [15:0] $end

$var reg 4 U datamux_o_dest_reg_addr [3:0] $end

$var reg 1 V k_clear_e $end

$var reg 16 W k_cpu_addr [15:0] $end

$var reg 8 X k_cpu_data_o [7:0] $end

$var reg 1 $ k_cpu_oe $end

$var reg 1 # k_cpu_we $end

$var reg 1 Y k_dec_su $end

$var reg 8 Z k_eahi [7:0] $end

$var reg 8 [ k_ealo [7:0] $end

$var reg 1 \ k_forced_mem_size $end

$var reg 1 ] k_inc_pc $end

$var reg 1 ^ k_inc_su $end

$var reg 8 _ k_ind_ea [7:0] $end

$var reg 2 ` k_mem_dest [1:0] $end

$var reg 8 a k_memhi [7:0] $end

$var reg 8 b k_memlo [7:0] $end

$var reg 16 c k_new_pc [15:0] $end

$var reg 8 d k_ofshi [7:0] $end

$var reg 8 e k_ofslo [7:0] $end

$var reg 8 f k_opcode [7:0] $end

$var reg 1 g k_p2_valid $end

$var reg 1 h k_p3_valid $end

$var reg 8 i k_postbyte0 [7:0] $end

$var reg 8 j k_pp_active_reg [7:0] $end

$var reg 8 k k_pp_regs [7:0] $end

$var reg 3 l k_reg_firq [2:0] $end

$var reg 3 m k_reg_irq [2:0] $end

$var reg 3 n k_reg_nmi [2:0] $end

$var reg 1 o k_set_e $end

$var reg 1 p k_write_dest $end

$var reg 1 q k_write_pc $end

$var reg 1 r k_write_post_incdec $end

$var reg 6 s next_mem_state [5:0] $end

$var reg 6 t next_push_state [5:0] $end

$var reg 6 u next_state [5:0] $end

$var reg 6 v state [5:0] $end

$scope module alu $end

$var wire 16 w a_in [15:0] $end

$var wire 16 x and16_r [15:0] $end

$var wire 16 y and16_w [15:0] $end

$var wire 8 z and8_r [7:0] $end

$var wire 8 { and8_w [7:0] $end

$var wire 16 | asr16_r [15:0] $end

$var wire 8 } asr8_r [7:0] $end

$var wire 16 ~ b_in [15:0] $end

$var wire 1 !" cand16_r $end

$var wire 1 "" cand8_r $end

$var wire 1 . clk $end

$var wire 1 #" cneg16_r $end

$var wire 1 $" cneg8_r $end

$var wire 16 %" com16_r [15:0] $end

$var wire 16 &" com16_w [15:0] $end

$var wire 8 '" com8_r [7:0] $end

$var wire 8 (" com8_w [7:0] $end

$var wire 16 )" eor16_r [15:0] $end

$var wire 16 *" eor16_w [15:0] $end

$var wire 8 +" eor8_r [7:0] $end

$var wire 8 ," eor8_w [7:0] $end

$var wire 16 -" mul16_r [15:0] $end

$var wire 16 ." neg16_r [15:0] $end

$var wire 8 /" neg8_r [7:0] $end

$var wire 16 0" or16_r [15:0] $end

$var wire 16 1" or16_w [15:0] $end

$var wire 8 2" or8_r [7:0] $end

$var wire 8 3" or8_w [7:0] $end

$var wire 16 4" rol16_r [15:0] $end

$var wire 8 5" rol8_r [7:0] $end

$var wire 16 6" ror16_r [15:0] $end

$var wire 8 7" ror8_r [7:0] $end

$var wire 16 8" shl16_r [15:0] $end

$var wire 8 9" shl8_r [7:0] $end

$var wire 16 :" shr16_r [15:0] $end

$var wire 8 ;" shr8_r [7:0] $end

$var wire 1 <" vadc16_r $end

$var wire 1 =" vadc8_r $end

$var wire 1 >" vadd16_r $end

$var wire 1 ?" vadd8_r $end

$var wire 1 @" vand16_r $end

$var wire 1 A" vand8_r $end

$var wire 1 B" vasr16_r $end

$var wire 1 C" vasr8_r $end

$var wire 1 D" vcom16_r $end

$var wire 1 E" vcom8_r $end

$var wire 1 F" vneg16_r $end

$var wire 1 G" vneg8_r $end

$var wire 1 H" vrol16_r $end

$var wire 1 I" vrol8_r $end

$var wire 1 J" vror16_r $end

$var wire 1 K" vror8_r $end

$var wire 1 L" vsbc16_r $end

$var wire 1 M" vsbc8_r $end

$var wire 1 N" vshl16_r $end

$var wire 1 O" vshl8_r $end

$var wire 1 P" vshr16_r $end

$var wire 1 Q" vshr8_r $end

$var wire 1 R" vsub16_r $end

$var wire 1 S" vsub8_r $end

$var wire 1 T" z_in $end

$var wire 1 U" v_in $end

$var wire 1 J sz_in $end

$var wire 8 V" sub8_w [7:0] $end

$var wire 8 W" sub8_r [7:0] $end

$var wire 16 X" sub16_w [15:0] $end

$var wire 16 Y" sub16_r [15:0] $end

$var wire 8 Z" shr8_w [7:0] $end

$var wire 16 [" shr16_w [15:0] $end

$var wire 8 \" shl8_w [7:0] $end

$var wire 16 ]" shl16_w [15:0] $end

$var wire 8 ^" sbc8_w [7:0] $end

$var wire 8 _" sbc8_r [7:0] $end

$var wire 16 `" sbc16_w [15:0] $end

$var wire 16 a" sbc16_r [15:0] $end

$var wire 8 b" ror8_w [7:0] $end

$var wire 16 c" ror16_w [15:0] $end

$var wire 8 d" rol8_w [7:0] $end

$var wire 16 e" rol16_w [15:0] $end

$var wire 5 f" opcode_in [4:0] $end

$var wire 8 g" neg8_w [7:0] $end

$var wire 16 h" neg16_w [15:0] $end

$var wire 1 i" n_in $end

$var wire 16 j" mul16_w [15:0] $end

$var wire 1 k" h_in $end

$var wire 1 l" daa_lnm9 $end

$var wire 4 m" daa8l_r [3:0] $end

$var wire 4 n" daa8h_r [3:0] $end

$var wire 1 o" csub8_w $end

$var wire 1 p" csub8_r $end

$var wire 1 q" csub16_w $end

$var wire 1 r" csub16_r $end

$var wire 1 s" cshr8_r $end

$var wire 1 t" cshr16_r $end

$var wire 1 u" cshl8_r $end

$var wire 1 v" cshl16_r $end

$var wire 1 w" csbc8_w $end

$var wire 1 x" csbc8_r $end

$var wire 1 y" csbc16_w $end

$var wire 1 z" csbc16_r $end

$var wire 1 {" cror8_r $end

$var wire 1 |" cror16_r $end

$var wire 1 }" crol8_r $end

$var wire 1 ~" crol16_r $end

$var wire 1 !# cmul16_r $end

$var wire 1 "# cdaa8_r $end

$var wire 1 ## ccom8_r $end

$var wire 1 $# ccom16_r $end

$var wire 1 %# casr8_r $end

$var wire 1 &# casr16_r $end

$var wire 1 '# cadd8_w $end

$var wire 1 (# cadd8_r $end

$var wire 1 )# cadd16_w $end

$var wire 1 *# cadd16_r $end

$var wire 1 +# cadc8_w $end

$var wire 1 ,# cadc8_r $end

$var wire 1 -# cadc16_w $end

$var wire 1 .# cadc16_r $end

$var wire 1 /# c_in $end

$var wire 8 0# asr8_w [7:0] $end

$var wire 16 1# asr16_w [15:0] $end

$var wire 8 2# add8_w [7:0] $end

$var wire 8 3# add8_r [7:0] $end

$var wire 16 4# add16_w [15:0] $end

$var wire 16 5# add16_r [15:0] $end

$var wire 8 6# adc8_w [7:0] $end

$var wire 8 7# adc8_r [7:0] $end

$var wire 16 8# adc16_w [15:0] $end

$var wire 16 9# adc16_r [15:0] $end

$var wire 8 :# CCR [7:0] $end

$var reg 8 ;# CCRo [7:0] $end

$var reg 1 <# c16 $end

$var reg 1 =# c8 $end

$var reg 1 ># h8 $end

$var reg 1 ?# n16 $end

$var reg 1 @# n8 $end

$var reg 16 A# q16 [15:0] $end

$var reg 8 B# q8 [7:0] $end

$var reg 16 C# q_out [15:0] $end

$var reg 1 D# reg_n_in $end

$var reg 1 E# reg_z_in $end

$var reg 16 F# regq16 [15:0] $end

$var reg 8 G# regq8 [7:0] $end

$var reg 1 H# v16 $end

$var reg 1 I# v8 $end

$var reg 1 J# z16 $end

$var reg 1 K# z8 $end

$upscope $end

$scope module dec_alu $end

$var wire 8 L# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 M# postbyte0 [7:0] $end

$var wire 1 : dest_flags $end

$var reg 5 N# alu_opcode [4:0] $end

$var reg 2 O# dec_alu_right_path_mod [1:0] $end

$upscope $end

$scope module dec_ea $end

$var wire 8 P# eapostbyte [7:0] $end

$var wire 1 G isind $end

$var reg 1 F noofs $end

$var reg 1 E ofs16 $end

$var reg 1 D ofs8 $end

$var reg 1 C write_post $end

$upscope $end

$scope module dec_op $end

$var wire 8 Q# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 R# postbyte0 [7:0] $end

$var wire 4 S# oplo [3:0] $end

$var reg 3 T# mode [2:0] $end

$var reg 3 U# optype [2:0] $end

$var reg 1 V# size $end

$var reg 1 < use_s $end

$upscope $end

$scope module dec_regs $end

$var wire 8 W# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 X# postbyte0 [7:0] $end

$var wire 1 ; write_dest $end

$var wire 1 = source_size $end

$var wire 1 J result_size $end

$var reg 4 Y# dest_reg [3:0] $end

$var reg 4 Z# path_left_addr [3:0] $end

$var reg 4 [# path_right_addr [3:0] $end

$upscope $end

$scope module regs $end

$var wire 8 \# CCR_in [7:0] $end

$var wire 1 V clear_e $end

$var wire 1 . clk_in $end

$var wire 16 ]# data_w [15:0] $end

$var wire 1 Y dec_su $end

$var wire 8 ^# eapostbyte [7:0] $end

$var wire 1 ] inc_pc $end

$var wire 1 ^ inc_su $end

$var wire 16 _# new_pc [15:0] $end

$var wire 16 `# offset16 [15:0] $end

$var wire 4 a# path_left_addr [3:0] $end

$var wire 4 b# path_right_addr [3:0] $end

$var wire 8 c# reg_dp [7:0] $end

$var wire 16 d# reg_pc [15:0] $end

$var wire 1 o set_e $end

$var wire 1 < use_s $end

$var wire 1 e# write_flags $end

$var wire 1 q write_pc $end

$var wire 1 r write_post $end

$var wire 1 p write_reg $end

$var wire 4 f# write_reg_addr [3:0] $end

$var wire 16 g# reg_su [15:0] $end

$var wire 8 h# CCR_o [7:0] $end

$var reg 8 i# ACCA [7:0] $end

$var reg 8 j# ACCB [7:0] $end

$var reg 8 k# DP [7:0] $end

$var reg 16 l# IX [15:0] $end

$var reg 16 m# IY [15:0] $end

$var reg 16 n# PC [15:0] $end

$var reg 16 o# SS [15:0] $end

$var reg 16 p# SU [15:0] $end

$var reg 1 q# cff $end

$var reg 16 r# ea_reg [15:0] $end

$var reg 16 s# ea_reg_post [15:0] $end

$var reg 16 t# eamem_addr [15:0] $end

$var reg 1 u# eflag $end

$var reg 1 v# fflag $end

$var reg 1 w# hflag $end

$var reg 1 x# intff $end

$var reg 1 y# nff $end

$var reg 16 z# path_left_data [15:0] $end

$var reg 16 {# path_right_data [15:0] $end

$var reg 1 |# vff $end

$var reg 1 }# zff $end

$upscope $end

$scope module test_cond $end

$var wire 8 ~# CCR [7:0] $end

$var wire 8 !$ opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 8 "$ postbyte0 [7:0] $end

$var wire 8 #$ op [7:0] $end

$var reg 1 I cond_taken $end

$upscope $end

$upscope $end

$scope module imem $end

$var wire 16 $$ addr [15:0] $end

$var wire 8 %$ data_i [7:0] $end

$var wire 8 &$ data_o [7:0] $end

$var wire 8 '$ mem0 [7:0] $end

$var wire 8 ($ mem1 [7:0] $end

$var wire 8 )$ mem2 [7:0] $end

$var wire 8 *$ mem3 [7:0] $end

$var wire 1 +$ oe $end

$var wire 1 ,$ we $end

$var reg 8 -$ latecheddata [7:0] $end

$upscope $end

$upscope $end

$enddefinitions $end

#0

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