Subversion Repositories 6809_6309_compatible_core

$date

        Tue Dec 31 08:40:54 2013

$end

$version

        Icarus Verilog

$end

$timescale

        1ns

$end

$scope module tb $end

$var wire 16 ! addr_o [15:0] $end

$var wire 8 " data_o_o [7:0] $end

$var wire 1 # we $end

$var wire 1 $ oe $end

$var wire 8 % data_o [7:0] $end

$var wire 8 & data_i [7:0] $end

$var wire 16 ' addr [15:0] $end

$var reg 1 ( clk $end

$var reg 1 ) reset $end

$scope module cpu $end

$var wire 1 ( cpu_clk $end

$var wire 1 * cpu_firq_n $end

$var wire 1 + cpu_irq_n $end

$var wire 1 , cpu_nmi_n $end

$var wire 1 ) cpu_reset $end

$var wire 6 - cpu_state_o [5:0] $end

$var wire 1 . k_clk $end

$var wire 1 / k_firq_req $end

$var wire 1 0 k_irq_req $end

$var wire 1 1 k_nmi_req $end

$var wire 1 2 k_reset $end

$var wire 16 3 regs_o_su [15:0] $end

$var wire 16 4 regs_o_right_path_data [15:0] $end

$var wire 16 5 regs_o_pc [15:0] $end

$var wire 16 6 regs_o_left_path_data [15:0] $end

$var wire 16 7 regs_o_eamem_addr [15:0] $end

$var wire 8 8 regs_o_dp [7:0] $end

$var wire 8 9 regs_o_CCR [7:0] $end

$var wire 1 : dec_o_write_flags $end

$var wire 1 ; dec_o_wdest $end

$var wire 1 < dec_o_use_s $end

$var wire 1 = dec_o_source_size $end

$var wire 2 > dec_o_right_path_mod [1:0] $end

$var wire 4 ? dec_o_right_path_addr [3:0] $end

$var wire 3 @ dec_o_p1_optype [2:0] $end

$var wire 3 A dec_o_p1_mode [2:0] $end

$var wire 4 B dec_o_left_path_addr [3:0] $end

$var wire 1 C dec_o_ea_wpost $end

$var wire 1 D dec_o_ea_ofs8 $end

$var wire 1 E dec_o_ea_ofs16 $end

$var wire 1 F dec_o_ea_ofs0 $end

$var wire 1 G dec_o_ea_indirect $end

$var wire 4 H dec_o_dest_reg_addr [3:0] $end

$var wire 1 I dec_o_cond_taken $end

$var wire 1 J dec_o_alu_size $end

$var wire 5 K dec_o_alu_opcode [4:0] $end

$var wire 1 # cpu_we_o $end

$var wire 1 $ cpu_oe_o $end

$var wire 8 L cpu_data_o [7:0] $end

$var wire 8 M cpu_data_i [7:0] $end

$var wire 16 N cpu_addr_o [15:0] $end

$var wire 16 O alu_o_result [15:0] $end

$var wire 8 P alu_o_CCR [7:0] $end

$var reg 4 Q datamux_o_alu_in_left_path_addr [3:0] $end

$var reg 16 R datamux_o_alu_in_left_path_data [15:0] $end

$var reg 16 S datamux_o_alu_in_right_path_data [15:0] $end

$var reg 16 T datamux_o_dest [15:0] $end

$var reg 4 U datamux_o_dest_reg_addr [3:0] $end

$var reg 1 V k_clear_e $end

$var reg 16 W k_cpu_addr [15:0] $end

$var reg 8 X k_cpu_data_o [7:0] $end

$var reg 1 $ k_cpu_oe $end

$var reg 1 # k_cpu_we $end

$var reg 1 Y k_dec_su $end

$var reg 8 Z k_eahi [7:0] $end

$var reg 8 [ k_ealo [7:0] $end

$var reg 1 \ k_forced_mem_size $end

$var reg 1 ] k_inc_pc $end

$var reg 1 ^ k_inc_su $end

$var reg 8 _ k_ind_ea [7:0] $end

$var reg 2 ` k_mem_dest [1:0] $end

$var reg 8 a k_memhi [7:0] $end

$var reg 8 b k_memlo [7:0] $end

$var reg 16 c k_new_pc [15:0] $end

$var reg 8 d k_ofshi [7:0] $end

$var reg 8 e k_ofslo [7:0] $end

$var reg 8 f k_opcode [7:0] $end

$var reg 1 g k_p2_valid $end

$var reg 1 h k_p3_valid $end

$var reg 8 i k_postbyte [7:0] $end

$var reg 8 j k_pp_active_reg [7:0] $end

$var reg 8 k k_pp_regs [7:0] $end

$var reg 3 l k_reg_firq [2:0] $end

$var reg 3 m k_reg_irq [2:0] $end

$var reg 3 n k_reg_nmi [2:0] $end

$var reg 1 o k_set_e $end

$var reg 1 p k_write_dest $end

$var reg 1 q k_write_exg $end

$var reg 1 r k_write_pc $end

$var reg 1 s k_write_post_incdec $end

$var reg 1 t k_write_tfr $end

$var reg 6 u next_mem_state [5:0] $end

$var reg 6 v next_push_state [5:0] $end

$var reg 6 w next_state [5:0] $end

$var reg 6 x state [5:0] $end

$scope module alu $end

$var wire 16 y a_in [15:0] $end

$var wire 16 z and16_r [15:0] $end

$var wire 16 { and16_w [15:0] $end

$var wire 8 | and8_r [7:0] $end

$var wire 8 } and8_w [7:0] $end

$var wire 16 ~ asr16_r [15:0] $end

$var wire 8 !" asr8_r [7:0] $end

$var wire 16 "" b_in [15:0] $end

$var wire 1 #" cand16_r $end

$var wire 1 $" cand8_r $end

$var wire 1 . clk $end

$var wire 1 %" cneg16_r $end

$var wire 1 &" cneg8_r $end

$var wire 16 '" com16_r [15:0] $end

$var wire 16 (" com16_w [15:0] $end

$var wire 8 )" com8_r [7:0] $end

$var wire 8 *" com8_w [7:0] $end

$var wire 16 +" eor16_r [15:0] $end

$var wire 16 ," eor16_w [15:0] $end

$var wire 8 -" eor8_r [7:0] $end

$var wire 8 ." eor8_w [7:0] $end

$var wire 16 /" mul16_r [15:0] $end

$var wire 16 0" neg16_r [15:0] $end

$var wire 8 1" neg8_r [7:0] $end

$var wire 16 2" or16_r [15:0] $end

$var wire 16 3" or16_w [15:0] $end

$var wire 8 4" or8_r [7:0] $end

$var wire 8 5" or8_w [7:0] $end

$var wire 16 6" rol16_r [15:0] $end

$var wire 8 7" rol8_r [7:0] $end

$var wire 16 8" ror16_r [15:0] $end

$var wire 8 9" ror8_r [7:0] $end

$var wire 16 :" shl16_r [15:0] $end

$var wire 8 ;" shl8_r [7:0] $end

$var wire 16 <" shr16_r [15:0] $end

$var wire 8 =" shr8_r [7:0] $end

$var wire 1 >" vadc16_r $end

$var wire 1 ?" vadc8_r $end

$var wire 1 @" vadd16_r $end

$var wire 1 A" vadd8_r $end

$var wire 1 B" vand16_r $end

$var wire 1 C" vand8_r $end

$var wire 1 D" vasr16_r $end

$var wire 1 E" vasr8_r $end

$var wire 1 F" vcom16_r $end

$var wire 1 G" vcom8_r $end

$var wire 1 H" vneg16_r $end

$var wire 1 I" vneg8_r $end

$var wire 1 J" vrol16_r $end

$var wire 1 K" vrol8_r $end

$var wire 1 L" vror16_r $end

$var wire 1 M" vror8_r $end

$var wire 1 N" vsbc16_r $end

$var wire 1 O" vsbc8_r $end

$var wire 1 P" vshl16_r $end

$var wire 1 Q" vshl8_r $end

$var wire 1 R" vshr16_r $end

$var wire 1 S" vshr8_r $end

$var wire 1 T" vsub16_r $end

$var wire 1 U" vsub8_r $end

$var wire 1 V" z_in $end

$var wire 1 W" v_in $end

$var wire 1 J sz_in $end

$var wire 8 X" sub8_w [7:0] $end

$var wire 8 Y" sub8_r [7:0] $end

$var wire 16 Z" sub16_w [15:0] $end

$var wire 16 [" sub16_r [15:0] $end

$var wire 8 \" shr8_w [7:0] $end

$var wire 16 ]" shr16_w [15:0] $end

$var wire 8 ^" shl8_w [7:0] $end

$var wire 16 _" shl16_w [15:0] $end

$var wire 8 `" sbc8_w [7:0] $end

$var wire 8 a" sbc8_r [7:0] $end

$var wire 16 b" sbc16_w [15:0] $end

$var wire 16 c" sbc16_r [15:0] $end

$var wire 8 d" ror8_w [7:0] $end

$var wire 16 e" ror16_w [15:0] $end

$var wire 8 f" rol8_w [7:0] $end

$var wire 16 g" rol16_w [15:0] $end

$var wire 5 h" opcode_in [4:0] $end

$var wire 8 i" neg8_w [7:0] $end

$var wire 16 j" neg16_w [15:0] $end

$var wire 1 k" n_in $end

$var wire 16 l" mul16_w [15:0] $end

$var wire 1 m" h_in $end

$var wire 1 n" daa_lnm9 $end

$var wire 4 o" daa8l_r [3:0] $end

$var wire 4 p" daa8h_r [3:0] $end

$var wire 1 q" csub8_w $end

$var wire 1 r" csub8_r $end

$var wire 1 s" csub16_w $end

$var wire 1 t" csub16_r $end

$var wire 1 u" cshr8_r $end

$var wire 1 v" cshr16_r $end

$var wire 1 w" cshl8_r $end

$var wire 1 x" cshl16_r $end

$var wire 1 y" csbc8_w $end

$var wire 1 z" csbc8_r $end

$var wire 1 {" csbc16_w $end

$var wire 1 |" csbc16_r $end

$var wire 1 }" cror8_r $end

$var wire 1 ~" cror16_r $end

$var wire 1 !# crol8_r $end

$var wire 1 "# crol16_r $end

$var wire 1 ## cmul16_r $end

$var wire 1 $# cdaa8_r $end

$var wire 1 %# ccom8_r $end

$var wire 1 &# ccom16_r $end

$var wire 1 '# casr8_r $end

$var wire 1 (# casr16_r $end

$var wire 1 )# cadd8_w $end

$var wire 1 *# cadd8_r $end

$var wire 1 +# cadd16_w $end

$var wire 1 ,# cadd16_r $end

$var wire 1 -# cadc8_w $end

$var wire 1 .# cadc8_r $end

$var wire 1 /# cadc16_w $end

$var wire 1 0# cadc16_r $end

$var wire 1 1# c_in $end

$var wire 8 2# asr8_w [7:0] $end

$var wire 16 3# asr16_w [15:0] $end

$var wire 8 4# add8_w [7:0] $end

$var wire 8 5# add8_r [7:0] $end

$var wire 16 6# add16_w [15:0] $end

$var wire 16 7# add16_r [15:0] $end

$var wire 8 8# adc8_w [7:0] $end

$var wire 8 9# adc8_r [7:0] $end

$var wire 16 :# adc16_w [15:0] $end

$var wire 16 ;# adc16_r [15:0] $end

$var wire 8 <# CCR [7:0] $end

$var reg 8 =# CCRo [7:0] $end

$var reg 1 ># c16 $end

$var reg 1 ?# c8 $end

$var reg 1 @# h8 $end

$var reg 1 A# n16 $end

$var reg 1 B# n8 $end

$var reg 16 C# q16 [15:0] $end

$var reg 8 D# q8 [7:0] $end

$var reg 16 E# q_out [15:0] $end

$var reg 1 F# reg_n_in $end

$var reg 1 G# reg_z_in $end

$var reg 16 H# regq16 [15:0] $end

$var reg 8 I# regq8 [7:0] $end

$var reg 1 J# v16 $end

$var reg 1 K# v8 $end

$var reg 1 L# z16 $end

$var reg 1 M# z8 $end

$upscope $end

$scope module dec_alu $end

$var wire 8 N# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 O# postbyte0 [7:0] $end

$var wire 1 : dest_flags $end

$var reg 5 P# alu_opcode [4:0] $end

$var reg 2 Q# dec_alu_right_path_mod [1:0] $end

$upscope $end

$scope module dec_ea $end

$var wire 8 R# eapostbyte [7:0] $end

$var wire 1 G isind $end

$var reg 1 F noofs $end

$var reg 1 E ofs16 $end

$var reg 1 D ofs8 $end

$var reg 1 C write_post $end

$upscope $end

$scope module dec_op $end

$var wire 8 S# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 T# postbyte0 [7:0] $end

$var wire 4 U# oplo [3:0] $end

$var reg 3 V# mode [2:0] $end

$var reg 3 W# optype [2:0] $end

$var reg 1 X# size $end

$var reg 1 < use_s $end

$upscope $end

$scope module dec_regs $end

$var wire 8 Y# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 Z# postbyte0 [7:0] $end

$var wire 1 ; write_dest $end

$var wire 1 = source_size $end

$var wire 1 J result_size $end

$var reg 4 [# dest_reg [3:0] $end

$var reg 4 \# path_left_addr [3:0] $end

$var reg 4 ]# path_right_addr [3:0] $end

$upscope $end

$scope module regs $end

$var wire 8 ^# CCR_in [7:0] $end

$var wire 1 V clear_e $end

$var wire 1 . clk_in $end

$var wire 16 _# data_w [15:0] $end

$var wire 1 Y dec_su $end

$var wire 8 `# eapostbyte [7:0] $end

$var wire 4 a# exg_dest_r [3:0] $end

$var wire 1 ] inc_pc $end

$var wire 1 ^ inc_su $end

$var wire 16 b# new_pc [15:0] $end

$var wire 16 c# offset16 [15:0] $end

$var wire 4 d# path_left_addr [3:0] $end

$var wire 4 e# path_right_addr [3:0] $end

$var wire 8 f# reg_dp [7:0] $end

$var wire 16 g# reg_pc [15:0] $end

$var wire 1 o set_e $end

$var wire 1 < use_s $end

$var wire 1 q write_exg $end

$var wire 1 h# write_flags $end

$var wire 1 r write_pc $end

$var wire 1 s write_post $end

$var wire 1 p write_reg $end

$var wire 4 i# write_reg_addr [3:0] $end

$var wire 1 t write_tfr $end

$var wire 16 j# u_plus_1 [15:0] $end

$var wire 16 k# u_minus_1 [15:0] $end

$var wire 16 l# s_plus_1 [15:0] $end

$var wire 16 m# s_minus_1 [15:0] $end

$var wire 16 n# reg_su [15:0] $end

$var wire 16 o# pc_plus_1 [15:0] $end

$var wire 16 p# new_u [15:0] $end

$var wire 16 q# new_s [15:0] $end

$var wire 16 r# left [15:0] $end

$var wire 8 s# CCR_o [7:0] $end

$var reg 8 t# ACCA [7:0] $end

$var reg 8 u# ACCB [7:0] $end

$var reg 8 v# DP [7:0] $end

$var reg 16 w# IX [15:0] $end

$var reg 16 x# IY [15:0] $end

$var reg 16 y# PC [15:0] $end

$var reg 16 z# SS [15:0] $end

$var reg 16 {# SU [15:0] $end

$var reg 1 |# cff $end

$var reg 16 }# ea_reg [15:0] $end

$var reg 16 ~# ea_reg_post [15:0] $end

$var reg 16 !$ eamem_addr [15:0] $end

$var reg 1 "$ eflag $end

$var reg 1 #$ fflag $end

$var reg 1 $$ hflag $end

$var reg 1 %$ intff $end

$var reg 1 &$ nff $end

$var reg 16 '$ path_left_data [15:0] $end

$var reg 16 ($ path_right_data [15:0] $end

$var reg 1 )$ vff $end

$var reg 1 *$ zff $end

$upscope $end

$scope module test_cond $end

$var wire 8 +$ CCR [7:0] $end

$var wire 8 ,$ opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 8 -$ postbyte0 [7:0] $end

$var wire 8 .$ op [7:0] $end

$var reg 1 I cond_taken $end

$upscope $end

$upscope $end

$scope module imem $end

$var wire 16 /$ addr [15:0] $end

$var wire 8 0$ data_i [7:0] $end

$var wire 8 1$ data_o [7:0] $end

$var wire 8 2$ mem0 [7:0] $end

$var wire 8 3$ mem1 [7:0] $end

$var wire 8 4$ mem2 [7:0] $end

$var wire 8 5$ mem3 [7:0] $end

$var wire 1 6$ oe $end

$var wire 1 7$ we $end

$var reg 8 8$ latecheddata [7:0] $end

$upscope $end

$upscope $end

$enddefinitions $end

#0

$dumpvars

bx 8$

17$

16$

b10001110 5$

b10111011 4$

b10101010 3$

b11001100 2$

bx 1$

bx 0$

bx /$

bx .$

bx -$

bx ,$

b0 +$

0*$

0)$

b1111111111111111 ($

b1111111111111111 '$

0&$

0%$

0$$

0#$

0"$

bx !$

bx ~#

bx }#

0|#

b111000000000 {#

b111100000000 z#

b1111111111111110 y#

b1010010101011010 x#

b0 w#

b0 v#

bx u#

bx t#

b0 s#

bx r#

bx q#

bx p#

b1111111111111111 o#

b111x00000000 n#

b111011111111 m#

b111100000001 l#

b110111111111 k#

b111000000001 j#

bx i#

0h#

b1111111111111110 g#

b0 f#

bx e#

bx d#

bx c#

bx b#

bx a#

bx `#

bx _#

b0xx00 ^#

bx ]#

bx \#

bx [#

bx Z#

bx Y#

xX#

bx W#

bx V#

bx U#

bx T#

bx S#

bx R#

bx Q#

bx P#

bx O#

bx N#

xM#

xL#

0K#

0J#

bx I#

bx H#

xG#

xF#

bx E#

b0 D#

b0 C#

xB#

xA#

0@#

0?#

0>#

b0xx00 =#

b0 <#

bx ;#

bx :#

bx 9#

bx 8#

bx 7#

bx 6#

bx 5#

bx 4#

b1111111111111111 3#

b11111111 2#

01#

x0#

x/#

x.#

x-#

x,#

x+#

x*#

x)#

1(#

1'#

0&#

0%#

1$#

x##

1"#

1!#

1~"

1}"

x|"

x{"

xz"

xy"

1x"

1w"

1v"

1u"

xt"

xs"

xr"

xq"

b101 p"

b101 o"

1n"

0m"

bx l"

0k"

b1 j"

b1 i"

bx h"

b1111111111111110 g"

b11111110 f"

b111111111111111 e"

b1111111 d"

bx c"

bx b"

bx a"

bx `"

b1111111111111110 _"

b11111110 ^"

b111111111111111 ]"

b1111111 \"

bx ["

bx Z"

bx Y"

bx X"

0W"

0V"

xU"

xT"

1S"

1R"

0Q"

0P"

xO"

xN"

1M"

1L"

0K"

0J"

0I"

0H"

0G"

0F"

0E"

0D"

0C"

0B"

xA"

x@"

x?"

x>"

b1111111 ="

b111111111111111 <"

b11111110 ;"

b1111111111111110 :"

b1111111 9"

b111111111111111 8"

b11111110 7"

b1111111111111110 6"

b11111111 5"

b11111111 4"

b1111111111111111 3"

b1111111111111111 2"

b1 1"

b1 0"

bx /"

bx ."

bx -"

bx ,"

bx +"

b0 *"

b0 )"

b0 ("

b0 '"

1&"

1%"

0$"

0#"

bx ""

b11111111 !"

b1111111111111111 ~

bx }

bx |

bx {

bx z

b1111111111111111 y

b0 x

bx w

bx v

bx u

0t

xs

xr

0q

xp

xo

b0 n

b0 m

b0 l

bx k

bx j

bx i

xh

xg

bx f

bx e

bx d

bx c

bx b

bx a

b0 `

bx _

x^

x]

x\

bx [

bx Z

xY

bx X

bx W

xV

bx U

bx T

bx S

b1111111111111111 R

bx Q

b0xx00 P

bx O

bx N

bx M

bx L

bx K

xJ

0I

bx H

xG

xF

xE

xD

xC

bx B

bx A

bx @

bx ?

bx >

x=

x<

x;

x:

b0 9

b0 8

bx 7

b1111111111111111 6

b1111111111111110 5

b1111111111111111 4

b111x00000000 3

12

01

00

0/

0.

b0 -

z,

z+

z*

1)

0(

bx '

bx &

bx %

0$

0#

bx "

bx !

$end

#5

b0 r#

b0 T

b0 _#

b100 P

b100 =#

b100 ^#

b0 O

b0 E#

1L#

0A#

1M#

0B#

0G#

0F#

b0 H#

b0 I#

1.

1(

#10

0.

0(

#15

1.

1(

#20

0.

0(

#25

1.

1(

#30

0.

0(

#35

1.

1(

#40

0.

0(

#45

1.

1(

#46

02

0)

#50

0.

0(

#55

b1000 u

b11111110 [

b11111111 Z

b110110 -

b110110 x

1\

b0z l

b0z m

b0z n

1.

1(

#60

0.

0(

#65

0\

b110111 -

b110111 x

b1111111111111110 !

b1111111111111110 '

b1111111111111110 N

b1111111111111110 W

b1111111111111110 /$

b0zz l

b0zz m

b0zz n

1.

1(

#70

0.

0(

#75

b0 &

b0 M

b0 1$

b0 8$

x/

x0

x1

b111000 -

b111000 x

06$

1$

bz l

bz m

bz n

1.

1(

#80

0.

0(

#85

b0xxxxxxxx c

b0xxxxxxxx b#

b1111111111111111 !

b1111111111111111 '

b1111111111111111 N

b1111111111111111 W

b1111111111111111 /$

b111010 -

b111010 x

b0 a

16$

0$

1.

1(

#90

0.

0(

#95

b111011 -

b111011 x

06$

1$

1.

1(

#100

0.

0(

#105

b0 c

b0 b#

b1000 -

b1000 x

1r

b0 b

16$

0$

1.

1(

#110

0.

0(

#115

bx 7

bx !$

b1 o#

b0 5

b0 g#

b0 y#

b1001 -

b1001 x

0r

1.

1(

#120

0.

0(

#125

b0 !

b0 '

b0 N

b0 W

b0 /$

b1010 -

b1010 x

1.

1(

#130

0.

0(

#135

b11001100 &

b11001100 M

b11001100 1$

b11001100 8$

1]

b1011 -

b1011 x

06$

1$

1.

1(

#140

0.

0(

#145

xH"

xI"

0T"

0N"

x%#

x&"

x&#

bx )"

bx *"

x%"

b0 |

b0 }

bx 4"

bx 5"

xE"

xD"

xS"

xR"

xQ"

xP"

xM"

xL"

xK"

xJ"

bx o"

bx p"

1J

bx '"

bx ("

b0 z

b0 {

bx 2"

bx 3"

bx 1"

bx i"

bx !"

bx 2#

bx ~

bx 3#

b0xxxxxxx ="

b0xxxxxxx \"

b0xxxxxxxxxxxxxxx <"

b0xxxxxxxxxxxxxxx ]"

bx0 7"

bx0 ;"

bx0 ^"