Subversion Repositories 6809_6309_compatible_core

$date

        Sun Jan  5 08:05:53 2014

$end

$version

        Icarus Verilog

$end

$timescale

        1ns

$end

$scope module tb $end

$var wire 16 ! addr_o [15:0] $end

$var wire 8 " data_o_o [7:0] $end

$var wire 1 # we $end

$var wire 1 $ oe $end

$var wire 8 % data_o [7:0] $end

$var wire 8 & data_i [7:0] $end

$var wire 16 ' addr [15:0] $end

$var reg 1 ( clk $end

$var reg 1 ) reset $end

$scope module cpu $end

$var wire 1 ( cpu_clk $end

$var wire 1 * cpu_firq_n $end

$var wire 1 + cpu_irq_n $end

$var wire 1 , cpu_nmi_n $end

$var wire 1 ) cpu_reset $end

$var wire 6 - cpu_state_o [5:0] $end

$var wire 1 . k_firq_req $end

$var wire 1 / k_irq_req $end

$var wire 1 0 k_nmi_req $end

$var wire 1 1 k_reset $end

$var wire 16 2 regs_o_su [15:0] $end

$var wire 16 3 regs_o_right_path_data [15:0] $end

$var wire 16 4 regs_o_pc [15:0] $end

$var wire 16 5 regs_o_left_path_data [15:0] $end

$var wire 16 6 regs_o_eamem_addr [15:0] $end

$var wire 8 7 regs_o_dp [7:0] $end

$var wire 8 8 regs_o_CCR [7:0] $end

$var wire 1 9 dec_o_write_flags $end

$var wire 1 : dec_o_wdest $end

$var wire 1 ; dec_o_use_s $end

$var wire 1 < dec_o_source_size $end

$var wire 2 = dec_o_right_path_mod [1:0] $end

$var wire 4 > dec_o_right_path_addr [3:0] $end

$var wire 3 ? dec_o_p1_optype [2:0] $end

$var wire 3 @ dec_o_p1_mode [2:0] $end

$var wire 4 A dec_o_left_path_addr [3:0] $end

$var wire 1 B dec_o_ea_wpost $end

$var wire 1 C dec_o_ea_ofs8 $end

$var wire 1 D dec_o_ea_ofs16 $end

$var wire 1 E dec_o_ea_ofs0 $end

$var wire 1 F dec_o_ea_indirect $end

$var wire 4 G dec_o_dest_reg_addr [3:0] $end

$var wire 1 H dec_o_cond_taken $end

$var wire 1 I dec_o_alu_size $end

$var wire 5 J dec_o_alu_opcode [4:0] $end

$var wire 1 # cpu_we_o $end

$var wire 1 $ cpu_oe_o $end

$var wire 8 K cpu_data_o [7:0] $end

$var wire 8 L cpu_data_i [7:0] $end

$var wire 16 M cpu_addr_o [15:0] $end

$var wire 16 N alu_o_result [15:0] $end

$var wire 8 O alu_o_CCR [7:0] $end

$var reg 4 P datamux_o_alu_in_left_path_addr [3:0] $end

$var reg 16 Q datamux_o_alu_in_left_path_data [15:0] $end

$var reg 16 R datamux_o_alu_in_right_path_data [15:0] $end

$var reg 16 S datamux_o_dest [15:0] $end

$var reg 4 T datamux_o_dest_reg_addr [3:0] $end

$var reg 1 U k_clear_e $end

$var reg 16 V k_cpu_addr [15:0] $end

$var reg 8 W k_cpu_data_o [7:0] $end

$var reg 1 $ k_cpu_oe $end

$var reg 1 # k_cpu_we $end

$var reg 1 X k_dec_su $end

$var reg 8 Y k_eahi [7:0] $end

$var reg 8 Z k_ealo [7:0] $end

$var reg 1 [ k_forced_mem_size $end

$var reg 1 \ k_inc_pc $end

$var reg 1 ] k_inc_su $end

$var reg 8 ^ k_ind_ea [7:0] $end

$var reg 2 _ k_mem_dest [1:0] $end

$var reg 8 ` k_memhi [7:0] $end

$var reg 8 a k_memlo [7:0] $end

$var reg 1 b k_mul_cnt $end

$var reg 16 c k_new_pc [15:0] $end

$var reg 8 d k_ofshi [7:0] $end

$var reg 8 e k_ofslo [7:0] $end

$var reg 8 f k_opcode [7:0] $end

$var reg 1 g k_p2_valid $end

$var reg 1 h k_p3_valid $end

$var reg 8 i k_postbyte [7:0] $end

$var reg 4 j k_pp_active_reg [3:0] $end

$var reg 8 k k_pp_regs [7:0] $end

$var reg 3 l k_reg_firq [2:0] $end

$var reg 3 m k_reg_irq [2:0] $end

$var reg 3 n k_reg_nmi [2:0] $end

$var reg 1 o k_set_e $end

$var reg 1 p k_write_dest $end

$var reg 1 q k_write_exg $end

$var reg 1 r k_write_pc $end

$var reg 1 s k_write_post_incdec $end

$var reg 1 t k_write_tfr $end

$var reg 6 u next_mem_state [5:0] $end

$var reg 6 v next_push_state [5:0] $end

$var reg 6 w next_state [5:0] $end

$var reg 6 x state [5:0] $end

$scope module alu $end

$var wire 16 y a_in [15:0] $end

$var wire 16 z b_in [15:0] $end

$var wire 1 ( clk_in $end

$var wire 1 I sz_in $end

$var wire 8 { q8_out [7:0] $end

$var wire 16 | q16_out [15:0] $end

$var wire 5 } opcode_in [4:0] $end

$var wire 8 ~ ccr8_out [7:0] $end

$var wire 4 !" ccr16_out [3:0] $end

$var wire 8 "" CCR [7:0] $end

$var reg 8 #" CCRo [7:0] $end

$var reg 16 $" q_out [15:0] $end

$var reg 16 %" ra_in [15:0] $end

$var reg 16 &" rb_in [15:0] $end

$scope module alu16 $end

$var wire 16 '" a_in [15:0] $end

$var wire 16 (" and16_r [15:0] $end

$var wire 16 )" and16_w [15:0] $end

$var wire 16 *" asr16_r [15:0] $end

$var wire 16 +" b_in [15:0] $end

$var wire 1 ," cand16_r $end

$var wire 1 ( clk_in $end

$var wire 1 -" cneg16_r $end

$var wire 16 ." com16_r [15:0] $end

$var wire 16 /" com16_w [15:0] $end

$var wire 16 0" eor16_r [15:0] $end

$var wire 16 1" eor16_w [15:0] $end

$var wire 16 2" neg16_r [15:0] $end

$var wire 16 3" or16_r [15:0] $end

$var wire 16 4" or16_w [15:0] $end

$var wire 16 5" rol16_r [15:0] $end

$var wire 16 6" ror16_r [15:0] $end

$var wire 16 7" shl16_r [15:0] $end

$var wire 16 8" shr16_r [15:0] $end

$var wire 1 9" vadc16_r $end

$var wire 1 :" vadd16_r $end

$var wire 1 ;" vand16_r $end

$var wire 1 <" vasr16_r $end

$var wire 1 =" vcom16_r $end

$var wire 1 >" vneg16_r $end

$var wire 1 ?" vrol16_r $end

$var wire 1 @" vror16_r $end

$var wire 1 A" vsbc16_r $end

$var wire 1 B" vshl16_r $end

$var wire 1 C" vshr16_r $end

$var wire 1 D" vsub16_r $end

$var wire 1 E" z_in $end

$var wire 1 F" v_in $end

$var wire 16 G" sub16_w [15:0] $end

$var wire 16 H" sub16_r [15:0] $end

$var wire 16 I" shr16_w [15:0] $end

$var wire 16 J" shl16_w [15:0] $end

$var wire 16 K" sbc16_w [15:0] $end

$var wire 16 L" sbc16_r [15:0] $end

$var wire 16 M" ror16_w [15:0] $end

$var wire 16 N" rol16_w [15:0] $end

$var wire 5 O" opcode_in [4:0] $end

$var wire 16 P" neg16_w [15:0] $end

$var wire 1 Q" n_in $end

$var wire 16 R" mul16_r [15:0] $end

$var wire 1 S" csub16_w $end

$var wire 1 T" csub16_r $end

$var wire 1 U" cshr16_r $end

$var wire 1 V" cshl16_r $end

$var wire 1 W" csbc16_w $end

$var wire 1 X" csbc16_r $end

$var wire 1 Y" cror16_r $end

$var wire 1 Z" crol16_r $end

$var wire 1 [" cmul16_r $end

$var wire 1 \" ccom16_r $end

$var wire 1 ]" casr16_r $end

$var wire 1 ^" cadd16_w $end

$var wire 1 _" cadd16_r $end

$var wire 1 `" cadc16_w $end

$var wire 1 a" cadc16_r $end

$var wire 1 b" c_in $end

$var wire 16 c" asr16_w [15:0] $end

$var wire 16 d" add16_w [15:0] $end

$var wire 16 e" add16_r [15:0] $end

$var wire 16 f" adc16_w [15:0] $end

$var wire 16 g" adc16_r [15:0] $end

$var wire 8 h" CCR [7:0] $end

$var reg 4 i" CCRo [3:0] $end

$var reg 1 j" c16 $end

$var reg 1 k" n16 $end

$var reg 16 l" q16 [15:0] $end

$var reg 16 m" q_out [15:0] $end

$var reg 1 n" reg_n_in $end

$var reg 1 o" reg_z_in $end

$var reg 16 p" regq16 [15:0] $end

$var reg 1 q" v16 $end

$var reg 1 r" z16 $end

$scope module mulu $end

$var wire 8 s" a [7:0] $end

$var wire 8 t" b [7:0] $end

$var wire 1 ( clk_in $end

$var wire 16 u" q [15:0] $end

$var reg 16 v" pipe0 [15:0] $end

$var reg 16 w" pipe1 [15:0] $end

$upscope $end

$upscope $end

$scope module alu8 $end

$var wire 16 x" a_in [15:0] $end

$var wire 8 y" and8_r [7:0] $end

$var wire 8 z" and8_w [7:0] $end

$var wire 8 {" asr8_r [7:0] $end

$var wire 16 |" b_in [15:0] $end

$var wire 1 }" cand8_r $end

$var wire 1 ( clk_in $end

$var wire 1 ~" cneg8_r $end

$var wire 8 !# com8_r [7:0] $end

$var wire 8 "# com8_w [7:0] $end

$var wire 8 ## eor8_r [7:0] $end

$var wire 8 $# eor8_w [7:0] $end

$var wire 8 %# neg8_r [7:0] $end

$var wire 8 &# or8_r [7:0] $end

$var wire 8 '# or8_w [7:0] $end

$var wire 8 (# rol8_r [7:0] $end

$var wire 8 )# ror8_r [7:0] $end

$var wire 8 *# shl8_r [7:0] $end

$var wire 8 +# shr8_r [7:0] $end

$var wire 1 ,# vadc8_r $end

$var wire 1 -# vadd8_r $end

$var wire 1 .# vand8_r $end

$var wire 1 /# vasr8_r $end

$var wire 1 0# vcom8_r $end

$var wire 1 1# vneg8_r $end

$var wire 1 2# vrol8_r $end

$var wire 1 3# vror8_r $end

$var wire 1 4# vsbc8_r $end

$var wire 1 5# vshl8_r $end

$var wire 1 6# vshr8_r $end

$var wire 1 7# vsub8_r $end

$var wire 1 8# z_in $end

$var wire 1 9# v_in $end

$var wire 8 :# sub8_w [7:0] $end

$var wire 8 ;# sub8_r [7:0] $end

$var wire 8 <# shr8_w [7:0] $end

$var wire 8 =# shl8_w [7:0] $end

$var wire 8 ># sbc8_w [7:0] $end

$var wire 8 ?# sbc8_r [7:0] $end

$var wire 8 @# ror8_w [7:0] $end

$var wire 8 A# rol8_w [7:0] $end

$var wire 5 B# opcode_in [4:0] $end

$var wire 8 C# neg8_w [7:0] $end

$var wire 1 D# n_in $end

$var wire 1 E# h_in $end

$var wire 1 F# daa_lnm9 $end

$var wire 4 G# daa8l_r [3:0] $end

$var wire 4 H# daa8h_r [3:0] $end

$var wire 1 I# csub8_w $end

$var wire 1 J# csub8_r $end

$var wire 1 K# cshr8_r $end

$var wire 1 L# cshl8_r $end

$var wire 1 M# csbc8_w $end

$var wire 1 N# csbc8_r $end

$var wire 1 O# cror8_r $end

$var wire 1 P# crol8_r $end

$var wire 1 Q# cdaa8_r $end

$var wire 1 R# ccom8_r $end

$var wire 1 S# casr8_r $end

$var wire 1 T# cadd8_w $end

$var wire 1 U# cadd8_r $end

$var wire 1 V# cadc8_w $end

$var wire 1 W# cadc8_r $end

$var wire 1 X# c_in $end

$var wire 8 Y# asr8_w [7:0] $end

$var wire 8 Z# add8_w [7:0] $end

$var wire 8 [# add8_r [7:0] $end

$var wire 8 \# adc8_w [7:0] $end

$var wire 8 ]# adc8_r [7:0] $end

$var wire 8 ^# CCR [7:0] $end

$var reg 8 _# CCRo [7:0] $end

$var reg 1 `# c8 $end

$var reg 1 a# h8 $end

$var reg 8 b# q8 [7:0] $end

$var reg 8 c# q_out [7:0] $end

$var reg 8 d# regq8 [7:0] $end

$var reg 1 e# v8 $end

$upscope $end

$upscope $end

$scope module dec_alu $end

$var wire 8 f# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 g# postbyte0 [7:0] $end

$var wire 1 9 dest_flags $end

$var reg 5 h# alu_opcode [4:0] $end

$var reg 2 i# dec_alu_right_path_mod [1:0] $end

$upscope $end

$scope module dec_ea $end

$var wire 8 j# eapostbyte [7:0] $end

$var wire 1 F isind $end

$var reg 1 E noofs $end

$var reg 1 D ofs16 $end

$var reg 1 C ofs8 $end

$var reg 1 B write_post $end

$upscope $end

$scope module dec_op $end

$var wire 8 k# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 l# postbyte0 [7:0] $end

$var wire 4 m# oplo [3:0] $end

$var reg 3 n# mode [2:0] $end

$var reg 3 o# optype [2:0] $end

$var reg 1 p# size $end

$var reg 1 ; use_s $end

$upscope $end

$scope module dec_regs $end

$var wire 8 q# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 r# postbyte0 [7:0] $end

$var wire 1 : write_dest $end

$var wire 1 < source_size $end

$var wire 1 I result_size $end

$var reg 4 s# dest_reg [3:0] $end

$var reg 4 t# path_left_addr [3:0] $end

$var reg 4 u# path_right_addr [3:0] $end

$upscope $end

$scope module regs $end

$var wire 8 v# CCR_in [7:0] $end

$var wire 1 U clear_e $end

$var wire 1 ( clk_in $end

$var wire 16 w# data_w [15:0] $end

$var wire 1 X dec_su $end

$var wire 8 x# eapostbyte [7:0] $end

$var wire 4 y# exg_dest_r [3:0] $end

$var wire 1 \ inc_pc $end

$var wire 1 ] inc_su $end

$var wire 16 z# new_pc [15:0] $end

$var wire 16 {# offset16 [15:0] $end

$var wire 4 |# path_left_addr [3:0] $end

$var wire 4 }# path_right_addr [3:0] $end

$var wire 8 ~# reg_dp [7:0] $end

$var wire 16 !$ reg_pc [15:0] $end

$var wire 1 o set_e $end

$var wire 1 ; use_s $end

$var wire 1 q write_exg $end

$var wire 1 "$ write_flags $end

$var wire 1 r write_pc $end

$var wire 1 s write_post $end

$var wire 1 p write_reg $end

$var wire 4 #$ write_reg_addr [3:0] $end

$var wire 1 t write_tfr $end

$var wire 16 $$ reg_su [15:0] $end

$var wire 16 %$ left [15:0] $end

$var wire 8 &$ CCR_o [7:0] $end

$var reg 8 '$ ACCA [7:0] $end

$var reg 8 ($ ACCB [7:0] $end

$var reg 8 )$ DP [7:0] $end

$var reg 16 *$ IX [15:0] $end

$var reg 16 +$ IY [15:0] $end

$var reg 16 ,$ PC [15:0] $end

$var reg 16 -$ SS [15:0] $end

$var reg 16 .$ SU [15:0] $end

$var reg 1 /$ cff $end

$var reg 16 0$ ea_reg [15:0] $end

$var reg 16 1$ ea_reg_post [15:0] $end

$var reg 16 2$ eamem_addr [15:0] $end

$var reg 1 3$ eflag $end

$var reg 1 4$ fflag $end

$var reg 1 5$ hflag $end

$var reg 1 6$ intff $end

$var reg 1 7$ nff $end

$var reg 16 8$ path_left_data [15:0] $end

$var reg 16 9$ path_right_data [15:0] $end

$var reg 1 :$ vff $end

$var reg 1 ;$ zff $end

$upscope $end

$scope module test_cond $end

$var wire 8 <$ CCR [7:0] $end

$var wire 8 =$ opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 8 >$ postbyte0 [7:0] $end

$var wire 8 ?$ op [7:0] $end

$var reg 1 H cond_taken $end

$upscope $end

$upscope $end

$scope module imem $end

$var wire 16 @$ addr [15:0] $end

$var wire 8 A$ data_i [7:0] $end

$var wire 8 B$ data_o [7:0] $end

$var wire 8 C$ mem0 [7:0] $end

$var wire 8 D$ mem1 [7:0] $end

$var wire 8 E$ mem2 [7:0] $end

$var wire 8 F$ mem3 [7:0] $end

$var wire 1 G$ oe $end

$var wire 1 H$ we $end

$var reg 8 I$ latecheddata [7:0] $end

$upscope $end

$upscope $end

$enddefinitions $end

#0

$dumpvars

bx I$

1H$

1G$

b111101 F$

b10111011 E$

b10101010 D$

b11001100 C$

bx B$

bx A$

bx @$

bx ?$

bx >$

bx =$

b0 <$

0;$

0:$

b1111111111111111 9$

b1111111111111111 8$

07$

06$

05$

04$

03$

bx 2$

bx 1$

bx 0$

0/$

b111000000000 .$

b111100000000 -$

b1111111111111110 ,$

b1010010101011010 +$

b0 *$

b0 )$

bx ($

bx '$

b0 &$

b0 %$

b111x00000000 $$

bx #$

0"$

b1111111111111110 !$

b0 ~#

bx }#

bx |#

bx {#

bx z#

bx y#

bx x#

b0 w#

b100 v#

bx u#

bx t#

bx s#

bx r#

bx q#

xp#

bx o#

bx n#

bx m#

bx l#

bx k#

bx j#

bx i#

bx h#

bx g#

bx f#

0e#

bx d#

b0 c#

b0 b#

0a#

0`#

b100 _#

b0 ^#

bx ]#

bx \#

bx [#

bx Z#

bx Y#

0X#

xW#

xV#

xU#

xT#

xS#

xR#

xQ#

xP#

xO#

xN#

xM#

xL#

xK#

xJ#

xI#

bx H#

bx G#

xF#

0E#

0D#

bx C#

bx B#

bx0 A#

b0xxxxxxx @#

bx ?#

bx >#

bx0 =#

b0xxxxxxx <#

bx ;#

bx :#

09#

08#

x7#

x6#

x5#

x4#

x3#

x2#

x1#

00#

x/#

0.#

x-#

x,#

b0xxxxxxx +#

bx0 *#

b0xxxxxxx )#

bx0 (#

bx '#

bx &#

bx %#

bx $#

bx ##

bx "#

bx !#

x~"

0}"

b0xxxxxxxx |"

bx {"

bx z"

bx y"

b0xxxxxxxx x"

bx w"

bx v"

bx u"

bx t"

bx s"

1r"

0q"

bx p"

xo"

xn"

b0 m"

b0 l"

0k"

0j"

b100 i"

b0 h"

bx g"

bx f"

bx e"

bx d"

bx c"

0b"

xa"

x`"

x_"

x^"

x]"

x\"

x["

xZ"

xY"

xX"

xW"

xV"

xU"

xT"

xS"

bx R"

0Q"

bx P"

bx O"

bx0 N"

b0xxxxxxxxxxxxxxx M"

bx L"

bx K"

bx0 J"

b0xxxxxxxxxxxxxxx I"

bx H"

bx G"

0F"

0E"

xD"

xC"

xB"

xA"

x@"

x?"

x>"

0="

x<"

0;"

x:"

x9"

b0xxxxxxxxxxxxxxx 8"

bx0 7"

b0xxxxxxxxxxxxxxx 6"

bx0 5"

bx 4"

bx 3"

bx 2"

bx 1"

bx 0"

bx /"

bx ."

x-"

0,"

bx +"

bx *"

bx )"

bx ("

bx '"

bx &"

bx %"

b0 $"

b100 #"

b0 ""

b100 !"

b100 ~

bx }

b0 |

b0 {

bx z

b1111111111111111 y

b0 x

bx w

bx v

bx u

0t

xs

xr

0q

xp

xo

b0 n

b0 m

b0 l

bx k

bx j

bx i

xh

xg

bx f

bx e

bx d

bx c

0b

bx a

bx `

b0 _

bx ^

x]

x\

x[

bx Z

bx Y

xX

bx W

bx V

xU

bx T

b0 S

bx R

b1111111111111111 Q

bx P

b100 O

b0 N

bx M

bx L

bx K

bx J

xI

0H

bx G

xF

xE

xD

xC

xB

bx A

bx @

bx ?

bx >

bx =

x<

x;

x:

x9

b0 8

b0 7

bx 6

b1111111111111111 5

b1111111111111110 4

b1111111111111111 3

b111x00000000 2

11

00

0/

0.

b0 -

z,

z+

z*

1)

0(

bx '

bx &

bx %

0$

0#

bx "

bx !

$end

#5

01#

1Q#

0R#

1~"

0/#

05#

02#

b0 !#

b0 "#

b11111111 &#

b11111111 '#

16#

13#

b101 G#

b101 H#

0>"

0<"

0B"

0?"

b1 %#

b1 C#

b11111111 {"

b11111111 Y#

b1111111 +#

b1111111 <#

b11111110 (#

b11111110 *#

b11111110 =#

b1111111 )#

b1111111 @#

b11111110 A#

1S#

1K#

1L#

1O#

1P#

1F#

0\"

1-"

1C"

1@"

b11111111 x"

b0 ."

b0 /"

b1111111111111111 3"

b1111111111111111 4"

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