Subversion Repositories 6809_6309_compatible_core

Lattice Place and Route Report for Design "P6809_P6809_map.ncd"

Thu Feb  6 15:35:23 2014

PAR: Place And Route Diamond (64-bit) 2.2.0.101.

Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf

Preference file: P6809_P6809.prf.

Placement level-cost: 5-1.

Routing Iterations: 6

Loading design for application par from file P6809_P6809_map.ncd.

Design name: CC3_top

NCD version: 3.2

Vendor:      LATTICE

Device:      LCMXO2-7000HE

Package:     TQFP144

Performance: 4

Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.

Package Status:                     Final          Version 1.36

Performance Hardware Data Status:   Final)         Version 23.4

License checked out.

Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)   69+4(JTAG)/336     20% used

                  69+4(JTAG)/115     60% bonded

   IOLOGIC           10/336           2% used

   SLICE           1208/3432         35% used

   GSR                1/1           100% used

   EBR               10/26           38% used

INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.

INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.

Number of Signals: 2917

Number of Connections: 9622

Pin Constraint Summary:

   68 out of 68 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:

    cpu_clkgen (driver: clk40_i, clk load #: 367)

The following 6 signals are selected to use the secondary clock routing resources:

    cpu0/G_9 (driver: cpu0/SLICE_764, clk load #: 0, sr load #: 0, ce load #: 80)

    cpu0/PC_1_sqmuxa_2_RNIK4633 (driver: cpu0/regs/SLICE_982, clk load #: 0, sr load #: 0, ce load #: 37)

    cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1 (driver: cpu0/regs/SLICE_322, clk load #: 0, sr load #: 0, ce load #: 25)

    cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3 (driver: cpu0/regs/SLICE_927, clk load #: 0, sr load #: 0, ce load #: 25)

    cpu0/regs/cff_1_sqmuxa_2_RNI1FDN (driver: cpu0/regs/SLICE_1258, clk load #: 0, sr load #: 0, ce load #: 18)

    cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_754, clk load #: 0, sr load #: 0, ce load #: 16)

Signal reset_o_c is selected as Global Set/Reset.

.

Starting Placer Phase 0.

...........

Finished Placer Phase 0.  REAL time: 9 secs

Starting Placer Phase 1.

.........................

Placer score = 922601.

Finished Placer Phase 1.  REAL time: 20 secs

Starting Placer Phase 2.

.

Placer score =  906811

Finished Placer Phase 2.  REAL time: 21 secs

------------------ Clock Report ------------------

Global Clock Resources:

  CLK_PIN    : 1 out of 8 (12%)

  PLL        : 0 out of 2 (0%)

  DCM        : 0 out of 2 (0%)

  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:

  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 367

  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_754" on site "R14C18D", clk load = 0, ce load = 16, sr load = 0

  SECONDARY "cpu0/G_9" from F0 on comp "cpu0/SLICE_764" on site "R21C18A", clk load = 0, ce load = 80, sr load = 0

  SECONDARY "cpu0/PC_1_sqmuxa_2_RNIK4633" from F0 on comp "cpu0/regs/SLICE_982" on site "R14C20A", clk load = 0, ce load = 37, sr load = 0

  SECONDARY "cpu0/regs/cff_1_sqmuxa_2_RNI1FDN" from F1 on comp "cpu0/regs/SLICE_1258" on site "R21C18C", clk load = 0, ce load = 18, sr load = 0

  SECONDARY "cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1" from F1 on comp "cpu0/regs/SLICE_322" on site "R14C20C", clk load = 0, ce load = 25, sr load = 0

  SECONDARY "cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3" from F1 on comp "cpu0/regs/SLICE_927" on site "R14C20B", clk load = 0, ce load = 25, sr load = 0

  PRIMARY  : 1 out of 8 (12%)

  SECONDARY: 6 out of 8 (75%)

Edge Clocks:

  No edge clock selected.

--------------- End of Clock Report ---------------

I/O Usage Summary (final):

   69 out of 336 (20.5%) PIO sites used.

   69 out of 115 (60.0%) bonded PIO sites used.

   Number of PIO comps: 69; differential: 0

   Number of Vref pins used: 0

I/O Bank Usage Summary:

+----------+----------------+------------+-----------+

| I/O Bank | Usage          | Bank Vccio | Bank Vref |

+----------+----------------+------------+-----------+

| 0        | 11 / 28 ( 39%) | 2.5V       | -         |

| 1        | 13 / 29 ( 44%) | 2.5V       | -         |

| 2        | 20 / 29 ( 68%) | 2.5V       | -         |

| 3        | 8 / 9 ( 88%)   | 2.5V       | -         |

| 4        | 7 / 10 ( 70%)  | 2.5V       | -         |

| 5        | 10 / 10 (100%) | 2.5V       | -         |

+----------+----------------+------------+-----------+

Total placer CPU time: 15 secs

Dumping design to file P6809_P6809.dir/5_1.ncd.

Starting router resource preassignment

Completed router resource preassignment. Real time: 26 secs

Start NBR router at Thu Feb 06 15:35:49 CET 2014

*****************************************************************

Info: NBR allows conflicts(one node used by more than one signal)

      in the earlier iterations. In each iteration, it tries to

      solve the conflicts while keeping the critical connections

      routed as short as possible. The routing process is said to

      be completed when no conflicts exist and all connections

      are routed.

Note: NBR uses a different method to calculate timing slacks. The

      worst slack and total negative slack may not be the same as

      that in TRCE report. You should always run TRCE to verify

      your design. Thanks.

*****************************************************************

Start NBR special constraint process at Thu Feb 06 15:35:49 CET 2014

Start NBR section for initial routing

Level 1, iteration 1

104(0.03%) conflicts; 8076(83.93%) untouched conns; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.246ns/0.000ns; real time: 29 secs

Level 2, iteration 1

75(0.02%) conflicts; 7564(78.61%) untouched conns; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.101ns/0.000ns; real time: 30 secs

Level 3, iteration 1

80(0.02%) conflicts; 6340(65.89%) untouched conns; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.302ns/0.000ns; real time: 31 secs

Level 4, iteration 1

428(0.11%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.257ns/0.000ns; real time: 34 secs

Info: Initial congestion level at 75% usage is 3

Info: Initial congestion area  at 75% usage is 41 (4.10%)

Start NBR section for normal routing

Level 1, iteration 1

11(0.00%) conflicts; 624(6.49%) untouched conns; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.167ns/0.000ns; real time: 35 secs

Level 4, iteration 1

131(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 37 secs

Level 4, iteration 2

62(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secs

Level 4, iteration 3

24(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secs

Level 4, iteration 4

13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secs

Level 4, iteration 5

5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs

Level 4, iteration 6

3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs

Level 4, iteration 7

2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs

Level 4, iteration 8

0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs

Start NBR section for re-routing

Level 4, iteration 1

0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;

Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs

Start NBR section for post-routing

End NBR router with 0 unrouted connection

NBR Summary

-----------

  Number of unrouted connections : 0 (0.00%)

  Number of connections with timing violations : 0 (0.00%)

  Estimated worst slack : 0.251ns

  Timing score : 0

-----------

Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.

Hold time optimization iteration 0:

All hold time violations have been successfully corrected in speed grade M

Total CPU time 31 secs

Total REAL time: 47 secs

Completely routed.

End of route.  9622 routed (100.00%); 0 unrouted.

Checking DRC ...

No errors found.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0

Dumping design to file P6809_P6809.dir/5_1.ncd.

All signals are completely routed.

PAR_SUMMARY::Run status = completed

PAR_SUMMARY::Number of unrouted conns = 0

PAR_SUMMARY::Worst  slack> = 0.251

PAR_SUMMARY::Timing score> = 0.000

PAR_SUMMARY::Worst  slack> = 0.217

PAR_SUMMARY::Timing score> = 0.000

Total CPU  time to completion: 32 secs

Total REAL time to completion: 48 secs

par done!

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