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ale500 |
#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
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#Mon Jan 6 06:54:11 2014
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
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@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
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@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":699:23:699:27|Specified digits overflow the number's size
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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Verilog syntax check successful!
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File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
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Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":157:7:157:12|Synthesizing module shift8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":197:7:197:10|Synthesizing module alu8
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:12:240:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:20:240:21|No assignment to z8
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":603:7:603:12|Synthesizing module mul8x8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":128:7:128:13|Synthesizing module arith16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":411:23:411:29|No assignment to wire arith_h
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":517:0:517:5|Pruning register regq16[15:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":418:6:418:13|Ignoring system task $display
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1039:0:1039:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 103 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 104 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 105 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 106 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 107 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 108 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 109 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 110 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 111 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 112 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 113 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 114 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 115 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 116 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[2] is always 0, optimizing ...
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
|
| 126 |
|
|
|
| 127 |
|
|
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
|
| 128 |
|
|
|
| 129 |
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
|
| 130 |
|
|
|
| 131 |
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@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
|
| 132 |
|
|
|
| 133 |
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom
|
| 134 |
|
|
|
| 135 |
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k
|
| 136 |
|
|
|
| 137 |
|
|
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
|
| 138 |
|
|
|
| 139 |
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext
|
| 140 |
|
|
|
| 141 |
|
|
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display
|
| 142 |
|
|
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet
|
| 143 |
|
|
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet
|
| 144 |
|
|
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
| 145 |
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|
@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
|
| 146 |
|
|
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
|
| 147 |
|
|
|
| 148 |
|
|
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
|
| 149 |
|
|
|
| 150 |
|
|
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
|
| 151 |
|
|
|
| 152 |
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|
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
|
| 153 |
|
|
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
|
| 154 |
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
|
| 155 |
|
|
|
| 156 |
|
|
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2
|
| 157 |
|
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o
|
| 158 |
|
|
|
| 159 |
|
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in
|
| 160 |
|
|
|
| 161 |
|
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out
|
| 162 |
|
|
|
| 163 |
|
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we
|
| 164 |
|
|
|
| 165 |
|
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe
|
| 166 |
|
|
|
| 167 |
|
|
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
| 168 |
|
|
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
| 169 |
|
|
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
| 170 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
|
| 171 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
|
| 172 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
|
| 173 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
|
| 174 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
|
| 175 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
|
| 176 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
|
| 177 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
|
| 178 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
|
| 179 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
|
| 180 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
|
| 181 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
|
| 182 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
|
| 183 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
|
| 184 |
|
|
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 5 to 3 of next_push_state[5:0]
|
| 185 |
|
|
|
| 186 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
| 187 |
|
|
|
| 188 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
|
| 189 |
|
|
|
| 190 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
|
| 191 |
|
|
|
| 192 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
| 193 |
|
|
|
| 194 |
|
|
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bits 15 to 13 of pipe0[15:0]
|
| 195 |
|
|
|
| 196 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Register bit pipe0[12] is always 0, optimizing ...
|
| 197 |
|
|
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bit 12 of pipe0[12:0]
|
| 198 |
|
|
|
| 199 |
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:12:198:17|Input clk_in is unused
|
| 200 |
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":159:18:159:21|Input b_in is unused
|
| 201 |
|
|
@END
|
| 202 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 203 |
|
|
# Mon Jan 6 06:54:13 2014
|
| 204 |
|
|
|
| 205 |
|
|
###########################################################]
|
| 206 |
|
|
Premap Report
|
| 207 |
|
|
|
| 208 |
|
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
| 209 |
|
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
| 210 |
|
|
Product Version G-2012.09L-SP1
|
| 211 |
|
|
|
| 212 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
| 213 |
|
|
|
| 214 |
|
|
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
|
| 215 |
|
|
Printing clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
|
| 216 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 217 |
|
|
@N: MF666 |Clock conversion enabled
|
| 218 |
|
|
|
| 219 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
|
| 220 |
|
|
|
| 221 |
|
|
|
| 222 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
|
| 223 |
|
|
|
| 224 |
|
|
|
| 225 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
| 226 |
|
|
|
| 227 |
|
|
|
| 228 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)
|
| 229 |
|
|
|
| 230 |
|
|
|
| 231 |
|
|
|
| 232 |
|
|
Clock Summary
|
| 233 |
|
|
**************
|
| 234 |
|
|
|
| 235 |
|
|
Start Requested Requested Clock Clock
|
| 236 |
|
|
Clock Frequency Period Type Group
|
| 237 |
|
|
--------------------------------------------------------------------------------------------------------------------
|
| 238 |
|
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
|
| 239 |
|
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
| 240 |
|
|
====================================================================================================================
|
| 241 |
|
|
|
| 242 |
|
|
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
| 243 |
|
|
|
| 244 |
|
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
| 245 |
|
|
Finished Pre Mapping Phase.Pre-mapping successful!
|
| 246 |
|
|
|
| 247 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)
|
| 248 |
|
|
|
| 249 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 250 |
|
|
# Mon Jan 6 06:54:14 2014
|
| 251 |
|
|
|
| 252 |
|
|
###########################################################]
|
| 253 |
|
|
Map & Optimize Report
|
| 254 |
|
|
|
| 255 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
| 256 |
|
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
| 257 |
|
|
Product Version G-2012.09L-SP1
|
| 258 |
|
|
|
| 259 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
| 260 |
|
|
|
| 261 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 262 |
|
|
@N: MF666 |Clock conversion enabled
|
| 263 |
|
|
|
| 264 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
| 265 |
|
|
|
| 266 |
|
|
|
| 267 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
| 268 |
|
|
|
| 269 |
|
|
|
| 270 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
|
| 271 |
|
|
|
| 272 |
|
|
|
| 273 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
|
| 274 |
|
|
|
| 275 |
|
|
|
| 276 |
|
|
|
| 277 |
|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
|
| 278 |
|
|
|
| 279 |
|
|
|
| 280 |
|
|
Available hyper_sources - for debug and ip models
|
| 281 |
|
|
None Found
|
| 282 |
|
|
|
| 283 |
|
|
|
| 284 |
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
|
| 285 |
|
|
|
| 286 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 287 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 288 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 289 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
|
| 290 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
|
| 291 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
| 292 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
| 293 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
|
| 294 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
| 295 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
|
| 296 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
| 297 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 298 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 299 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 300 |
|
|
|
| 301 |
|
|
Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 161MB)
|
| 302 |
|
|
|
| 303 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 304 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 305 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 306 |
|
|
|
| 307 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 163MB)
|
| 308 |
|
|
|
| 309 |
|
|
|
| 310 |
|
|
|
| 311 |
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 165MB)
|
| 312 |
|
|
|
| 313 |
|
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":883:11:883:29|Pipelining module un75
|
| 314 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register k_pp_regs[7:0] pushed in.
|
| 315 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":143:35:143:85|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
|
| 316 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":100:35:100:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_2[8:0] from cpu0.alu.alu8.a8.un26_q_out[8:0]
|
| 317 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":140:35:140:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
|
| 318 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":99:35:99:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_1_0[8:0] from cpu0.alu.alu8.a8.un17_q_out[8:0]
|
| 319 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":254:2:254:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.ea.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]
|
| 320 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
|
| 321 |
|
|
|
| 322 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
|
| 323 |
|
|
|
| 324 |
|
|
|
| 325 |
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 151MB peak: 165MB)
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 165MB)
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 212MB peak: 229MB)
|
| 335 |
|
|
|
| 336 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 337 |
|
|
------------------------------------------------------------
|
| 338 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 339 |
|
|
------------------------------------------------------------
|
| 340 |
|
|
------------------------------------------------------------
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 229MB)
|
| 344 |
|
|
|
| 345 |
|
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
| 346 |
|
|
|
| 347 |
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 169MB peak: 229MB)
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
|
| 351 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
| 352 |
|
|
|
| 353 |
|
|
1 non-gated/non-generated clock tree(s) driving 455 clock pin(s) of sequential element(s)
|
| 354 |
|
|
|
| 355 |
|
|
342 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
| 356 |
|
|
|
| 357 |
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
| 358 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
| 359 |
|
|
---------------------------------------------------------------------------------------
|
| 360 |
|
|
@K:CKID0001 clk40_i port 455 cpu_clk
|
| 361 |
|
|
=======================================================================================
|
| 362 |
|
|
===== Gated/Generated Clocks =====
|
| 363 |
|
|
************** None **************
|
| 364 |
|
|
----------------------------------
|
| 365 |
|
|
==================================
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
| 369 |
|
|
|
| 370 |
|
|
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
|
| 371 |
|
|
|
| 372 |
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 172MB peak: 229MB)
|
| 373 |
|
|
|
| 374 |
|
|
Writing EDIF Netlist and constraint files
|
| 375 |
|
|
G-2012.09L-SP1
|
| 376 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
| 377 |
|
|
|
| 378 |
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 176MB peak: 229MB)
|
| 379 |
|
|
|
| 380 |
|
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
|
|
|
| 384 |
|
|
##### START OF TIMING REPORT #####[
|
| 385 |
|
|
# Timing Report written on Mon Jan 6 06:54:29 2014
|
| 386 |
|
|
#
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
Top view: CC3_top
|
| 390 |
|
|
Requested Frequency: 1.0 MHz
|
| 391 |
|
|
Wire load mode: top
|
| 392 |
|
|
Paths requested: 5
|
| 393 |
|
|
Constraint File(s):
|
| 394 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
| 395 |
|
|
|
| 396 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
| 397 |
|
|
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
Performance Summary
|
| 401 |
|
|
*******************
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
Worst slack in design: 978.474
|
| 405 |
|
|
|
| 406 |
|
|
Requested Estimated Requested Estimated Clock Clock
|
| 407 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
| 408 |
|
|
------------------------------------------------------------------------------------------------------------------------
|
| 409 |
|
|
CC3_top|clk40_i 1.0 MHz 46.5 MHz 1000.000 21.526 978.474 inferred Inferred_clkgroup_0
|
| 410 |
|
|
========================================================================================================================
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
|
| 414 |
|
|
|
| 415 |
|
|
|
| 416 |
|
|
Clock Relationships
|
| 417 |
|
|
*******************
|
| 418 |
|
|
|
| 419 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
| 420 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
| 421 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
| 422 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
| 423 |
|
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 978.474 | No paths - | No paths - | No paths -
|
| 424 |
|
|
==========================================================================================================================
|
| 425 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
| 426 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 427 |
|
|
|
| 428 |
|
|
|
| 429 |
|
|
|
| 430 |
|
|
Interface Information
|
| 431 |
|
|
*********************
|
| 432 |
|
|
|
| 433 |
|
|
No IO constraint found
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
====================================
|
| 438 |
|
|
Detailed Report for Clock: CC3_top|clk40_i
|
| 439 |
|
|
====================================
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
|
| 443 |
|
|
Starting Points with Worst Slack
|
| 444 |
|
|
********************************
|
| 445 |
|
|
|
| 446 |
|
|
Starting Arrival
|
| 447 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 448 |
|
|
Clock
|
| 449 |
|
|
----------------------------------------------------------------------------------------------
|
| 450 |
|
|
cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.302 978.474
|
| 451 |
|
|
cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.302 978.617
|
| 452 |
|
|
cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.292 978.627
|
| 453 |
|
|
cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.296 978.766
|
| 454 |
|
|
cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.292 978.770
|
| 455 |
|
|
cpu0.alu.ra_in[0] CC3_top|clk40_i FD1P3AX Q ra_in[0] 1.305 979.039
|
| 456 |
|
|
cpu0.alu.ra_in[1] CC3_top|clk40_i FD1P3AX Q ra_in[1] 1.309 979.178
|
| 457 |
|
|
cpu0.alu.ra_in[2] CC3_top|clk40_i FD1P3AX Q ra_in[2] 1.309 979.178
|
| 458 |
|
|
cpu0.alu.ra_in[3] CC3_top|clk40_i FD1P3AX Q ra_in[3] 1.305 979.324
|
| 459 |
|
|
cpu0.alu.ra_in[4] CC3_top|clk40_i FD1P3AX Q ra_in[4] 1.292 979.338
|
| 460 |
|
|
==============================================================================================
|
| 461 |
|
|
|
| 462 |
|
|
|
| 463 |
|
|
Ending Points with Worst Slack
|
| 464 |
|
|
******************************
|
| 465 |
|
|
|
| 466 |
|
|
Starting Required
|
| 467 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 468 |
|
|
Clock
|
| 469 |
|
|
----------------------------------------------------------------------------------------------
|
| 470 |
|
|
cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 978.474
|
| 471 |
|
|
cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 978.474
|
| 472 |
|
|
cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 978.474
|
| 473 |
|
|
cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 978.474
|
| 474 |
|
|
cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 978.617
|
| 475 |
|
|
cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 978.617
|
| 476 |
|
|
cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 978.617
|
| 477 |
|
|
cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 978.617
|
| 478 |
|
|
cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 978.760
|
| 479 |
|
|
cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 978.760
|
| 480 |
|
|
==============================================================================================
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
|
| 484 |
|
|
Worst Path Information
|
| 485 |
|
|
***********************
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
Path information for path number 1:
|
| 489 |
|
|
Requested Period: 1000.000
|
| 490 |
|
|
- Setup time: 0.106
|
| 491 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 492 |
|
|
= Required time: 999.894
|
| 493 |
|
|
|
| 494 |
|
|
- Propagation time: 21.420
|
| 495 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 496 |
|
|
= Slack (critical) : 978.474
|
| 497 |
|
|
|
| 498 |
|
|
Number of logic level(s): 23
|
| 499 |
|
|
Starting point: cpu0.alu.rb_in[0] / Q
|
| 500 |
|
|
Ending point: cpu0.regs.SS[15] / D
|
| 501 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 502 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 503 |
|
|
|
| 504 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 505 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 506 |
|
|
---------------------------------------------------------------------------------------------------------
|
| 507 |
|
|
cpu0.alu.rb_in[0] FD1P3AX Q Out 1.302 1.302 -
|
| 508 |
|
|
rb_in[0] Net - - - - 26
|
| 509 |
|
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO INV A In 0.000 1.302 -
|
| 510 |
|
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.870 -
|
| 511 |
|
|
rb_in_i[0] Net - - - - 1
|
| 512 |
|
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.870 -
|
| 513 |
|
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0 CCU2D COUT Out 1.544 3.415 -
|
| 514 |
|
|
un8_q_out_cry_0 Net - - - - 1
|
| 515 |
|
|
cpu0.alu.alu8.a8.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.415 -
|
| 516 |
|
|
cpu0.alu.alu8.a8.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.964 -
|
| 517 |
|
|
un8_q_out[2] Net - - - - 1
|
| 518 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.964 -
|
| 519 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.981 -
|
| 520 |
|
|
q_out_2_cry_1_0_RNO_0 Net - - - - 1
|
| 521 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0 CCU2D C1 In 0.000 5.981 -
|
| 522 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0 CCU2D COUT Out 1.544 7.525 -
|
| 523 |
|
|
q_out_2_cry_2 Net - - - - 1
|
| 524 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_3_0 CCU2D CIN In 0.000 7.525 -
|
| 525 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_3_0 CCU2D COUT Out 0.143 7.668 -
|
| 526 |
|
|
q_out_2_cry_4 Net - - - - 1
|
| 527 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_5_0 CCU2D CIN In 0.000 7.668 -
|
| 528 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_5_0 CCU2D COUT Out 0.143 7.811 -
|
| 529 |
|
|
q_out_2_cry_6 Net - - - - 1
|
| 530 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_7_0 CCU2D CIN In 0.000 7.811 -
|
| 531 |
|
|
cpu0.alu.alu8.a8.q_out_2_cry_7_0 CCU2D S0 Out 1.549 9.360 -
|
| 532 |
|
|
N_2388 Net - - - - 1
|
| 533 |
|
|
cpu0.alu.alu8.a8.q_out_3[7] ORCALUT4 A In 0.000 9.360 -
|
| 534 |
|
|
cpu0.alu.alu8.a8.q_out_3[7] ORCALUT4 Z Out 1.089 10.448 -
|
| 535 |
|
|
arith_q[7] Net - - - - 2
|
| 536 |
|
|
cpu0.alu.alu8.q_out_4_am[7] ORCALUT4 A In 0.000 10.448 -
|
| 537 |
|
|
cpu0.alu.alu8.q_out_4_am[7] ORCALUT4 Z Out 1.017 11.465 -
|
| 538 |
|
|
q_out_4_am[7] Net - - - - 1
|
| 539 |
|
|
cpu0.alu.alu8.q_out_4[7] PFUMX BLUT In 0.000 11.465 -
|
| 540 |
|
|
cpu0.alu.alu8.q_out_4[7] PFUMX Z Out 0.286 11.751 -
|
| 541 |
|
|
N_160 Net - - - - 2
|
| 542 |
|
|
cpu0.alu.alu8.q_out_5_RNIRSTD1[7] ORCALUT4 A In 0.000 11.751 -
|
| 543 |
|
|
cpu0.alu.alu8.q_out_5_RNIRSTD1[7] ORCALUT4 Z Out 1.089 12.840 -
|
| 544 |
|
|
q8_out[7] Net - - - - 2
|
| 545 |
|
|
cpu0.alu.q_out[7] ORCALUT4 A In 0.000 12.840 -
|
| 546 |
|
|
cpu0.alu.q_out[7] ORCALUT4 Z Out 0.449 13.289 -
|
| 547 |
|
|
alu_o_result[7] Net - - - - 1
|
| 548 |
|
|
cpu0.alu.alu8.l8.datamux_o_dest[7] PFUMX ALUT In 0.000 13.289 -
|
| 549 |
|
|
cpu0.alu.alu8.l8.datamux_o_dest[7] PFUMX Z Out 0.286 13.575 -
|
| 550 |
|
|
datamux_o_dest[7] Net - - - - 2
|
| 551 |
|
|
cpu0.regs.path_left_data_RNIOEVA1[7] ORCALUT4 B In 0.000 13.575 -
|
| 552 |
|
|
cpu0.regs.path_left_data_RNIOEVA1[7] ORCALUT4 Z Out 1.273 14.848 -
|
| 553 |
|
|
left_1[7] Net - - - - 9
|
| 554 |
|
|
cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 14.848 -
|
| 555 |
|
|
cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 15.865 -
|
| 556 |
|
|
N_250 Net - - - - 1
|
| 557 |
|
|
cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 15.865 -
|
| 558 |
|
|
cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 16.882 -
|
| 559 |
|
|
SS_16[7] Net - - - - 1
|
| 560 |
|
|
cpu0.regs.SS_228_m3 ORCALUT4 B In 0.000 16.882 -
|
| 561 |
|
|
cpu0.regs.SS_228_m3 ORCALUT4 Z Out 1.017 17.898 -
|
| 562 |
|
|
SS_228_i1_mux Net - - - - 1
|
| 563 |
|
|
cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 17.898 -
|
| 564 |
|
|
cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.544 19.443 -
|
| 565 |
|
|
SS_cry[7] Net - - - - 1
|
| 566 |
|
|
cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 19.443 -
|
| 567 |
|
|
cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 19.586 -
|
| 568 |
|
|
SS_cry[9] Net - - - - 1
|
| 569 |
|
|
cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 19.586 -
|
| 570 |
|
|
cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 19.729 -
|
| 571 |
|
|
SS_cry[11] Net - - - - 1
|
| 572 |
|
|
cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 19.729 -
|
| 573 |
|
|
cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 19.871 -
|
| 574 |
|
|
SS_cry[13] Net - - - - 1
|
| 575 |
|
|
cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 19.871 -
|
| 576 |
|
|
cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 21.420 -
|
| 577 |
|
|
SS_s[15] Net - - - - 1
|
| 578 |
|
|
cpu0.regs.SS[15] FD1P3AX D In 0.000 21.420 -
|
| 579 |
|
|
=========================================================================================================
|
| 580 |
|
|
|
| 581 |
|
|
|
| 582 |
|
|
|
| 583 |
|
|
##### END OF TIMING REPORT #####]
|
| 584 |
|
|
|
| 585 |
|
|
---------------------------------------
|
| 586 |
|
|
Resource Usage Report
|
| 587 |
|
|
Part: lcmxo2_7000he-4
|
| 588 |
|
|
|
| 589 |
|
|
Register bits: 439 of 6864 (6%)
|
| 590 |
|
|
PIC Latch: 0
|
| 591 |
|
|
I/O cells: 49
|
| 592 |
|
|
Block Rams : 10 of 26 (38%)
|
| 593 |
|
|
|
| 594 |
|
|
|
| 595 |
|
|
Details:
|
| 596 |
|
|
CCU2D: 196
|
| 597 |
|
|
DP8KC: 10
|
| 598 |
|
|
FD1P3AX: 393
|
| 599 |
|
|
FD1P3DX: 6
|
| 600 |
|
|
FD1S3AX: 28
|
| 601 |
|
|
FD1S3IX: 2
|
| 602 |
|
|
GSR: 1
|
| 603 |
|
|
IB: 1
|
| 604 |
|
|
INV: 19
|
| 605 |
|
|
L6MUX21: 26
|
| 606 |
|
|
OB: 40
|
| 607 |
|
|
OBZ: 8
|
| 608 |
|
|
OFS1P3DX: 9
|
| 609 |
|
|
OFS1P3IX: 1
|
| 610 |
|
|
ORCALUT4: 2024
|
| 611 |
|
|
PFUMX: 222
|
| 612 |
|
|
PUR: 1
|
| 613 |
|
|
VHI: 13
|
| 614 |
|
|
VLO: 20
|
| 615 |
|
|
false: 1
|
| 616 |
|
|
true: 8
|
| 617 |
|
|
Mapper successful!
|
| 618 |
|
|
|
| 619 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)
|
| 620 |
|
|
|
| 621 |
|
|
Process took 0h:00m:14s realtime, 0h:00m:14s cputime
|
| 622 |
|
|
# Mon Jan 6 06:54:29 2014
|
| 623 |
|
|
|
| 624 |
|
|
###########################################################]
|
