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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.srr] - Blame information for rev 10

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Line No. Rev Author Line
1 9 ale500 
#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
9 10 ale500 
#Thu Feb  6 15:34:32 2014
10 9 ale500 
 
11 
Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
14 
 
15 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
17 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
18 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
20 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
21 
@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
22 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
23 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
24 
@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
25 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
26 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
27 10 ale500 
@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":732:23:732:27|Specified digits overflow the number's size
28 9 ale500 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
29 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
30 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
31 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
32 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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Verilog syntax check successful!
34 10 ale500 
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v changed - recompiling
35 9 ale500 
Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
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38 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
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40 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":158:7:158:12|Synthesizing module shift8
41 9 ale500 
 
42 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:7:198:10|Synthesizing module alu8
43 9 ale500 
 
44 10 ale500 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
45 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:12:241:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:20:241:21|No assignment to z8
47 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":302:0:302:5|Pruning register regq8[7:0]
48 9 ale500 
 
49 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":604:7:604:12|Synthesizing module mul8x8
50 9 ale500 
 
51 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":129:7:129:13|Synthesizing module arith16
52 9 ale500 
 
53 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":326:7:326:11|Synthesizing module alu16
54 9 ale500 
 
55 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":412:23:412:29|No assignment to wire arith_h
56 9 ale500 
 
57 10 ale500 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":518:0:518:5|Pruning register regq16[15:0]
58 9 ale500 
 
59 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
60 
 
61 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
62 
 
63 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
64 
 
65 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
66 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
67 
 
68 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op
69 
 
70 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea
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72 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
75 
 
76 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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78 10 ale500 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":450:6:450:13|Ignoring system task $display
79 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1074:0:1074:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
80 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":67:11:67:23|No assignment to wire alu8_o_result
81 9 ale500 
 
82 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":68:11:68:20|No assignment to wire alu8_o_CCR
83 9 ale500 
 
84 10 ale500 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
85 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
86 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
87 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
88 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
89 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
90 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
91 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
92 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
93 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
94 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
95 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
96 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
97 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
98 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
99 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
100 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
101 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
102 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
103 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
104 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
105 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
106 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
107 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
108 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
109 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
110 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
111 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
112 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
113 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
114 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
115 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
116 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
117 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit k_mem_dest[1] is always 0, optimizing ...
118 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[1] is always 0, optimizing ...
119 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[2] is always 0, optimizing ...
120 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
121 9 ale500 
 
122 10 ale500 
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bit 1 of k_mem_dest[1:0]
123 
 
124 9 ale500 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
125 
 
126 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
127 
 
128 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
129 
 
130 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
131 
 
132 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
133 
 
134 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom
135 
 
136 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k
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138 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
139 
 
140 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext
141 
 
142 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display
143 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet
144 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet
145 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
146 
@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
147 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
148 
 
149 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
150 
 
151 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
152 
 
153 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
154 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
155 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
156 
 
157 10 ale500 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:14:37:21|No assignment to clk_div2
158 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o
159 9 ale500 
 
160 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in
161 9 ale500 
 
162 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out
163 9 ale500 
 
164 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:23:44:29|No assignment to wire cpu1_we
165 9 ale500 
 
166 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe
167 9 ale500 
 
168 10 ale500 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
169 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
170 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
171 9 ale500 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
172 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
173 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
174 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
175 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
176 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
177 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
178 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
179 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
180 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
181 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
182 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
183 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
184 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
185 10 ale500 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 5 to 3 of next_push_state[5:0]
186 9 ale500 
 
187 10 ale500 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":22:12:22:20|Input debug_clk is unused
188 9 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
189 
 
190 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
191 
 
192 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
193 
 
194 10 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused
195 9 ale500 
 
196 10 ale500 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]
197 9 ale500 
 
198 10 ale500 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...
199 
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]
200 9 ale500 
 
201 10 ale500 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":199:12:199:17|Input clk_in is unused
202 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":160:18:160:21|Input b_in is unused
203 9 ale500 
@END
204 10 ale500 
Process took 0h:00m:04s realtime, 0h:00m:02s cputime
205 
# Thu Feb  6 15:34:36 2014
206 9 ale500 
 
207 
###########################################################]
208 
Premap Report
209 
 
210 
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
211 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
212 
Product Version G-2012.09L-SP1
213 
 
214 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
215 
 
216 
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
217 
Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
218 
@N: MF248 |Running in 64-bit mode.
219 
@N: MF666 |Clock conversion enabled
220 
 
221 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
222 
 
223 
 
224 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
225 
 
226 
 
227 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
228 
 
229 
 
230 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)
231 
 
232 
 
233 
 
234 
Clock Summary
235 
**************
236 
 
237 
Start                             Requested     Requested     Clock                              Clock
238 
Clock                             Frequency     Period        Type                               Group
239 
--------------------------------------------------------------------------------------------------------------------
240 
CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0
241 10 ale500 
CC3_top|div_derived_clock         1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
242 9 ale500 
CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
243 
====================================================================================================================
244 
 
245 10 ale500 
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
246 9 ale500 
 
247 
syn_allowed_resources : blockrams=26  set on top level netlist CC3_top
248 
Finished Pre Mapping Phase.Pre-mapping successful!
249 
 
250 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)
251 
 
252 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
253 10 ale500 
# Thu Feb  6 15:34:40 2014
254 9 ale500 
 
255 
###########################################################]
256 
Map & Optimize Report
257 
 
258 
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
259 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
260 
Product Version G-2012.09L-SP1
261 
 
262 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
263 
 
264 
@N: MF248 |Running in 64-bit mode.
265 
@N: MF666 |Clock conversion enabled
266 
 
267 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
268 
 
269 
 
270 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
271 
 
272 
 
273 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
274 
 
275 
 
276 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
277 
 
278 
 
279 
 
280 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
281 
 
282 
 
283 
Available hyper_sources - for debug and ip models
284 
        None Found
285 
 
286 
 
287 10 ale500 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
288 9 ale500 
 
289 10 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
290 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
291 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
292 9 ale500 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
293 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
294 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
295 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
296 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
297 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
298 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
299 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
300 10 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
301 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
302 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
303 9 ale500 
 
304 10 ale500 
Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 159MB)
305 9 ale500 
 
306 10 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
307 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
308 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
309 9 ale500 
 
310 10 ale500 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 160MB)
311 9 ale500 
 
312 
 
313 
 
314 10 ale500 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 160MB)
315 9 ale500 
 
316 10 ale500 
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]
317 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IY[15:0] pushed in.
318 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IX[15:0] pushed in.
319 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_ind_ea[7:0] pushed in.
320 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register DP[7:0] pushed in.
321 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.
322 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register eflag pushed in.
323 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register fflag pushed in.
324 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register hflag pushed in.
325 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register intff pushed in.
326 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register nff pushed in.
327 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register zff pushed in.
328 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register vff pushed in.
329 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register cff pushed in.
330 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register PC[15:0] pushed in.
331 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.
332 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_write_pc pushed in.
333 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_inc_pc pushed in.
334 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":141:35:141:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
335 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":142:35:142:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
336 9 ale500 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
337 
 
338 10 ale500 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
339 9 ale500 
 
340 
 
341 10 ale500 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
342 9 ale500 
 
343 
 
344 10 ale500 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 160MB)
345 9 ale500 
 
346 
 
347 10 ale500 
Finished preparing to map (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:11s; Memory used current: 151MB peak: 160MB)
348 9 ale500 
 
349 
 
350 10 ale500 
Finished technology mapping (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 230MB)
351 9 ale500 
 
352 
Pass             CPU time               Worst Slack             Luts / Registers
353 
------------------------------------------------------------
354 
Pass             CPU time               Worst Slack             Luts / Registers
355 
------------------------------------------------------------
356 
------------------------------------------------------------
357 
 
358 
 
359 10 ale500 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 230MB)
360 9 ale500 
 
361 
@N: FX164 |The option to pack flops in the IOB has not been specified
362 
 
363 10 ale500 
Finished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:15s; Memory used current: 168MB peak: 230MB)
364 9 ale500 
 
365 
 
366 
 
367 
#### START OF CLOCK OPTIMIZATION REPORT #####[
368 
 
369 10 ale500 
1 non-gated/non-generated clock tree(s) driving 596 clock pin(s) of sequential element(s)
370 9 ale500 
 
371 10 ale500 
264 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
372 9 ale500 
 
373 
=========================== Non-Gated/Non-Generated Clocks ============================
374 
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
375 
---------------------------------------------------------------------------------------
376 10 ale500 
@K:CKID0001       clk40_i             port                   596        div
377 9 ale500 
=======================================================================================
378 
===== Gated/Generated Clocks =====
379 
************** None **************
380 
----------------------------------
381 
==================================
382 
 
383 
 
384 
##### END OF CLOCK OPTIMIZATION REPORT ######]
385 
 
386 
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
387 
 
388 10 ale500 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:16s; Memory used current: 170MB peak: 230MB)
389 9 ale500 
 
390 
Writing EDIF Netlist and constraint files
391 
G-2012.09L-SP1
392 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
393 
 
394 10 ale500 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:17s; Memory used current: 174MB peak: 230MB)
395 9 ale500 
 
396 
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
397 
 
398 
 
399 
 
400 
##### START OF TIMING REPORT #####[
401 10 ale500 
# Timing Report written on Thu Feb  6 15:35:10 2014
402 9 ale500 
#
403 
 
404 
 
405 
Top view:               CC3_top
406 
Requested Frequency:    1.0 MHz
407 
Wire load mode:         top
408 
Paths requested:        5
409 
Constraint File(s):
410 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
411 
 
412 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
413 
 
414 
 
415 
 
416 
Performance Summary
417 
*******************
418 
 
419 
 
420 10 ale500 
Worst slack in design: 978.937
421 9 ale500 
 
422 
                    Requested     Estimated     Requested     Estimated                 Clock        Clock
423 
Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group
424 
------------------------------------------------------------------------------------------------------------------------
425 10 ale500 
CC3_top|clk40_i     1.0 MHz       47.5 MHz      1000.000      21.063        978.937     inferred     Inferred_clkgroup_0
426 9 ale500 
========================================================================================================================
427 
 
428 
 
429 
 
430 
 
431 
 
432 
Clock Relationships
433 
*******************
434 
 
435 
Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
436 
--------------------------------------------------------------------------------------------------------------------------
437 
Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
438 
--------------------------------------------------------------------------------------------------------------------------
439 10 ale500 
CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.937  |  No paths    -      |  No paths    -      |  No paths    -
440 9 ale500 
==========================================================================================================================
441 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
442 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
443 
 
444 
 
445 
 
446 
Interface Information
447 
*********************
448 
 
449 
No IO constraint found
450 
 
451 
 
452 
 
453 
====================================
454 
Detailed Report for Clock: CC3_top|clk40_i
455 
====================================
456 
 
457 
 
458 
 
459 
Starting Points with Worst Slack
460 
********************************
461 
 
462 
                      Starting                                             Arrival
463 
Instance              Reference           Type        Pin     Net          Time        Slack
464 
                      Clock
465 
----------------------------------------------------------------------------------------------
466 10 ale500 
cpu0.alu.rb_in[0]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[0]     1.296       978.937
467 
cpu0.alu.rb_in[1]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[1]     1.296       979.080
468 
cpu0.alu.rb_in[2]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[2]     1.284       979.092
469 
cpu0.alu.rb_in[3]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[3]     1.288       979.231
470 
cpu0.alu.rb_in[4]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[4]     1.284       979.235
471 
cpu0.alu.ra_in[0]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[0]     1.299       979.502
472 
cpu0.alu.rb_in[5]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[5]     1.284       979.533
473 
cpu0.alu.rb_in[6]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[6]     1.272       979.545
474 
cpu0.alu.ra_in[1]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[1]     1.299       979.645
475 
cpu0.alu.ra_in[2]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[2]     1.299       979.645
476 9 ale500 
==============================================================================================
477 
 
478 
 
479 
Ending Points with Worst Slack
480 
******************************
481 
 
482 
                     Starting                                             Required
483 
Instance             Reference           Type        Pin     Net          Time         Slack
484 
                     Clock
485 
----------------------------------------------------------------------------------------------
486 10 ale500 
cpu0.regs.SS[14]     CC3_top|clk40_i     FD1P3AX     D       SS_s[14]     999.894      978.937
487 
cpu0.regs.SS[15]     CC3_top|clk40_i     FD1P3AX     D       SS_s[15]     999.894      978.937
488 
cpu0.regs.SU[14]     CC3_top|clk40_i     FD1P3AX     D       SU_s[14]     999.894      978.937
489 
cpu0.regs.SU[15]     CC3_top|clk40_i     FD1P3AX     D       SU_s[15]     999.894      978.937
490 
cpu0.regs.SS[12]     CC3_top|clk40_i     FD1P3AX     D       SS_s[12]     999.894      979.080
491 
cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_s[13]     999.894      979.080
492 
cpu0.regs.SU[12]     CC3_top|clk40_i     FD1P3AX     D       SU_s[12]     999.894      979.080
493 
cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_s[13]     999.894      979.080
494 
cpu0.regs.SS[10]     CC3_top|clk40_i     FD1P3AX     D       SS_s[10]     999.894      979.223
495 
cpu0.regs.SS[11]     CC3_top|clk40_i     FD1P3AX     D       SS_s[11]     999.894      979.223
496 9 ale500 
==============================================================================================
497 
 
498 
 
499 
 
500 
Worst Path Information
501 
***********************
502 
 
503 
 
504 
Path information for path number 1:
505 
      Requested Period:                      1000.000
506 
    - Setup time:                            0.106
507 
    + Clock delay at ending point:           0.000 (ideal)
508 
    = Required time:                         999.894
509 
 
510 10 ale500 
    - Propagation time:                      20.957
511 9 ale500 
    - Clock delay at starting point:         0.000 (ideal)
512 10 ale500 
    = Slack (critical) :                     978.937
513 9 ale500 
 
514 10 ale500 
    Number of logic level(s):                22
515 9 ale500 
    Starting point:                          cpu0.alu.rb_in[0] / Q
516 
    Ending point:                            cpu0.regs.SS[15] / D
517 
    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK
518 
    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK
519 
 
520 10 ale500 
Instance / Net                                            Pin      Pin               Arrival     No. of
521 
Name                                         Type         Name     Dir     Delay     Time        Fan Out(s)
522 
-----------------------------------------------------------------------------------------------------------
523 
cpu0.alu.rb_in[0]                            FD1P3AX      Q        Out     1.296     1.296       -
524 
rb_in[0]                                     Net          -        -       -         -           24
525 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO     INV          A        In      0.000     1.296       -
526 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO     INV          Z        Out     0.568     1.864       -
527 
rb_in_i[0]                                   Net          -        -       -         -           1
528 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0         CCU2D        A1       In      0.000     1.864       -
529 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0         CCU2D        COUT     Out     1.544     3.408       -
530 
un8_q_out_cry_0                              Net          -        -       -         -           1
531 
cpu0.alu.alu16.a16.un8_q_out_cry_1_0         CCU2D        CIN      In      0.000     3.408       -
532 
cpu0.alu.alu16.a16.un8_q_out_cry_1_0         CCU2D        S1       Out     1.549     4.957       -
533 
un8_q_out[2]                                 Net          -        -       -         -           1
534 
cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0     ORCALUT4     A        In      0.000     4.957       -
535 
cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0     ORCALUT4     Z        Out     1.017     5.974       -
536 
q_out_2_cry_1_0_RNO_0                        Net          -        -       -         -           1
537 
cpu0.alu.alu16.a16.q_out_2_cry_1_0           CCU2D        C1       In      0.000     5.974       -
538 
cpu0.alu.alu16.a16.q_out_2_cry_1_0           CCU2D        COUT     Out     1.544     7.519       -
539 
q_out_2_cry_2                                Net          -        -       -         -           1
540 
cpu0.alu.alu16.a16.q_out_2_cry_3_0           CCU2D        CIN      In      0.000     7.519       -
541 
cpu0.alu.alu16.a16.q_out_2_cry_3_0           CCU2D        COUT     Out     0.143     7.661       -
542 
q_out_2_cry_4                                Net          -        -       -         -           1
543 
cpu0.alu.alu16.a16.q_out_2_cry_5_0           CCU2D        CIN      In      0.000     7.661       -
544 
cpu0.alu.alu16.a16.q_out_2_cry_5_0           CCU2D        COUT     Out     0.143     7.804       -
545 
q_out_2_cry_6                                Net          -        -       -         -           1
546 
cpu0.alu.alu16.a16.q_out_2_cry_7_0           CCU2D        CIN      In      0.000     7.804       -
547 
cpu0.alu.alu16.a16.q_out_2_cry_7_0           CCU2D        S0       Out     1.549     9.353       -
548 
N_2370                                       Net          -        -       -         -           1
549 
cpu0.alu.alu16.a16.q_out_3[7]                ORCALUT4     B        In      0.000     9.353       -
550 
cpu0.alu.alu16.a16.q_out_3[7]                ORCALUT4     Z        Out     1.153     10.506      -
551 
arith_q[7]                                   Net          -        -       -         -           3
552 
cpu0.alu.alu16.q_out_1[7]                    ORCALUT4     A        In      0.000     10.506      -
553 
cpu0.alu.alu16.q_out_1[7]                    ORCALUT4     Z        Out     1.017     11.523      -
554 
N_60                                         Net          -        -       -         -           1
555 
cpu0.alu.alu16.q_out[7]                      PFUMX        ALUT     In      0.000     11.523      -
556 
cpu0.alu.alu16.q_out[7]                      PFUMX        Z        Out     0.286     11.809      -
557 
q16_out[7]                                   Net          -        -       -         -           2
558 
cpu0.alu.alu8.datamux_o_dest_bm[7]           ORCALUT4     B        In      0.000     11.809      -
559 
cpu0.alu.alu8.datamux_o_dest_bm[7]           ORCALUT4     Z        Out     1.017     12.826      -
560 
datamux_o_dest_bm[7]                         Net          -        -       -         -           1
561 
cpu0.alu.alu8.datamux_o_dest[7]              PFUMX        ALUT     In      0.000     12.826      -
562 
cpu0.alu.alu8.datamux_o_dest[7]              PFUMX        Z        Out     0.286     13.112      -
563 
datamux_o_dest[7]                            Net          -        -       -         -           2
564 
cpu0.regs.left_1[7]                          ORCALUT4     A        In      0.000     13.112      -
565 
cpu0.regs.left_1[7]                          ORCALUT4     Z        Out     1.273     14.385      -
566 
left_1[7]                                    Net          -        -       -         -           9
567 
cpu0.regs.SS_16_0[7]                         ORCALUT4     B        In      0.000     14.385      -
568 
cpu0.regs.SS_16_0[7]                         ORCALUT4     Z        Out     1.017     15.402      -
569 
N_250                                        Net          -        -       -         -           1
570 
cpu0.regs.SS_16[7]                           ORCALUT4     A        In      0.000     15.402      -
571 
cpu0.regs.SS_16[7]                           ORCALUT4     Z        Out     1.017     16.418      -
572 
SS_16[7]                                     Net          -        -       -         -           1
573 
cpu0.regs.SS_230_m3                          ORCALUT4     B        In      0.000     16.418      -
574 
cpu0.regs.SS_230_m3                          ORCALUT4     Z        Out     1.017     17.435      -
575 
SS_230_i1_mux                                Net          -        -       -         -           1
576 
cpu0.regs.SS_cry_0[6]                        CCU2D        C1       In      0.000     17.435      -
577 
cpu0.regs.SS_cry_0[6]                        CCU2D        COUT     Out     1.544     18.980      -
578 
SS_cry[7]                                    Net          -        -       -         -           1
579 
cpu0.regs.SS_cry_0[8]                        CCU2D        CIN      In      0.000     18.980      -
580 
cpu0.regs.SS_cry_0[8]                        CCU2D        COUT     Out     0.143     19.122      -
581 
SS_cry[9]                                    Net          -        -       -         -           1
582 
cpu0.regs.SS_cry_0[10]                       CCU2D        CIN      In      0.000     19.122      -
583 
cpu0.regs.SS_cry_0[10]                       CCU2D        COUT     Out     0.143     19.265      -
584 
SS_cry[11]                                   Net          -        -       -         -           1
585 
cpu0.regs.SS_cry_0[12]                       CCU2D        CIN      In      0.000     19.265      -
586 
cpu0.regs.SS_cry_0[12]                       CCU2D        COUT     Out     0.143     19.408      -
587 
SS_cry[13]                                   Net          -        -       -         -           1
588 
cpu0.regs.SS_cry_0[14]                       CCU2D        CIN      In      0.000     19.408      -
589 
cpu0.regs.SS_cry_0[14]                       CCU2D        S1       Out     1.549     20.957      -
590 
SS_s[15]                                     Net          -        -       -         -           1
591 
cpu0.regs.SS[15]                             FD1P3AX      D        In      0.000     20.957      -
592 
===========================================================================================================
593 9 ale500 
 
594 
 
595 
 
596 
##### END OF TIMING REPORT #####]
597 
 
598 
---------------------------------------
599 
Resource Usage Report
600 
Part: lcmxo2_7000he-4
601 
 
602 10 ale500 
Register bits: 580 of 6864 (8%)
603 9 ale500 
PIC Latch:       0
604 10 ale500 
I/O cells:       69
605 9 ale500 
Block Rams : 10 of 26 (38%)
606 
 
607 
 
608 
Details:
609 10 ale500 
BB:             8
610 
CCU2D:          186
611 9 ale500 
DP8KC:          10
612 10 ale500 
FD1P3AX:        529
613 9 ale500 
FD1P3DX:        6
614 10 ale500 
FD1S3AX:        32
615 
FD1S3IX:        3
616 9 ale500 
GSR:            1
617 
IB:             1
618 10 ale500 
INV:            20
619 
L6MUX21:        16
620 
OB:             60
621 9 ale500 
OFS1P3DX:       9
622 
OFS1P3IX:       1
623 10 ale500 
ORCALUT4:       2014
624 
PFUMX:          226
625 9 ale500 
PUR:            1
626 10 ale500 
VHI:            14
627 9 ale500 
VLO:            20
628 
false:          1
629 10 ale500 
true:           7
630 9 ale500 
Mapper successful!
631 
 
632 10 ale500 
At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:17s; Memory used current: 44MB peak: 230MB)
633 9 ale500 
 
634 10 ale500 
Process took 0h:00m:30s realtime, 0h:00m:17s cputime
635 
# Thu Feb  6 15:35:11 2014
636 9 ale500 
 
637 
###########################################################]

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