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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.twr] - Blame information for rev 12

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Line No. Rev Author Line
1 12 ale500 
 
2 
Loading design for application trce from file p6809_p6809.ncd.
3 
Design name: CC3_top
4 
NCD version: 3.2
5 
Vendor:      LATTICE
6 
Device:      LCMXO2-7000HE
7 
Package:     TQFP144
8 
Performance: 4
9 
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.
10 
Package Status:                     Final          Version 1.36
11 
Performance Hardware Data Status:   Final)         Version 23.4
12 
Setup and Hold Report
13 
 
14 
--------------------------------------------------------------------------------
15 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.1.0.96
16 
Sun Jul 06 07:47:15 2014
17 
 
18 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
19 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
20 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
21 
Copyright (c) 2001 Agere Systems   All rights reserved.
22 
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.
23 
 
24 
Report Information
25 
------------------
26 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf
27 
Design file:     p6809_p6809.ncd
28 
Preference file: p6809_p6809.prf
29 
Device,speed:    LCMXO2-7000HE,4
30 
Report level:    verbose report, limited to 10 items per preference
31 
--------------------------------------------------------------------------------
32 
 
33 
Report Type:     based on TRACE automatically generated preferences
34 
BLOCK ASYNCPATHS
35 
BLOCK RESETPATHS
36 
--------------------------------------------------------------------------------
37 
 
38 
 
39 
 
40 
================================================================================
41 
Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
42 
            4096 items scored, 4096 timing errors detected.
43 
--------------------------------------------------------------------------------
44 
 
45 
 
46 
Error: The following path exceeds requirements by 24.781ns
47 
 
48 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
49 
 
50 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
51 
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)
52 
 
53 
   Delay:              33.571ns  (26.7% logic, 73.3% route), 18 logic levels.
54 
 
55 
 Constraint Details:
56 
 
57 
     33.571ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
58 
      8.956ns delay constraint less
59 
      0.000ns skew and
60 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.781ns
61 
 
62 
 Physical Path Details:
63 
 
64 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:
65 
 
66 
   Name    Fanout   Delay (ns)          Site               Resource
67 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
68 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
69 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
70 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
71 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
72 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
73 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
74 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
75 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
76 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
77 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
78 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
79 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
80 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
81 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
82 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
83 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
84 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
85 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
86 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
87 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
88 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
89 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
90 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
91 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
92 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
93 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
94 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
95 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
96 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
97 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
98 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
99 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
100 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
101 
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
102 
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
103 
                  --------
104 
                   33.571   (26.7% logic, 73.3% route), 18 logic levels.
105 
 
106 
 Clock Skew Details:
107 
 
108 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
109 
 
110 
   Name    Fanout   Delay (ns)          Site               Resource
111 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
112 
                  --------
113 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
114 
 
115 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
116 
 
117 
   Name    Fanout   Delay (ns)          Site               Resource
118 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
119 
                  --------
120 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
121 
 
122 
 
123 
Error: The following path exceeds requirements by 24.723ns
124 
 
125 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
126 
 
127 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
128 
   Destination:    FF         Data in        cpu0/regs/SS[14]  (to clk40_i_c +)
129 
 
130 
   Delay:              33.513ns  (26.6% logic, 73.4% route), 18 logic levels.
131 
 
132 
 Constraint Details:
133 
 
134 
     33.513ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
135 
      8.956ns delay constraint less
136 
      0.000ns skew and
137 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.723ns
138 
 
139 
 Physical Path Details:
140 
 
141 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:
142 
 
143 
   Name    Fanout   Delay (ns)          Site               Resource
144 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
145 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
146 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
147 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
148 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
149 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
150 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
151 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
152 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
153 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
154 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
155 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
156 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
157 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
158 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
159 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
160 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
161 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
162 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
163 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
164 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
165 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
166 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
167 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
168 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
169 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
170 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
171 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
172 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
173 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
174 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
175 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
176 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
177 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
178 
FCITOF0_DE  ---     0.585    R11C13A.FCI to     R11C13A.F0 cpu0/regs/SLICE_64
179 
ROUTE         1     0.000     R11C13A.F0 to    R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
180 
                  --------
181 
                   33.513   (26.6% logic, 73.4% route), 18 logic levels.
182 
 
183 
 Clock Skew Details:
184 
 
185 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
186 
 
187 
   Name    Fanout   Delay (ns)          Site               Resource
188 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
189 
                  --------
190 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
191 
 
192 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
193 
 
194 
   Name    Fanout   Delay (ns)          Site               Resource
195 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
196 
                  --------
197 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
198 
 
199 
 
200 
Error: The following path exceeds requirements by 24.619ns
201 
 
202 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
203 
 
204 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
205 
   Destination:    FF         Data in        cpu0/regs/SS[13]  (to clk40_i_c +)
206 
 
207 
   Delay:              33.409ns  (26.3% logic, 73.7% route), 17 logic levels.
208 
 
209 
 Constraint Details:
210 
 
211 
     33.409ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
212 
      8.956ns delay constraint less
213 
      0.000ns skew and
214 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.619ns
215 
 
216 
 Physical Path Details:
217 
 
218 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:
219 
 
220 
   Name    Fanout   Delay (ns)          Site               Resource
221 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
222 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
223 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
224 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
225 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
226 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
227 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
228 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
229 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
230 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
231 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
232 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
233 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
234 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
235 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
236 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
237 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
238 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
239 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
240 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
241 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
242 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
243 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
244 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
245 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
246 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
247 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
248 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
249 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
250 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
251 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
252 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
253 
FCITOF1_DE  ---     0.643    R11C12D.FCI to     R11C12D.F1 cpu0/regs/SLICE_65
254 
ROUTE         1     0.000     R11C12D.F1 to    R11C12D.DI1 cpu0/regs/SS_s[13] (to clk40_i_c)
255 
                  --------
256 
                   33.409   (26.3% logic, 73.7% route), 17 logic levels.
257 
 
258 
 Clock Skew Details:
259 
 
260 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
261 
 
262 
   Name    Fanout   Delay (ns)          Site               Resource
263 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
264 
                  --------
265 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
266 
 
267 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_65:
268 
 
269 
   Name    Fanout   Delay (ns)          Site               Resource
270 
ROUTE       318     2.399       27.PADDI to    R11C12D.CLK clk40_i_c
271 
                  --------
272 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
273 
 
274 
 
275 
Error: The following path exceeds requirements by 24.561ns
276 
 
277 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
278 
 
279 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
280 
   Destination:    FF         Data in        cpu0/regs/SS[12]  (to clk40_i_c +)
281 
 
282 
   Delay:              33.351ns  (26.2% logic, 73.8% route), 17 logic levels.
283 
 
284 
 Constraint Details:
285 
 
286 
     33.351ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
287 
      8.956ns delay constraint less
288 
      0.000ns skew and
289 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.561ns
290 
 
291 
 Physical Path Details:
292 
 
293 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:
294 
 
295 
   Name    Fanout   Delay (ns)          Site               Resource
296 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
297 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
298 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
299 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
300 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
301 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
302 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
303 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
304 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
305 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
306 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
307 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
308 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
309 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
310 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
311 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
312 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
313 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
314 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
315 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
316 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
317 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
318 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
319 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
320 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
321 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
322 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
323 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
324 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
325 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
326 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
327 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
328 
FCITOF0_DE  ---     0.585    R11C12D.FCI to     R11C12D.F0 cpu0/regs/SLICE_65
329 
ROUTE         1     0.000     R11C12D.F0 to    R11C12D.DI0 cpu0/regs/SS_s[12] (to clk40_i_c)
330 
                  --------
331 
                   33.351   (26.2% logic, 73.8% route), 17 logic levels.
332 
 
333 
 Clock Skew Details:
334 
 
335 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
336 
 
337 
   Name    Fanout   Delay (ns)          Site               Resource
338 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
339 
                  --------
340 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
341 
 
342 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_65:
343 
 
344 
   Name    Fanout   Delay (ns)          Site               Resource
345 
ROUTE       318     2.399       27.PADDI to    R11C12D.CLK clk40_i_c
346 
                  --------
347 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
348 
 
349 
 
350 
Error: The following path exceeds requirements by 24.119ns
351 
 
352 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
353 
 
354 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
355 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to clk40_i_c +)
356 
 
357 
   Delay:              32.909ns  (30.3% logic, 69.7% route), 22 logic levels.
358 
 
359 
 Constraint Details:
360 
 
361 
     32.909ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
362 
      8.956ns delay constraint less
363 
      0.000ns skew and
364 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.119ns
365 
 
366 
 Physical Path Details:
367 
 
368 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_55:
369 
 
370 
   Name    Fanout   Delay (ns)          Site               Resource
371 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
372 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
373 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
374 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
375 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
376 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
377 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
378 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
379 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
380 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
381 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
382 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
383 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
384 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
385 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
386 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
387 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
388 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
389 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
390 
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
391 
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
392 
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
393 
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
394 
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
395 
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
396 
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
397 
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
398 
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
399 
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
400 
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
401 
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
402 
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
403 
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
404 
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
405 
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
406 
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
407 
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
408 
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
409 
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
410 
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
411 
FCITOFCO_D  ---     0.162    R12C10D.FCI to    R12C10D.FCO cpu0/regs/SLICE_56
412 
ROUTE         1     0.000    R12C10D.FCO to    R12C11A.FCI cpu0/regs/SU_cry[13]
413 
FCITOF1_DE  ---     0.643    R12C11A.FCI to     R12C11A.F1 cpu0/regs/SLICE_55
414 
ROUTE         1     0.000     R12C11A.F1 to    R12C11A.DI1 cpu0/regs/SU_s[15] (to clk40_i_c)
415 
                  --------
416 
                   32.909   (30.3% logic, 69.7% route), 22 logic levels.
417 
 
418 
 Clock Skew Details:
419 
 
420 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
421 
 
422 
   Name    Fanout   Delay (ns)          Site               Resource
423 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
424 
                  --------
425 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
426 
 
427 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
428 
 
429 
   Name    Fanout   Delay (ns)          Site               Resource
430 
ROUTE       318     2.399       27.PADDI to    R12C11A.CLK clk40_i_c
431 
                  --------
432 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
433 
 
434 
 
435 
Error: The following path exceeds requirements by 24.061ns
436 
 
437 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
438 
 
439 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
440 
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to clk40_i_c +)
441 
 
442 
   Delay:              32.851ns  (30.2% logic, 69.8% route), 22 logic levels.
443 
 
444 
 Constraint Details:
445 
 
446 
     32.851ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
447 
      8.956ns delay constraint less
448 
      0.000ns skew and
449 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.061ns
450 
 
451 
 Physical Path Details:
452 
 
453 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_55:
454 
 
455 
   Name    Fanout   Delay (ns)          Site               Resource
456 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
457 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
458 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
459 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
460 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
461 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
462 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
463 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
464 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
465 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
466 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
467 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
468 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
469 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
470 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
471 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
472 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
473 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
474 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
475 
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
476 
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
477 
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
478 
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
479 
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
480 
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
481 
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
482 
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
483 
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
484 
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
485 
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
486 
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
487 
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
488 
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
489 
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
490 
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
491 
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
492 
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
493 
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
494 
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
495 
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
496 
FCITOFCO_D  ---     0.162    R12C10D.FCI to    R12C10D.FCO cpu0/regs/SLICE_56
497 
ROUTE         1     0.000    R12C10D.FCO to    R12C11A.FCI cpu0/regs/SU_cry[13]
498 
FCITOF0_DE  ---     0.585    R12C11A.FCI to     R12C11A.F0 cpu0/regs/SLICE_55
499 
ROUTE         1     0.000     R12C11A.F0 to    R12C11A.DI0 cpu0/regs/SU_s[14] (to clk40_i_c)
500 
                  --------
501 
                   32.851   (30.2% logic, 69.8% route), 22 logic levels.
502 
 
503 
 Clock Skew Details:
504 
 
505 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
506 
 
507 
   Name    Fanout   Delay (ns)          Site               Resource
508 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
509 
                  --------
510 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
511 
 
512 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
513 
 
514 
   Name    Fanout   Delay (ns)          Site               Resource
515 
ROUTE       318     2.399       27.PADDI to    R12C11A.CLK clk40_i_c
516 
                  --------
517 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
518 
 
519 
 
520 
Error: The following path exceeds requirements by 23.971ns
521 
 
522 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
523 
 
524 
   Source:         FF         Q              cpu0/k_opcode[5]  (from clk40_i_c +)
525 
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)
526 
 
527 
   Delay:              32.761ns  (25.8% logic, 74.2% route), 17 logic levels.
528 
 
529 
 Constraint Details:
530 
 
531 
     32.761ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
532 
      8.956ns delay constraint less
533 
      0.000ns skew and
534 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.971ns
535 
 
536 
 Physical Path Details:
537 
 
538 
      Data path cpu0/SLICE_1144 to cpu0/regs/SLICE_64:
539 
 
540 
   Name    Fanout   Delay (ns)          Site               Resource
541 
REG_DEL     ---     0.452    R12C21A.CLK to     R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
542 
ROUTE        52     4.508     R12C21A.Q1 to     R19C22A.A0 cpu0/k_opcode[5]
543 
CTOF_DEL    ---     0.495     R19C22A.A0 to     R19C22A.F0 cpu0/SLICE_772
544 
ROUTE         2     1.308     R19C22A.F0 to     R18C24A.A0 cpu0/un1_k_opcode_3_4
545 
CTOF_DEL    ---     0.495     R18C24A.A0 to     R18C24A.F0 cpu0/dec_regs/SLICE_1118
546 
ROUTE         1     0.693     R18C24A.F0 to     R18C24B.B1 cpu0/dec_regs/path_left_addr79
547 
CTOF_DEL    ---     0.495     R18C24B.B1 to     R18C24B.F1 cpu0/dec_regs/SLICE_771
548 
ROUTE         1     0.964     R18C24B.F1 to     R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
549 
CTOF_DEL    ---     0.495     R17C24A.A1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
550 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
551 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
552 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
553 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
554 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
555 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
556 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
557 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
558 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
559 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
560 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
561 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
562 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
563 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
564 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
565 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
566 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
567 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
568 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
569 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
570 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
571 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
572 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
573 
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
574 
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
575 
                  --------
576 
                   32.761   (25.8% logic, 74.2% route), 17 logic levels.
577 
 
578 
 Clock Skew Details:
579 
 
580 
      Source Clock Path clk40_i to cpu0/SLICE_1144:
581 
 
582 
   Name    Fanout   Delay (ns)          Site               Resource
583 
ROUTE       318     2.399       27.PADDI to    R12C21A.CLK clk40_i_c
584 
                  --------
585 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
586 
 
587 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
588 
 
589 
   Name    Fanout   Delay (ns)          Site               Resource
590 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
591 
                  --------
592 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
593 
 
594 
 
595 
Error: The following path exceeds requirements by 23.957ns
596 
 
597 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
598 
 
599 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
600 
   Destination:    FF         Data in        cpu0/regs/SU[13]  (to clk40_i_c +)
601 
 
602 
   Delay:              32.747ns  (29.9% logic, 70.1% route), 21 logic levels.
603 
 
604 
 Constraint Details:
605 
 
606 
     32.747ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_56 exceeds
607 
      8.956ns delay constraint less
608 
      0.000ns skew and
609 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.957ns
610 
 
611 
 Physical Path Details:
612 
 
613 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_56:
614 
 
615 
   Name    Fanout   Delay (ns)          Site               Resource
616 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
617 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
618 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
619 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
620 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
621 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
622 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
623 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
624 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
625 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
626 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
627 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
628 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
629 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
630 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
631 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
632 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
633 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
634 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
635 
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
636 
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
637 
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
638 
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
639 
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
640 
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
641 
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
642 
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
643 
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
644 
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
645 
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
646 
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
647 
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
648 
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
649 
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
650 
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
651 
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
652 
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
653 
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
654 
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
655 
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
656 
FCITOF1_DE  ---     0.643    R12C10D.FCI to     R12C10D.F1 cpu0/regs/SLICE_56
657 
ROUTE         1     0.000     R12C10D.F1 to    R12C10D.DI1 cpu0/regs/SU_s[13] (to clk40_i_c)
658 
                  --------
659 
                   32.747   (29.9% logic, 70.1% route), 21 logic levels.
660 
 
661 
 Clock Skew Details:
662 
 
663 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
664 
 
665 
   Name    Fanout   Delay (ns)          Site               Resource
666 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
667 
                  --------
668 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
669 
 
670 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_56:
671 
 
672 
   Name    Fanout   Delay (ns)          Site               Resource
673 
ROUTE       318     2.399       27.PADDI to    R12C10D.CLK clk40_i_c
674 
                  --------
675 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
676 
 
677 
 
678 
Error: The following path exceeds requirements by 23.922ns
679 
 
680 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
681 
 
682 
   Source:         FF         Q              cpu0/k_ind_ea[7]  (from clk40_i_c +)
683 
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)
684 
 
685 
   Delay:              32.712ns  (27.6% logic, 72.4% route), 18 logic levels.
686 
 
687 
 Constraint Details:
688 
 
689 
     32.712ns physical path delay SLICE_284 to cpu0/regs/SLICE_64 exceeds
690 
      8.956ns delay constraint less
691 
      0.000ns skew and
692 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.922ns
693 
 
694 
 Physical Path Details:
695 
 
696 
      Data path SLICE_284 to cpu0/regs/SLICE_64:
697 
 
698 
   Name    Fanout   Delay (ns)          Site               Resource
699 
REG_DEL     ---     0.452    R14C14A.CLK to     R14C14A.Q1 SLICE_284 (from clk40_i_c)
700 
ROUTE        26     3.767     R14C14A.Q1 to      R5C14B.A1 cpu0/k_ind_ea[7]
701 
CTOF_DEL    ---     0.495      R5C14B.A1 to      R5C14B.F1 cpu0/regs/ea/SLICE_877
702 
ROUTE        18     1.450      R5C14B.F1 to      R5C15D.A1 cpu0/regs/ea/N_62
703 
CTOF_DEL    ---     0.495      R5C15D.A1 to      R5C15D.F1 cpu0/regs/ea/SLICE_668
704 
ROUTE        18     1.939      R5C15D.F1 to      R6C15B.D1 cpu0/regs/ea/N_107
705 
CTOF_DEL    ---     0.495      R6C15B.D1 to      R6C15B.F1 cpu0/regs/ea/SLICE_876
706 
ROUTE        16     2.634      R6C15B.F1 to      R8C12C.A1 cpu0/regs/ea/un1_eapostbyte_12
707 
CTOF_DEL    ---     0.495      R8C12C.A1 to      R8C12C.F1 cpu0/regs/ea/SLICE_1211
708 
ROUTE         1     1.163      R8C12C.F1 to      R8C13D.C0 cpu0/regs/ea/N_77
709 
C0TOFCO_DE  ---     1.023      R8C13D.C0 to     R8C13D.FCO cpu0/regs/ea/SLICE_51
710 
ROUTE         1     0.000     R8C13D.FCO to     R8C14A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
711 
FCITOFCO_D  ---     0.162     R8C14A.FCI to     R8C14A.FCO cpu0/regs/ea/SLICE_50
712 
ROUTE         1     0.000     R8C14A.FCO to     R8C14B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
713 
FCITOFCO_D  ---     0.162     R8C14B.FCI to     R8C14B.FCO cpu0/regs/ea/SLICE_49
714 
ROUTE         1     0.000     R8C14B.FCO to     R8C14C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
715 
FCITOF0_DE  ---     0.585     R8C14C.FCI to      R8C14C.F0 cpu0/regs/ea/SLICE_48
716 
ROUTE         4     3.207      R8C14C.F0 to      R9C22A.A1 cpu0/regs/ea/regs_o_eamem_addr[11]
717 
CTOF_DEL    ---     0.495      R9C22A.A1 to      R9C22A.F1 cpu0/regs/ea/SLICE_1071
718 
ROUTE         1     1.193      R9C22A.F1 to      R9C25A.C0 cpu0/regs/ea/N_1327
719 
CTOF_DEL    ---     0.495      R9C25A.C0 to      R9C25A.F0 cpu0/SLICE_862
720 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
721 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
722 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
723 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
724 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
725 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
726 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
727 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
728 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
729 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
730 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
731 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
732 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
733 
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
734 
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
735 
                  --------
736 
                   32.712   (27.6% logic, 72.4% route), 18 logic levels.
737 
 
738 
 Clock Skew Details:
739 
 
740 
      Source Clock Path clk40_i to SLICE_284:
741 
 
742 
   Name    Fanout   Delay (ns)          Site               Resource
743 
ROUTE       318     2.399       27.PADDI to    R14C14A.CLK clk40_i_c
744 
                  --------
745 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
746 
 
747 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
748 
 
749 
   Name    Fanout   Delay (ns)          Site               Resource
750 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
751 
                  --------
752 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
753 
 
754 
 
755 
Error: The following path exceeds requirements by 23.913ns
756 
 
757 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
758 
 
759 
   Source:         FF         Q              cpu0/k_opcode[5]  (from clk40_i_c +)
760 
   Destination:    FF         Data in        cpu0/regs/SS[14]  (to clk40_i_c +)
761 
 
762 
   Delay:              32.703ns  (25.7% logic, 74.3% route), 17 logic levels.
763 
 
764 
 Constraint Details:
765 
 
766 
     32.703ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
767 
      8.956ns delay constraint less
768 
      0.000ns skew and
769 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.913ns
770 
 
771 
 Physical Path Details:
772 
 
773 
      Data path cpu0/SLICE_1144 to cpu0/regs/SLICE_64:
774 
 
775 
   Name    Fanout   Delay (ns)          Site               Resource
776 
REG_DEL     ---     0.452    R12C21A.CLK to     R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
777 
ROUTE        52     4.508     R12C21A.Q1 to     R19C22A.A0 cpu0/k_opcode[5]
778 
CTOF_DEL    ---     0.495     R19C22A.A0 to     R19C22A.F0 cpu0/SLICE_772
779 
ROUTE         2     1.308     R19C22A.F0 to     R18C24A.A0 cpu0/un1_k_opcode_3_4
780 
CTOF_DEL    ---     0.495     R18C24A.A0 to     R18C24A.F0 cpu0/dec_regs/SLICE_1118
781 
ROUTE         1     0.693     R18C24A.F0 to     R18C24B.B1 cpu0/dec_regs/path_left_addr79
782 
CTOF_DEL    ---     0.495     R18C24B.B1 to     R18C24B.F1 cpu0/dec_regs/SLICE_771
783 
ROUTE         1     0.964     R18C24B.F1 to     R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
784 
CTOF_DEL    ---     0.495     R17C24A.A1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
785 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
786 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
787 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
788 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
789 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
790 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
791 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
792 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
793 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
794 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
795 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
796 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
797 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
798 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
799 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
800 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
801 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
802 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
803 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
804 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
805 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
806 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
807 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
808 
FCITOF0_DE  ---     0.585    R11C13A.FCI to     R11C13A.F0 cpu0/regs/SLICE_64
809 
ROUTE         1     0.000     R11C13A.F0 to    R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
810 
                  --------
811 
                   32.703   (25.7% logic, 74.3% route), 17 logic levels.
812 
 
813 
 Clock Skew Details:
814 
 
815 
      Source Clock Path clk40_i to cpu0/SLICE_1144:
816 
 
817 
   Name    Fanout   Delay (ns)          Site               Resource
818 
ROUTE       318     2.399       27.PADDI to    R12C21A.CLK clk40_i_c
819 
                  --------
820 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
821 
 
822 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
823 
 
824 
   Name    Fanout   Delay (ns)          Site               Resource
825 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
826 
                  --------
827 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
828 
 
829 
Warning:  29.641MHz is the maximum frequency for this preference.
830 
 
831 
Report Summary
832 
--------------
833 
----------------------------------------------------------------------------
834 
Preference                              |   Constraint|       Actual|Levels
835 
----------------------------------------------------------------------------
836 
                                        |             |             |
837 
FREQUENCY NET "clk40_i_c" 111.645000    |             |             |
838 
MHz ;                                   |  111.645 MHz|   29.641 MHz|  18 *
839 
                                        |             |             |
840 
----------------------------------------------------------------------------
841 
 
842 
 
843 
1 preference(marked by "*" above) not met.
844 
 
845 
----------------------------------------------------------------------------
846 
Critical Nets                           |   Loads|  Errors| % of total
847 
----------------------------------------------------------------------------
848 
cpu0/dec_o_alu_size                     |      25|    3143|     76.73%
849 
                                        |        |        |
850 
cpu0/dec_o_left_path_addr[3]            |       5|    2799|     68.33%
851 
                                        |        |        |
852 
cpu0/dec_regs/un1_path_left_addr75_1    |       6|    2724|     66.50%
853 
                                        |        |        |
854 
cpu0/dec_regs/path_left_addr_2_sqmuxa   |       8|    2457|     59.99%
855 
                                        |        |        |
856 
cpu0/dec_regs/path_left_addr_o_sn_N_2   |       5|    2152|     52.54%
857 
                                        |        |        |
858 
cpu0/dec_regs/un1_path_left_addr85_1_0  |       2|    1902|     46.44%
859 
                                        |        |        |
860 
cpu0/dec_regs/un1_path_left_addr75_1_4  |       1|    1706|     41.65%
861 
                                        |        |        |
862 
cpu0/regs/SU_cry[9]                     |       1|    1283|     31.32%
863 
                                        |        |        |
864 
cpu0/dec_regs/un1_path_left_addr85_1_1_2|       1|    1267|     30.93%
865 
                                        |        |        |
866 
cpu0/regs/SS_cry[11]                    |       1|    1111|     27.12%
867 
                                        |        |        |
868 
cpu0/regs/SU_cry[5]                     |       1|    1107|     27.03%
869 
                                        |        |        |
870 
cpu0/state133_3                         |      13|    1096|     26.76%
871 
                                        |        |        |
872 
cpu0/regs/SU_cry[11]                    |       1|    1045|     25.51%
873 
                                        |        |        |
874 
cpu0/regs/SU_cry[7]                     |       1|    1024|     25.00%
875 
                                        |        |        |
876 
cpu0/regs/left_1[11]                    |       6|     955|     23.32%
877 
                                        |        |        |
878 
cpu0/datamux_o_dest[11]                 |       2|     955|     23.32%
879 
                                        |        |        |
880 
cpu0/k_opcode[7]                        |      42|     951|     23.22%
881 
                                        |        |        |
882 
cpu0/regs/SU_cry[3]                     |       1|     891|     21.75%
883 
                                        |        |        |
884 
cpu0/regs/ea/N_107                      |      18|     882|     21.53%
885 
                                        |        |        |
886 
cpu0/regs/ea/un1_eapostbyte_12          |      16|     864|     21.09%
887 
                                        |        |        |
888 
cpu0/regs/N_256                         |       1|     852|     20.80%
889 
                                        |        |        |
890 
cpu0/regs/SS_226_i1_mux                 |       1|     852|     20.80%
891 
                                        |        |        |
892 
cpu0/regs/SS_16[11]                     |       1|     852|     20.80%
893 
                                        |        |        |
894 
cpu0/regs/ea/eamem_addr_o_cry_8         |       1|     770|     18.80%
895 
                                        |        |        |
896 
cpu0/regs/SU_cry[13]                    |       1|     672|     16.41%
897 
                                        |        |        |
898 
cpu0/dec_regs/un1_path_left_addr75_1_0  |       1|     636|     15.53%
899 
                                        |        |        |
900 
cpu0/alu/k_cpu_addr_1_sqmuxa_1          |       1|     619|     15.11%
901 
                                        |        |        |
902 
cpu0/un1_cpu_reset_9                    |       4|     619|     15.11%
903 
                                        |        |        |
904 
cpu0/regs/ea/eamem_addr_o_cry_6         |       1|     616|     15.04%
905 
                                        |        |        |
906 
cpu0/un1_state_116                      |      16|     615|     15.01%
907 
                                        |        |        |
908 
cpu0/regs/SS_cry[13]                    |       1|     612|     14.94%
909 
                                        |        |        |
910 
cpu0/dec_regs/un1_path_left_addr85_1_1_1|       1|     588|     14.36%
911 
                                        |        |        |
912 
cpu0/regs/left_1[2]                     |       9|     585|     14.28%
913 
                                        |        |        |
914 
cpu0/datamux_o_dest[2]                  |       2|     585|     14.28%
915 
                                        |        |        |
916 
cpu0/dec_regs/path_left_addr79          |       1|     583|     14.23%
917 
                                        |        |        |
918 
cpu0/regs/ea/N_62                       |      18|     576|     14.06%
919 
                                        |        |        |
920 
cpu0/regs/N_283                         |       1|     545|     13.31%
921 
                                        |        |        |
922 
cpu0/regs/SU_201_i1_mux                 |       1|     545|     13.31%
923 
                                        |        |        |
924 
cpu0/regs/SU_16[2]                      |       1|     545|     13.31%
925 
                                        |        |        |
926 
cpu0/k_opcode[1]                        |      61|     537|     13.11%
927 
                                        |        |        |
928 
cpu0/datamux_o_dest[9]                  |       2|     525|     12.82%
929 
                                        |        |        |
930 
cpu0/regs/left_1[9]                     |       6|     525|     12.82%
931 
                                        |        |        |
932 
cpu0/regs/left_1[3]                     |       9|     502|     12.26%
933 
                                        |        |        |
934 
cpu0/datamux_o_dest[3]                  |       2|     502|     12.26%
935 
                                        |        |        |
936 
cpu0/un1_k_opcode_3_4                   |       2|     499|     12.18%
937 
                                        |        |        |
938 
cpu0/un1_k_cpu_addr_1_cry_8             |       1|     472|     11.52%
939 
                                        |        |        |
940 
cpu0/k_opcode[5]                        |      52|     469|     11.45%
941 
                                        |        |        |
942 
cpu0/regs/SS_cry[5]                     |       1|     463|     11.30%
943 
                                        |        |        |
944 
cpu0/un1_k_cpu_addr_1_cry_10            |       1|     459|     11.21%
945 
                                        |        |        |
946 
cpu0/regs/ea/eamem_addr_o_cry_10        |       1|     450|     10.99%
947 
                                        |        |        |
948 
cpu0/regs/N_290                         |       1|     445|     10.86%
949 
                                        |        |        |
950 
cpu0/regs/SU_208_i1_mux                 |       1|     445|     10.86%
951 
                                        |        |        |
952 
cpu0/regs/SU_16[9]                      |       1|     445|     10.86%
953 
                                        |        |        |
954 
cpu0/un1_k_cpu_addr_1_cry_6             |       1|     444|     10.84%
955 
                                        |        |        |
956 
cpu0/regs/SS_cry[9]                     |       1|     437|     10.67%
957 
                                        |        |        |
958 
cpu0/regs/SS_cry[7]                     |       1|     424|     10.35%
959 
                                        |        |        |
960 
cpu0/alu/mulu/N_1325                    |       1|     419|     10.23%
961 
                                        |        |        |
962 
----------------------------------------------------------------------------
963 
 
964 
 
965 
Clock Domains Analysis
966 
------------------------
967 
 
968 
Found 1 clocks:
969 
 
970 
Clock Domain: clk40_i_c   Source: clk40_i.PAD   Loads: 318
971 
   Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
972 
 
973 
 
974 
Timing summary (Setup):
975 
---------------
976 
 
977 
Timing errors: 4096  Score: 88089612
978 
Cumulative negative slack: 88089612
979 
 
980 
Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)
981 
 
982 
--------------------------------------------------------------------------------
983 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.1.0.96
984 
Sun Jul 06 07:47:16 2014
985 
 
986 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
987 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
988 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
989 
Copyright (c) 2001 Agere Systems   All rights reserved.
990 
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.
991 
 
992 
Report Information
993 
------------------
994 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf
995 
Design file:     p6809_p6809.ncd
996 
Preference file: p6809_p6809.prf
997 
Device,speed:    LCMXO2-7000HE,m
998 
Report level:    verbose report, limited to 10 items per preference
999 
--------------------------------------------------------------------------------
1000 
 
1001 
BLOCK ASYNCPATHS
1002 
BLOCK RESETPATHS
1003 
--------------------------------------------------------------------------------
1004 
 
1005 
 
1006 
 
1007 
================================================================================
1008 
Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
1009 
            4096 items scored, 0 timing errors detected.
1010 
--------------------------------------------------------------------------------
1011 
 
1012 
 
1013 
Passed: The following path meets requirements by 0.199ns
1014 
 
1015 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1016 
 
1017 
   Source:         FF         Q              textctrl/chars_data[1]  (from clk40_i_c +)
1018 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1019 
 
1020 
   Delay:               0.304ns  (43.1% logic, 56.9% route), 1 logic levels.
1021 
 
1022 
 Constraint Details:
1023 
 
1024 
      0.304ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
1025 
      0.052ns ADDR_HLD and
1026 
      0.000ns delay constraint less
1027 
     -0.053ns skew requirement (totaling 0.105ns) by 0.199ns
1028 
 
1029 
 Physical Path Details:
1030 
 
1031 
      Data path SLICE_412 to textctrl/font/fontrom_0_0_3:
1032 
 
1033 
   Name    Fanout   Delay (ns)          Site               Resource
1034 
REG_DEL     ---     0.131    R18C28D.CLK to     R18C28D.Q1 SLICE_412 (from clk40_i_c)
1035 
ROUTE         4     0.173     R18C28D.Q1 to *R_R20C27.ADA6 textctrl/chars_data[1] (to clk40_i_c)
1036 
                  --------
1037 
                    0.304   (43.1% logic, 56.9% route), 1 logic levels.
1038 
 
1039 
 Clock Skew Details:
1040 
 
1041 
      Source Clock Path clk40_i to SLICE_412:
1042 
 
1043 
   Name    Fanout   Delay (ns)          Site               Resource
1044 
ROUTE       318     0.846       27.PADDI to    R18C28D.CLK clk40_i_c
1045 
                  --------
1046 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1047 
 
1048 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1049 
 
1050 
   Name    Fanout   Delay (ns)          Site               Resource
1051 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1052 
                  --------
1053 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1054 
 
1055 
 
1056 
Passed: The following path meets requirements by 0.216ns
1057 
 
1058 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1059 
 
1060 
   Source:         FF         Q              textctrl/line_cnt[3]  (from clk40_i_c +)
1061 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to clk40_i_c +)
1062 
 
1063 
   Delay:               0.339ns  (38.6% logic, 61.4% route), 1 logic levels.
1064 
 
1065 
 Constraint Details:
1066 
 
1067 
      0.339ns physical path delay textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0 meets
1068 
      0.052ns ADDR_HLD and
1069 
      0.000ns delay constraint less
1070 
     -0.071ns skew requirement (totaling 0.123ns) by 0.216ns
1071 
 
1072 
 Physical Path Details:
1073 
 
1074 
      Data path textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0:
1075 
 
1076 
   Name    Fanout   Delay (ns)          Site               Resource
1077 
REG_DEL     ---     0.131    R22C26B.CLK to     R22C26B.Q1 textctrl/SLICE_421 (from clk40_i_c)
1078 
ROUTE         7     0.208     R22C26B.Q1 to *R_R20C24.ADA4 textctrl/line_cnt[3] (to clk40_i_c)
1079 
                  --------
1080 
                    0.339   (38.6% logic, 61.4% route), 1 logic levels.
1081 
 
1082 
 Clock Skew Details:
1083 
 
1084 
      Source Clock Path clk40_i to textctrl/SLICE_421:
1085 
 
1086 
   Name    Fanout   Delay (ns)          Site               Resource
1087 
ROUTE       318     0.828       27.PADDI to    R22C26B.CLK clk40_i_c
1088 
                  --------
1089 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1090 
 
1091 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
1092 
 
1093 
   Name    Fanout   Delay (ns)          Site               Resource
1094 
ROUTE       318     0.899       27.PADDI to *R_R20C24.CLKA clk40_i_c
1095 
                  --------
1096 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1097 
 
1098 
 
1099 
Passed: The following path meets requirements by 0.277ns
1100 
 
1101 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1102 
 
1103 
   Source:         FF         Q              textctrl/chars_data[0]  (from clk40_i_c +)
1104 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1105 
 
1106 
   Delay:               0.382ns  (34.3% logic, 65.7% route), 1 logic levels.
1107 
 
1108 
 Constraint Details:
1109 
 
1110 
      0.382ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
1111 
      0.052ns ADDR_HLD and
1112 
      0.000ns delay constraint less
1113 
     -0.053ns skew requirement (totaling 0.105ns) by 0.277ns
1114 
 
1115 
 Physical Path Details:
1116 
 
1117 
      Data path SLICE_412 to textctrl/font/fontrom_0_0_3:
1118 
 
1119 
   Name    Fanout   Delay (ns)          Site               Resource
1120 
REG_DEL     ---     0.131    R18C28D.CLK to     R18C28D.Q0 SLICE_412 (from clk40_i_c)
1121 
ROUTE         4     0.251     R18C28D.Q0 to *R_R20C27.ADA5 textctrl/chars_data[0] (to clk40_i_c)
1122 
                  --------
1123 
                    0.382   (34.3% logic, 65.7% route), 1 logic levels.
1124 
 
1125 
 Clock Skew Details:
1126 
 
1127 
      Source Clock Path clk40_i to SLICE_412:
1128 
 
1129 
   Name    Fanout   Delay (ns)          Site               Resource
1130 
ROUTE       318     0.846       27.PADDI to    R18C28D.CLK clk40_i_c
1131 
                  --------
1132 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1133 
 
1134 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1135 
 
1136 
   Name    Fanout   Delay (ns)          Site               Resource
1137 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1138 
                  --------
1139 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1140 
 
1141 
 
1142 
Passed: The following path meets requirements by 0.294ns
1143 
 
1144 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1145 
 
1146 
   Source:         FF         Q              cpu0/k_cpu_addr[0]  (from clk40_i_c +)
1147 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)
1148 
 
1149 
   Delay:               0.418ns  (31.3% logic, 68.7% route), 1 logic levels.
1150 
 
1151 
 Constraint Details:
1152 
 
1153 
      0.418ns physical path delay cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1 meets
1154 
      0.071ns ADDR_HLD and
1155 
      0.000ns delay constraint less
1156 
     -0.053ns skew requirement (totaling 0.124ns) by 0.294ns
1157 
 
1158 
 Physical Path Details:
1159 
 
1160 
      Data path cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1:
1161 
 
1162 
   Name    Fanout   Delay (ns)          Site               Resource
1163 
REG_DEL     ---     0.131    R16C14C.CLK to     R16C14C.Q0 cpu0/SLICE_183 (from clk40_i_c)
1164 
ROUTE        11     0.287     R16C14C.Q0 to *R_R13C13.ADB1 addr_o_c[0] (to clk40_i_c)
1165 
                  --------
1166 
                    0.418   (31.3% logic, 68.7% route), 1 logic levels.
1167 
 
1168 
 Clock Skew Details:
1169 
 
1170 
      Source Clock Path clk40_i to cpu0/SLICE_183:
1171 
 
1172 
   Name    Fanout   Delay (ns)          Site               Resource
1173 
ROUTE       318     0.846       27.PADDI to    R16C14C.CLK clk40_i_c
1174 
                  --------
1175 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1176 
 
1177 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1178 
 
1179 
   Name    Fanout   Delay (ns)          Site               Resource
1180 
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
1181 
                  --------
1182 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1183 
 
1184 
 
1185 
Passed: The following path meets requirements by 0.302ns
1186 
 
1187 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1188 
 
1189 
   Source:         FF         Q              textctrl/chars_data[7]  (from clk40_i_c +)
1190 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1191 
 
1192 
   Delay:               0.407ns  (32.2% logic, 67.8% route), 1 logic levels.
1193 
 
1194 
 Constraint Details:
1195 
 
1196 
      0.407ns physical path delay SLICE_415 to textctrl/font/fontrom_0_0_3 meets
1197 
      0.052ns ADDR_HLD and
1198 
      0.000ns delay constraint less
1199 
     -0.053ns skew requirement (totaling 0.105ns) by 0.302ns
1200 
 
1201 
 Physical Path Details:
1202 
 
1203 
      Data path SLICE_415 to textctrl/font/fontrom_0_0_3:
1204 
 
1205 
   Name    Fanout   Delay (ns)          Site               Resource
1206 
REG_DEL     ---     0.131    R16C28A.CLK to     R16C28A.Q1 SLICE_415 (from clk40_i_c)
1207 
ROUTE         4     0.276     R16C28A.Q1 to *_R20C27.ADA12 textctrl/chars_data[7] (to clk40_i_c)
1208 
                  --------
1209 
                    0.407   (32.2% logic, 67.8% route), 1 logic levels.
1210 
 
1211 
 Clock Skew Details:
1212 
 
1213 
      Source Clock Path clk40_i to SLICE_415:
1214 
 
1215 
   Name    Fanout   Delay (ns)          Site               Resource
1216 
ROUTE       318     0.846       27.PADDI to    R16C28A.CLK clk40_i_c
1217 
                  --------
1218 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1219 
 
1220 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1221 
 
1222 
   Name    Fanout   Delay (ns)          Site               Resource
1223 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1224 
                  --------
1225 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1226 
 
1227 
 
1228 
Passed: The following path meets requirements by 0.314ns
1229 
 
1230 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1231 
 
1232 
   Source:         FF         Q              cpu0/k_cpu_addr[6]  (from clk40_i_c +)
1233 
   Destination:    DP8KC      Port           bios/bios2k_0_1_0(ASIC)  (to clk40_i_c +)
1234 
 
1235 
   Delay:               0.419ns  (31.3% logic, 68.7% route), 1 logic levels.
1236 
 
1237 
 Constraint Details:
1238 
 
1239 
      0.419ns physical path delay cpu0/SLICE_186 to bios/bios2k_0_1_0 meets
1240 
      0.052ns ADDR_HLD and
1241 
      0.000ns delay constraint less
1242 
     -0.053ns skew requirement (totaling 0.105ns) by 0.314ns
1243 
 
1244 
 Physical Path Details:
1245 
 
1246 
      Data path cpu0/SLICE_186 to bios/bios2k_0_1_0:
1247 
 
1248 
   Name    Fanout   Delay (ns)          Site               Resource
1249 
REG_DEL     ---     0.131    R15C12A.CLK to     R15C12A.Q0 cpu0/SLICE_186 (from clk40_i_c)
1250 
ROUTE         8     0.288     R15C12A.Q0 to *R_R13C10.ADA8 addr_o_c[6] (to clk40_i_c)
1251 
                  --------
1252 
                    0.419   (31.3% logic, 68.7% route), 1 logic levels.
1253 
 
1254 
 Clock Skew Details:
1255 
 
1256 
      Source Clock Path clk40_i to cpu0/SLICE_186:
1257 
 
1258 
   Name    Fanout   Delay (ns)          Site               Resource
1259 
ROUTE       318     0.846       27.PADDI to    R15C12A.CLK clk40_i_c
1260 
                  --------
1261 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1262 
 
1263 
      Destination Clock Path clk40_i to bios/bios2k_0_1_0:
1264 
 
1265 
   Name    Fanout   Delay (ns)          Site               Resource
1266 
ROUTE       318     0.899       27.PADDI to *R_R13C10.CLKA clk40_i_c
1267 
                  --------
1268 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1269 
 
1270 
 
1271 
Passed: The following path meets requirements by 0.322ns
1272 
 
1273 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1274 
 
1275 
   Source:         FF         Q              cpu0/k_cpu_addr[5]  (from clk40_i_c +)
1276 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)
1277 
 
1278 
   Delay:               0.446ns  (29.4% logic, 70.6% route), 1 logic levels.
1279 
 
1280 
 Constraint Details:
1281 
 
1282 
      0.446ns physical path delay cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1 meets
1283 
      0.071ns ADDR_HLD and
1284 
      0.000ns delay constraint less
1285 
     -0.053ns skew requirement (totaling 0.124ns) by 0.322ns
1286 
 
1287 
 Physical Path Details:
1288 
 
1289 
      Data path cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1:
1290 
 
1291 
   Name    Fanout   Delay (ns)          Site               Resource
1292 
REG_DEL     ---     0.131    R16C13D.CLK to     R16C13D.Q1 cpu0/SLICE_185 (from clk40_i_c)
1293 
ROUTE         9     0.315     R16C13D.Q1 to *R_R13C13.ADB6 addr_o_c[5] (to clk40_i_c)
1294 
                  --------
1295 
                    0.446   (29.4% logic, 70.6% route), 1 logic levels.
1296 
 
1297 
 Clock Skew Details:
1298 
 
1299 
      Source Clock Path clk40_i to cpu0/SLICE_185:
1300 
 
1301 
   Name    Fanout   Delay (ns)          Site               Resource
1302 
ROUTE       318     0.846       27.PADDI to    R16C13D.CLK clk40_i_c
1303 
                  --------
1304 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1305 
 
1306 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1307 
 
1308 
   Name    Fanout   Delay (ns)          Site               Resource
1309 
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
1310 
                  --------
1311 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1312 
 
1313 
 
1314 
Passed: The following path meets requirements by 0.326ns
1315 
 
1316 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1317 
 
1318 
   Source:         FF         Q              textctrl/line_cnt[1]  (from clk40_i_c +)
1319 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1320 
 
1321 
   Delay:               0.449ns  (29.2% logic, 70.8% route), 1 logic levels.
1322 
 
1323 
 Constraint Details:
1324 
 
1325 
      0.449ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3 meets
1326 
      0.052ns ADDR_HLD and
1327 
      0.000ns delay constraint less
1328 
     -0.071ns skew requirement (totaling 0.123ns) by 0.326ns
1329 
 
1330 
 Physical Path Details:
1331 
 
1332 
      Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3:
1333 
 
1334 
   Name    Fanout   Delay (ns)          Site               Resource
1335 
REG_DEL     ---     0.131    R22C27D.CLK to     R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
1336 
ROUTE         9     0.318     R22C27D.Q1 to *R_R20C27.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
1337 
                  --------
1338 
                    0.449   (29.2% logic, 70.8% route), 1 logic levels.
1339 
 
1340 
 Clock Skew Details:
1341 
 
1342 
      Source Clock Path clk40_i to textctrl/SLICE_420:
1343 
 
1344 
   Name    Fanout   Delay (ns)          Site               Resource
1345 
ROUTE       318     0.828       27.PADDI to    R22C27D.CLK clk40_i_c
1346 
                  --------
1347 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1348 
 
1349 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1350 
 
1351 
   Name    Fanout   Delay (ns)          Site               Resource
1352 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1353 
                  --------
1354 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1355 
 
1356 
 
1357 
Passed: The following path meets requirements by 0.326ns
1358 
 
1359 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1360 
 
1361 
   Source:         FF         Q              cpu0/k_cpu_addr[9]  (from clk40_i_c +)
1362 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)
1363 
 
1364 
   Delay:               0.450ns  (29.1% logic, 70.9% route), 1 logic levels.
1365 
 
1366 
 Constraint Details:
1367 
 
1368 
      0.450ns physical path delay cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1 meets
1369 
      0.071ns ADDR_HLD and
1370 
      0.000ns delay constraint less
1371 
     -0.053ns skew requirement (totaling 0.124ns) by 0.326ns
1372 
 
1373 
 Physical Path Details:
1374 
 
1375 
      Data path cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1:
1376 
 
1377 
   Name    Fanout   Delay (ns)          Site               Resource
1378 
REG_DEL     ---     0.131    R15C12B.CLK to     R15C12B.Q1 cpu0/SLICE_187 (from clk40_i_c)
1379 
ROUTE         8     0.319     R15C12B.Q1 to *_R13C13.ADB10 addr_o_c[9] (to clk40_i_c)
1380 
                  --------
1381 
                    0.450   (29.1% logic, 70.9% route), 1 logic levels.
1382 
 
1383 
 Clock Skew Details:
1384 
 
1385 
      Source Clock Path clk40_i to cpu0/SLICE_187:
1386 
 
1387 
   Name    Fanout   Delay (ns)          Site               Resource
1388 
ROUTE       318     0.846       27.PADDI to    R15C12B.CLK clk40_i_c
1389 
                  --------
1390 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1391 
 
1392 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1393 
 
1394 
   Name    Fanout   Delay (ns)          Site               Resource
1395 
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
1396 
                  --------
1397 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1398 
 
1399 
 
1400 
Passed: The following path meets requirements by 0.328ns
1401 
 
1402 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1403 
 
1404 
   Source:         FF         Q              textctrl/line_cnt[1]  (from clk40_i_c +)
1405 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to clk40_i_c +)
1406 
 
1407 
   Delay:               0.451ns  (29.0% logic, 71.0% route), 1 logic levels.
1408 
 
1409 
 Constraint Details:
1410 
 
1411 
      0.451ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0 meets
1412 
      0.052ns ADDR_HLD and
1413 
      0.000ns delay constraint less
1414 
     -0.071ns skew requirement (totaling 0.123ns) by 0.328ns
1415 
 
1416 
 Physical Path Details:
1417 
 
1418 
      Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0:
1419 
 
1420 
   Name    Fanout   Delay (ns)          Site               Resource
1421 
REG_DEL     ---     0.131    R22C27D.CLK to     R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
1422 
ROUTE         9     0.320     R22C27D.Q1 to *R_R20C24.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
1423 
                  --------
1424 
                    0.451   (29.0% logic, 71.0% route), 1 logic levels.
1425 
 
1426 
 Clock Skew Details:
1427 
 
1428 
      Source Clock Path clk40_i to textctrl/SLICE_420:
1429 
 
1430 
   Name    Fanout   Delay (ns)          Site               Resource
1431 
ROUTE       318     0.828       27.PADDI to    R22C27D.CLK clk40_i_c
1432 
                  --------
1433 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1434 
 
1435 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
1436 
 
1437 
   Name    Fanout   Delay (ns)          Site               Resource
1438 
ROUTE       318     0.899       27.PADDI to *R_R20C24.CLKA clk40_i_c
1439 
                  --------
1440 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1441 
 
1442 
Report Summary
1443 
--------------
1444 
----------------------------------------------------------------------------
1445 
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
1446 
----------------------------------------------------------------------------
1447 
                                        |             |             |
1448 
FREQUENCY NET "clk40_i_c" 111.645000    |             |             |
1449 
MHz ;                                   |     0.000 ns|     0.199 ns|   1
1450 
                                        |             |             |
1451 
----------------------------------------------------------------------------
1452 
 
1453 
 
1454 
All preferences were met.
1455 
 
1456 
 
1457 
Clock Domains Analysis
1458 
------------------------
1459 
 
1460 
Found 1 clocks:
1461 
 
1462 
Clock Domain: clk40_i_c   Source: clk40_i.PAD   Loads: 318
1463 
   Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
1464 
 
1465 
 
1466 
Timing summary (Hold):
1467 
---------------
1468 
 
1469 
Timing errors: 0  Score: 0
1470 
Cumulative negative slack: 0
1471 
 
1472 
Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)
1473 
 
1474 
 
1475 
 
1476 
Timing summary (Setup and Hold):
1477 
---------------
1478 
 
1479 
Timing errors: 4096 (setup), 0 (hold)
1480 
Score: 88089612 (setup), 0 (hold)
1481 
Cumulative negative slack: 88089612 (88089612+0)
1482 
--------------------------------------------------------------------------------
1483 
 
1484 
--------------------------------------------------------------------------------
1485 
 

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